ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)

When decoding a srs instruction, invalid mode encoding returns invalid instruction.
This can happen when garbage instructions are fetched from mispredicted path

7 files changed, 28 insertions, 6 deletions

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index ec36ff751..d8752d520 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -101,7 +101,8 @@ enum DependenceTags {
     // 0..31 are the integer regs 0..31
     // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
     FP_Base_DepTag = 40,
-    Ctrl_Base_DepTag = 72
+    Ctrl_Base_DepTag = 72,
+    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 444e979fb..a568e4a9c 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
  *
@@ -59,9 +71,9 @@ const int NumFloatSpecialRegs = 8;
 
 const int NumIntRegs = NUM_INTREGS;
 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-
 const int NumMiscRegs = NUM_MISCREGS;
 
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
 // semantically meaningful register indices
 const int ReturnValueReg = 0;
@@ -85,6 +97,7 @@ const int SyscallSuccessReg = ReturnValueReg;
 // These help enumerate all the registers for dependence tracking.
 const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
 
 typedef union {
     IntReg   intreg;
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 5cf76634d..dce7858bf 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -283,6 +283,7 @@ enum MiscRegIndex{
 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
 const int NumMiscRegs = MISCREG_NUMREGS;
+const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 5bcca3641..59816a599 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -82,6 +82,7 @@ const int SyscallSuccessReg = 3;
 // These help enumerate all the registers for dependence tracking.
 const int FP_Base_DepTag = NumIntRegs;
 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
 
 typedef union {
     IntReg   intreg;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 639b7a487..cf9f54b59 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -58,7 +58,8 @@ namespace SparcISA
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
         FP_Base_DepTag = 32*3+9,
-        Ctrl_Base_DepTag = FP_Base_DepTag + 64
+        Ctrl_Base_DepTag = FP_Base_DepTag + 64,
+        Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
     };
 
     // semantically meaningful register indices
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index e14b9a1ba..ea737fa63 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -76,7 +76,8 @@ enum DependenceTags {
         //The microcode fp registers
         8 +
         //The indices that are mapped over the fp stack
-        8
+        8,
+    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
 };
 
 // semantically meaningful register indices
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index ce206435c..7f796c4c8 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -966,9 +966,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
             src_reg = src_reg - TheISA::FP_Base_DepTag;
             flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
             flat_src_reg += TheISA::NumIntRegs;
-        } else {
+        } else if (src_reg < TheISA::Max_DepTag) {
             flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
+        } else {
+            panic("Reg index is out of bound: %d.", src_reg);
         }
 
         inst->flattenSrcReg(src_idx, flat_src_reg);
@@ -1012,11 +1014,13 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
             // Integer registers are flattened.
             flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
-        } else {
+        } else if (dest_reg < TheISA::Max_DepTag) {
             // Floating point and Miscellaneous registers need their indexes
             // adjusted to account for the expanded number of flattened int regs.
             flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
+        } else {
+            panic("Reg index is out of bound: %d.", dest_reg);
         }
 
         inst->flattenDestReg(dest_idx, flat_dest_reg);