diff options
| author | Korey Sewell <ksewell@umich.edu> | 2010-06-23 18:21:44 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-06-23 18:21:44 -0400 |
| commit | e17c41c17692dd6bc50bc0a564e5655b6fa8b8fa (patch) | |
| tree | 65578cde64d8404ec021e9a970f4052ab9d76164 | |
| parent | 1f778b3583be6b8166d11cb6d19480aaab3f3539 (diff) | |
| download | gem5-e17c41c17692dd6bc50bc0a564e5655b6fa8b8fa.tar.xz | |
inorder: update regressions
8 files changed, 519 insertions, 512 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 19b19681f..aadbb6853 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:54:51 -M5 executing on zizzer +M5 compiled Jun 23 2010 16:05:32 +M5 revision f157e4974de9+ 7462+ default qtip inorder_update_regr tip +M5 started Jun 23 2010 16:57:34 +M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index f3687e9fd..108e63d44 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 55482 # Simulator instruction rate (inst/s) -host_mem_usage 223108 # Number of bytes of host memory used -host_seconds 1592.24 # Real time elapsed on the host -host_tick_rate 66617861 # Simulator tick rate (ticks/s) +host_inst_rate 51467 # Simulator instruction rate (inst/s) +host_mem_usage 168500 # Number of bytes of host memory used +host_seconds 1716.45 # Real time elapsed on the host +host_tick_rate 61684615 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.106071 # Number of seconds simulated -sim_ticks 106071426500 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 4715785 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 11658962 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1659877 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 10683155 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 8920904 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 13755709 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 5728293 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8027416 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1659877 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.cyclesExecuted 53070972 # Number of Cycles Execution Unit was used. -system.cpu.Execution-Unit.instReqsProcessed 53075554 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 393312 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 2262427 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.250166 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 187375293 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 88340673 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. -system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 165543836 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 85.696841 # Percentage of cycles cpu is active +sim_seconds 0.105878 # Number of seconds simulated +sim_ticks 105878306500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 40.484338 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 4662108 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 11515831 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 1659774 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 2359487 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 8920848 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 13754477 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 5781163 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 7973314 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 1659774 # Number of times the RAS was used to get a target. +system.cpu.Execution-Unit.executions 53075554 # Number of Instructions Executed. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 485820 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 1873667 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed +system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed +system.cpu.RegFile-Manager.regFileAccesses 156428919 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 103882038 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File +system.cpu.RegFile-Manager.regForwards 2136327 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 85.568977 # Percentage of cycles cpu is active +system.cpu.comBranches 13754477 # Number of Branches instructions committed +system.cpu.comFloats 151453 # Number of Floating Point instructions committed +system.cpu.comInts 30457224 # Number of Integer instructions committed +system.cpu.comLoads 20379399 # Number of Load instructions committed +system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed +system.cpu.comNops 8748916 # Number of Nop instructions committed +system.cpu.comStores 14844619 # Number of Store instructions committed system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.401417 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.401418 # CPI: Total CPI of All Threads +system.cpu.cpi 2.397046 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.397046 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38148.092683 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35044.037784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38170.794523 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35065.488925 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2318107000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2319486500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2129486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2130789500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56431.835934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53431.835934 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56329.688303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53329.688303 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8453094000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8437793000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8003715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7988414000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +70,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 51155.262895 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 51089.146035 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 48058.755503 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10771201000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10757279500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10133201000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10119203500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995316 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.814935 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995318 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.822350 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 51155.262895 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 51089.146035 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 48058.755503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679456 # number of overall hits -system.cpu.dcache.overall_miss_latency 10771201000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10757279500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10133201000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10119203500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,11 +102,10 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.814935 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.822350 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 843108000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 841843000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.data_accesses 34987415 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 34890015 # DTB hits @@ -119,74 +122,73 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 99022487 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18976.095303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15795.359051 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 98940181 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1561846500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000831 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 82306 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1244311000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000796 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 78777 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 98672431 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 19067.834064 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15854.703492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 98591653 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1540261500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000819 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 80778 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3006 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1233052000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000788 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 77772 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1255.952638 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 800 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1267.701139 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 32000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 99022487 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18976.095303 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency -system.cpu.icache.demand_hits 98940181 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1561846500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000831 # miss rate for demand accesses -system.cpu.icache.demand_misses 82306 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1244311000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 78777 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 98672431 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 19067.834064 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15854.703492 # average overall mshr miss latency +system.cpu.icache.demand_hits 98591653 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1540261500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000819 # miss rate for demand accesses +system.cpu.icache.demand_misses 80778 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3006 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1233052000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000788 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 77772 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.914772 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1873.453452 # Average occupied blocks per context -system.cpu.icache.overall_accesses 99022487 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18976.095303 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.914796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1873.502207 # Average occupied blocks per context +system.cpu.icache.overall_accesses 98672431 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 19067.834064 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15854.703492 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 98940181 # number of overall hits -system.cpu.icache.overall_miss_latency 1561846500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000831 # miss rate for overall accesses -system.cpu.icache.overall_misses 82306 # number of overall misses -system.cpu.icache.overall_mshr_hits 3529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1244311000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 78777 # number of overall MSHR misses +system.cpu.icache.overall_hits 98591653 # number of overall hits +system.cpu.icache.overall_miss_latency 1540261500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000819 # miss rate for overall accesses +system.cpu.icache.overall_misses 80778 # number of overall misses +system.cpu.icache.overall_mshr_hits 3006 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1233052000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000788 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 77772 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 76731 # number of replacements -system.cpu.icache.sampled_refs 78777 # Sample count of references to valid blocks. +system.cpu.icache.replacements 75726 # number of replacements +system.cpu.icache.sampled_refs 77772 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1873.453452 # Cycle average of tags in use -system.cpu.icache.total_refs 98940181 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1873.502207 # Cycle average of tags in use +system.cpu.icache.total_refs 98591653 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 99022707 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 30343130 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.416421 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.416421 # IPC: Total IPC of All Threads +system.cpu.idleCycles 30558645 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.417180 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.417180 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 99026503 # ITB accesses +system.cpu.itb.fetch_accesses 98676443 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 99022489 # ITB hits -system.cpu.itb.fetch_misses 4014 # ITB misses +system.cpu.itb.fetch_hits 98672432 # ITB hits +system.cpu.itb.fetch_misses 4011 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -196,105 +198,104 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52441.606653 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.219393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7529461000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52334.072769 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226358 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7514021500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743151500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743152500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 139543 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52270.364151 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.968830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 96072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2272245000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.311524 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43471 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1739056000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.311524 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43471 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 138538 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52300.064414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.819527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 95069 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2273431500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.313770 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43469 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1738969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43469 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51886.725664 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322476000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51908.527755 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.815768 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 322611500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248617500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.642732 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.636939 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 283121 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52401.809152 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 96072 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9801706000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.660668 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 187049 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 282116 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52326.169359 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.293792 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 95069 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9787453000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.663015 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 187047 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7482207500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.660668 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 187049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7482122000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.663015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 187047 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.083121 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.474053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2723.703646 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15533.764861 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 283121 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52401.809152 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.083104 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.474046 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2723.143012 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15533.530659 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 282116 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52326.169359 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.293792 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 96072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9801706000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.660668 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 187049 # number of overall misses +system.cpu.l2cache.overall_hits 95069 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9787453000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.663015 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 187047 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7482207500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.660668 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 187049 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7482122000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.663015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 187047 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 147734 # number of replacements -system.cpu.l2cache.sampled_refs 172940 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147732 # number of replacements +system.cpu.l2cache.sampled_refs 172938 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18257.468506 # Cycle average of tags in use -system.cpu.l2cache.total_refs 111154 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18256.673671 # Cycle average of tags in use +system.cpu.l2cache.total_refs 110151 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120636 # number of writebacks -system.cpu.numCycles 212142855 # number of cpu cycles simulated -system.cpu.runCycles 181799725 # Number of cycles cpu stages are processed. +system.cpu.numCycles 211756614 # number of cpu cycles simulated +system.cpu.runCycles 181197969 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 113116352 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 99026503 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 46.679160 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 123790270 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 88352585 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 41.647684 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 122327069 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 113080171 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 98676443 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 46.598990 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 123406302 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 88350312 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 41.722575 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 121940828 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 42.337408 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 176911585 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 42.414631 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 176525344 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.607333 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 123802182 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 16.637624 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 123415941 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 41.642069 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 212142815 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.stage-4.utilization 41.718023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 211756614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index c38fd9b15..99f0a770b 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:53:58 -M5 executing on zizzer +M5 compiled Jun 23 2010 16:05:32 +M5 revision f157e4974de9+ 7462+ default qtip inorder_update_regr tip +M5 started Jun 23 2010 17:31:47 +M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index bfc24ccd9..064ca5d45 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58773 # Simulator instruction rate (inst/s) -host_mem_usage 210528 # Number of bytes of host memory used -host_seconds 1563.70 # Real time elapsed on the host -host_tick_rate 63236927 # Simulator tick rate (ticks/s) +host_inst_rate 54041 # Simulator instruction rate (inst/s) +host_mem_usage 157904 # Number of bytes of host memory used +host_seconds 1700.61 # Real time elapsed on the host +host_tick_rate 58028620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098884 # Number of seconds simulated -sim_ticks 98883816000 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 5701477 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 8843835 # Number of BTB lookups +sim_seconds 0.098684 # Number of seconds simulated +sim_ticks 98684146000 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 63.856280 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 5483107 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 8586637 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 1029596 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 11272469 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7465254 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 10241221 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 2498039 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 7743182 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.condIncorrect 3205078 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 7465012 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 10240685 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 2715877 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 7524808 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.cyclesExecuted 64907308 # Number of Cycles Execution Unit was used. -system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 267967 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 3261320 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.328200 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 195278137 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. -system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 196150546 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 96.104408 # Percentage of cycles cpu is active +system.cpu.Execution-Unit.executions 64907696 # Number of Instructions Executed. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 357110 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 2847968 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed +system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed +system.cpu.RegFile-Manager.regFileAccesses 185972249 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 117544888 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File +system.cpu.RegFile-Manager.regForwards 2843109 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 95.924038 # Percentage of cycles cpu is active +system.cpu.comBranches 10240685 # Number of Branches instructions committed +system.cpu.comFloats 3775974 # Number of Floating Point instructions committed +system.cpu.comInts 43625545 # Number of Integer instructions committed +system.cpu.comLoads 20034413 # Number of Load instructions committed +system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed +system.cpu.comNops 7723346 # Number of Nop instructions committed +system.cpu.comStores 6502695 # Number of Store instructions committed system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.151916 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.151916 # CPI: Total CPI of All Threads +system.cpu.cpi 2.147571 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.147571 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51575.789474 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48548.421053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51585.263158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48561.052632 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24498500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24503000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23060500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23066500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56234.265734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53234.265734 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56218.934911 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53218.934911 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104539500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104511000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98962500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98934000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +70,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55286.203942 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55275.921165 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52270.994002 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 129038000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 129014000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 122023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 122000500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352005 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.813640 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352002 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.798330 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55286.203942 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55275.921165 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52270.994002 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 129038000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 129014000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 122023000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 122000500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,11 +102,10 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.813640 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.798330 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 26497301 # DTB hits @@ -119,73 +122,72 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 103175523 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27130.157283 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.529994 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 103166749 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 238040000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 102632944 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 27261.770785 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23983.385799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 102624236 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 237395500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8774 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205787000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8585 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_misses 8708 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 131 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205705500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 8577 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2500 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12017.093652 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 11965.050251 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 103175523 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27130.157283 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency -system.cpu.icache.demand_hits 103166749 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 238040000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 102632944 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 27261.770785 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23983.385799 # average overall mshr miss latency +system.cpu.icache.demand_hits 102624236 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 237395500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8774 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205787000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8585 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_misses 8708 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 131 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205705500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 8577 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697574 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.631049 # Average occupied blocks per context -system.cpu.icache.overall_accesses 103175523 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27130.157283 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.697567 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.616252 # Average occupied blocks per context +system.cpu.icache.overall_accesses 102632944 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 27261.770785 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23983.385799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 103166749 # number of overall hits -system.cpu.icache.overall_miss_latency 238040000 # number of overall miss cycles +system.cpu.icache.overall_hits 102624236 # number of overall hits +system.cpu.icache.overall_miss_latency 237395500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8774 # number of overall misses -system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205787000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8585 # number of overall MSHR misses +system.cpu.icache.overall_misses 8708 # number of overall misses +system.cpu.icache.overall_mshr_hits 131 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205705500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 8577 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6751 # number of replacements -system.cpu.icache.sampled_refs 8585 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6743 # number of replacements +system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.631049 # Cycle average of tags in use -system.cpu.icache.total_refs 103166749 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.616252 # Cycle average of tags in use +system.cpu.icache.total_refs 102624236 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 103175522 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 7704221 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.464702 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.464702 # IPC: Total IPC of All Threads +system.cpu.idleCycles 8044656 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.465642 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.465642 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 103175571 # ITB accesses +system.cpu.itb.fetch_accesses 102632992 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 103175524 # ITB hits +system.cpu.itb.fetch_hits 102632945 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,28 +198,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52230.263158 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52211.384439 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91298500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 91265500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 9060 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52165.034280 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52168.952008 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40019.915116 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5997 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159781500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338079 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 159793500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 122581000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338079 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52229.729730 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52274.774775 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5797500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5802500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles @@ -227,73 +229,73 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.974587 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.971947 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52184.369154 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5997 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 251080000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445133 # miss rate for demand accesses +system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 251059000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 192511000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.445463 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061819 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.061818 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2025.680452 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.727236 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 10808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2025.652199 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.726445 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52184.369154 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5997 # number of overall hits -system.cpu.l2cache.overall_miss_latency 251080000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445133 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 5989 # number of overall hits +system.cpu.l2cache.overall_miss_latency 251059000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4811 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 192511000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.445463 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2039.407688 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5983 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2039.378644 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 197767633 # number of cpu cycles simulated -system.cpu.runCycles 190063412 # Number of cycles cpu stages are processed. +system.cpu.numCycles 197368293 # number of cpu cycles simulated +system.cpu.runCycles 189323637 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94592062 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 103175571 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 52.170100 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 105665019 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 92102614 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.571126 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 104275149 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94735301 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 102632992 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 52.000750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 105250860 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 92117433 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 46.672863 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 103875809 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.273906 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 171230502 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.369556 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 170831162 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.418339 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 105864577 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.445488 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 105465237 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.470221 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 197767633 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.564245 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 197368293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 3181a01cf..e4a83a80f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 01:43:39 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 01:43:43 -M5 executing on zizzer +M5 compiled Jun 23 2010 16:05:32 +M5 revision f157e4974de9+ 7462+ default qtip inorder_update_regr tip +M5 started Jun 23 2010 16:08:02 +M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31242000 because target called exit() +Exiting @ tick 31241000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 8b050d9d7..051a5e733 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,42 +1,46 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 29156 # Simulator instruction rate (inst/s) -host_mem_usage 203904 # Number of bytes of host memory used +host_inst_rate 29161 # Simulator instruction rate (inst/s) +host_mem_usage 154960 # Number of bytes of host memory used host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 142052352 # Simulator tick rate (ticks/s) +host_tick_rate 142056848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31242000 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 94 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 314 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 125 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 895 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 751 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 829 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 237 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. -system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 524 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 134 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.069457 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13850 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. -system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 19960 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 22.272545 # Percentage of cycles cpu is active +sim_ticks 31241000 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 307 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 124 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 653 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 750 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 1051 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 817 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 234 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 124 # Number of times the RAS was used to get a target. +system.cpu.Execution-Unit.executions 4354 # Number of Instructions Executed. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 130 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed +system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed +system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File +system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 22.258854 # Percentage of cycles cpu is active +system.cpu.comBranches 1051 # Number of Branches instructions committed +system.cpu.comFloats 2 # Number of Floating Point instructions committed +system.cpu.comInts 3265 # Number of Integer instructions committed +system.cpu.comLoads 1185 # Number of Load instructions committed +system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed +system.cpu.comNops 17 # Number of Nop instructions committed +system.cpu.comStores 865 # Number of Store instructions committed system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.757183 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.757183 # CPI: Total CPI of All Threads +system.cpu.cpi 9.756871 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.756871 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56336.842105 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53336.842105 # average ReadReq mshr miss latency @@ -48,13 +52,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 5067000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56057.471264 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53057.471264 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4877000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4616000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +70,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56203.296703 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56208.791209 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10229000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10230000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9684000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025306 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.651945 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025304 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.646332 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56203.296703 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56208.791209 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10229000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10230000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9684000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,11 +102,10 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.651945 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.646332 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -119,73 +122,72 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7296 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55536.544850 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6995 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16716500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.041255 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7293 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55534.883721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52861.403509 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6992 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16716000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041272 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.039062 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15065500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.630282 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.619718 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7296 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55536.544850 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency -system.cpu.icache.demand_hits 6995 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16716500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.041255 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7293 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55534.883721 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52861.403509 # average overall mshr miss latency +system.cpu.icache.demand_hits 6992 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16716000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041272 # miss rate for demand accesses system.cpu.icache.demand_misses 301 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.039062 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15065500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063623 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.299954 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7296 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55536.544850 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.063620 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.293561 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7293 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55534.883721 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52861.403509 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6995 # number of overall hits -system.cpu.icache.overall_miss_latency 16716500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.041255 # miss rate for overall accesses +system.cpu.icache.overall_hits 6992 # number of overall hits +system.cpu.icache.overall_miss_latency 16716000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041272 # miss rate for overall accesses system.cpu.icache.overall_misses 301 # number of overall misses system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.039062 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15065500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.299954 # Cycle average of tags in use -system.cpu.icache.total_refs 6995 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.293561 # Cycle average of tags in use +system.cpu.icache.total_refs 6992 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7294 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 48568 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102489 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102489 # IPC: Total IPC of All Threads +system.cpu.idleCycles 48575 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102492 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102492 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7313 # ITB accesses +system.cpu.itb.fetch_accesses 7310 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7296 # ITB hits +system.cpu.itb.fetch_hits 7293 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,19 +198,19 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52054.794521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3800000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52065.963061 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52064.643799 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19733000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19732500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles @@ -232,10 +234,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52064.159292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52065.265487 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23533500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -246,13 +248,13 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.005537 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.445272 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 181.436948 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52064.159292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52065.265487 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23533500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -264,32 +266,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.445272 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.436948 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62485 # number of cpu cycles simulated -system.cpu.runCycles 13917 # Number of cycles cpu stages are processed. +system.cpu.numCycles 62483 # number of cpu cycles simulated +system.cpu.runCycles 13908 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55172 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7313 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.703609 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55931 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 55173 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7310 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.699182 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55929 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 6554 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.488917 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 56015 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 10.489253 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56013 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.354485 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60432 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.354817 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60430 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.285589 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 56081 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.285694 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56079 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.248860 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62485 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.249188 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62483 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 12732e5e1..776151103 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 02:40:58 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 02:41:01 -M5 executing on zizzer +M5 compiled Jun 23 2010 15:46:45 +M5 revision f157e4974de9 7462 default qtip inorder_update_regr tip +M5 started Jun 23 2010 15:46:50 +M5 executing on zooks command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29206500 because target called exit() +Exiting @ tick 29208500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 76dc624e3..eb0573e7d 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,42 +1,46 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30301 # Simulator instruction rate (inst/s) -host_mem_usage 205096 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 151651964 # Simulator tick rate (ticks/s) +host_inst_rate 17945 # Simulator instruction rate (inst/s) +host_mem_usage 155896 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 89863736 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29206500 # Number of ticks simulated -system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 0 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 499 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 666 # Number of conditional branches incorrect +sim_ticks 29208500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 160 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 86 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 607 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.lookups 916 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 826 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 90 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedNotTaken 802 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 114 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.cyclesExecuted 3725 # Number of Cycles Execution Unit was used. -system.cpu.Execution-Unit.instReqsProcessed 3734 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 541 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 35 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.063769 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 11702 # Number of Instructions Requests that completed in this resource. -system.cpu.Graduation-Unit.instReqsProcessed 5827 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed. -system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource. -system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 10713 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 20.277673 # Percentage of cycles cpu is active +system.cpu.Execution-Unit.executions 3734 # Number of Instructions Executed. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 88 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed +system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed +system.cpu.RegFile-Manager.regFileAccesses 10683 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7273 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File +system.cpu.RegFile-Manager.regForwards 30 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 20.281420 # Percentage of cycles cpu is active +system.cpu.comBranches 916 # Number of Branches instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed +system.cpu.comInts 2155 # Number of Integer instructions committed +system.cpu.comLoads 1164 # Number of Load instructions committed +system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed +system.cpu.comNops 657 # Number of Nop instructions committed +system.cpu.comStores 925 # Number of Store instructions committed system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads +system.cpu.cpi 10.025399 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 10.025399 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency @@ -79,8 +83,8 @@ system.cpu.dcache.demand_mshr_misses 151 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021605 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 88.492735 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency @@ -98,11 +102,10 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 88.492735 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache_port.instReqsProcessed 2089 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -112,65 +115,64 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 5876 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55805.280528 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52805.280528 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5573 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16909000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.051566 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 16000000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.051566 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.392739 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency -system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses +system.cpu.icache.demand_accesses 5876 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55805.280528 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52805.280528 # average overall mshr miss latency +system.cpu.icache.demand_hits 5573 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16909000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.051566 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 16000000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.051566 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context -system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.066096 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 135.365361 # Average occupied blocks per context +system.cpu.icache.overall_accesses 5876 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55805.280528 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52805.280528 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5571 # number of overall hits -system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses +system.cpu.icache.overall_hits 5573 # number of overall hits +system.cpu.icache.overall_miss_latency 16909000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.051566 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 16000000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.051566 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use -system.cpu.icache.total_refs 5571 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 135.365361 # Cycle average of tags in use +system.cpu.icache.total_refs 5573 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 5873 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads +system.cpu.idleCycles 46570 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.099747 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.099747 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -190,10 +192,10 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52094.072165 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20212500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles @@ -217,10 +219,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52113.895216 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22878000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -231,13 +233,13 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 187.035304 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52113.895216 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22878000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses system.cpu.l2cache.overall_misses 439 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -249,32 +251,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 187.035304 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 58414 # number of cpu cycles simulated -system.cpu.runCycles 11845 # Number of cycles cpu stages are processed. +system.cpu.numCycles 58418 # number of cpu cycles simulated +system.cpu.runCycles 11848 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 52542 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 5876 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.058544 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 52590 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 9.976377 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 52586 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 9.983224 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 56328 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.577664 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 52591 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 9.974665 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 58418 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |