ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state.  In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages.  Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.

--HG--
rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py
rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py

10 files changed, 275 insertions, 26 deletions

diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index df3062c93..806719916 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -234,7 +234,7 @@ machine(Directory, "AMD Hammer-like protocol")
   // ** IN_PORTS **
   
   // Trigger Queue
-  in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
+  in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) {
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
         if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -250,7 +250,7 @@ machine(Directory, "AMD Hammer-like protocol")
     }
   }
 
-  in_port(unblockNetwork_in, ResponseMsg, unblockToDir) {
+  in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) {
     if (unblockNetwork_in.isReady()) {
       peek(unblockNetwork_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
@@ -275,7 +275,7 @@ machine(Directory, "AMD Hammer-like protocol")
   }
 
   // Response Network
-  in_port(responseToDir_in, ResponseMsg, responseToDir) {
+  in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) {
     if (responseToDir_in.isReady()) {
       peek(responseToDir_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:ACK) {
@@ -295,22 +295,8 @@ machine(Directory, "AMD Hammer-like protocol")
     }
   }
 
-  in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
-    if (dmaRequestQueue_in.isReady()) {
-      peek(dmaRequestQueue_in, DMARequestMsg) {
-        if (in_msg.Type == DMARequestType:READ) {
-          trigger(Event:DMA_READ, in_msg.LineAddress);
-        } else if (in_msg.Type == DMARequestType:WRITE) {
-          trigger(Event:DMA_WRITE, in_msg.LineAddress);
-        } else {
-          error("Invalid message");
-        }
-      }
-    }
-  }
-
   // off-chip memory request/response is done
-  in_port(memQueue_in, MemoryMsg, memBuffer) {
+  in_port(memQueue_in, MemoryMsg, memBuffer, rank=2) {
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
@@ -325,7 +311,7 @@ machine(Directory, "AMD Hammer-like protocol")
     }
   }
 
-  in_port(requestQueue_in, RequestMsg, requestToDir) {
+  in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:PUT) {
@@ -349,6 +335,20 @@ machine(Directory, "AMD Hammer-like protocol")
     }
   }
 
+  in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir, rank=0) {
+    if (dmaRequestQueue_in.isReady()) {
+      peek(dmaRequestQueue_in, DMARequestMsg) {
+        if (in_msg.Type == DMARequestType:READ) {
+          trigger(Event:DMA_READ, in_msg.LineAddress);
+        } else if (in_msg.Type == DMARequestType:WRITE) {
+          trigger(Event:DMA_WRITE, in_msg.LineAddress);
+        } else {
+          error("Invalid message");
+        }
+      }
+    }
+  }
+
   // Actions
   
   action(r_setMRU, "\rr", desc="manually set the MRU bit for pf entry" ) {
@@ -772,6 +772,10 @@ machine(Directory, "AMD Hammer-like protocol")
     unblockNetwork_in.dequeue();
   }
 
+  action(k_wakeUpDependents, "k", desc="wake-up dependents") {
+    wake_up_dependents(address);
+  }
+
   action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
     memQueue_in.dequeue();
   }
@@ -784,8 +788,11 @@ machine(Directory, "AMD Hammer-like protocol")
     dmaRequestQueue_in.dequeue();
   }
 
-  action(y_recycleDmaRequestQueue, "y", desc="recycle dma request queue") {
-    dmaRequestQueue_in.recycle();
+  action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") {
+    peek(dmaRequestQueue_in, DMARequestMsg) {
+        APPEND_TRANSITION_COMMENT(in_msg.Requestor);
+    } 
+    stall_and_wait(dmaRequestQueue_in, address);
   }
 
   action(r_recordMemoryData, "rd", desc="record data from memory to TBE") {
@@ -882,11 +889,11 @@ machine(Directory, "AMD Hammer-like protocol")
     }
   }
 
-  action(zz_recycleRequest, "\z", desc="Recycle the request queue") {
+  action(z_stallAndWaitRequest, "z", desc="Recycle the request queue") {
     peek(requestQueue_in, RequestMsg) {
         APPEND_TRANSITION_COMMENT(in_msg.Requestor);
     } 
-    requestQueue_in.recycle();
+    stall_and_wait(requestQueue_in, address);
   }
 
   // TRANSITIONS
@@ -1055,26 +1062,29 @@ machine(Directory, "AMD Hammer-like protocol")
               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, 
               NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R}, 
              {GETS, GETX, PUT, Pf_Replacement}) {
-    zz_recycleRequest;
+    z_stallAndWaitRequest;
   }
 
   transition({NO_B, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D, 
               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, 
               NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R}, 
              {DMA_READ, DMA_WRITE}) {
-    y_recycleDmaRequestQueue;
+    zd_stallAndWaitDMARequest;
   }
 
   transition(NO_B, UnblockS, NX) {
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 
   transition(NO_B, UnblockM, NO) {
     uo_updateOwnerIfPf;
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 
   transition(O_B, UnblockS, O) {
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 
@@ -1125,6 +1135,7 @@ machine(Directory, "AMD Hammer-like protocol")
 
   transition({O_R, S_R, NO_R}, All_acks_and_data_no_sharers, E) {
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1197,6 +1208,7 @@ machine(Directory, "AMD Hammer-like protocol")
     dt_sendDmaDataFromTbe;
     wdt_writeDataFromTBE;
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1209,6 +1221,7 @@ machine(Directory, "AMD Hammer-like protocol")
     dt_sendDmaDataFromTbe;
     wdt_writeDataFromTBE;
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1221,6 +1234,7 @@ machine(Directory, "AMD Hammer-like protocol")
     dt_sendDmaDataFromTbe;
     wdt_writeDataFromTBE;
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1233,12 +1247,14 @@ machine(Directory, "AMD Hammer-like protocol")
     dt_sendDmaDataFromTbe;
     wdt_writeDataFromTBE;
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
   transition(O_DR_B, All_acks_and_owner_data, O) {
     wdt_writeDataFromTBE;
     w_deallocateTBE;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1246,6 +1262,7 @@ machine(Directory, "AMD Hammer-like protocol")
     wdt_writeDataFromTBE;
     w_deallocateTBE;
     pfd_probeFilterDeallocate;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1259,6 +1276,7 @@ machine(Directory, "AMD Hammer-like protocol")
     wdt_writeDataFromTBE;
     w_deallocateTBE;
     ppfd_possibleProbeFilterDeallocate;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1273,6 +1291,7 @@ machine(Directory, "AMD Hammer-like protocol")
     wdt_writeDataFromTBE;
     w_deallocateTBE;
     ppfd_possibleProbeFilterDeallocate;
+    k_wakeUpDependents;
     g_popTriggerQueue;
   }
 
@@ -1286,6 +1305,7 @@ machine(Directory, "AMD Hammer-like protocol")
     da_sendDmaAck;
     w_deallocateTBE;
     ppfd_possibleProbeFilterDeallocate;
+    k_wakeUpDependents;
     l_popMemQueue;
   }
 
@@ -1305,11 +1325,13 @@ machine(Directory, "AMD Hammer-like protocol")
 
   transition(NO_W, Memory_Data, NO) {
     w_deallocateTBE;
+    k_wakeUpDependents;
     l_popMemQueue;
   }
 
   transition(O_W, Memory_Data, O) {
     w_deallocateTBE;
+    k_wakeUpDependents;
     l_popMemQueue;
   }
 
@@ -1328,26 +1350,31 @@ machine(Directory, "AMD Hammer-like protocol")
 
   transition(WB_E_W, Memory_Ack, E) {
     pfd_probeFilterDeallocate;
+    k_wakeUpDependents;
     l_popMemQueue;
   }
 
   transition(WB_O_W, Memory_Ack, O) {
+    k_wakeUpDependents;
     l_popMemQueue;
   }
 
   transition(WB, Writeback_Clean, O) {
     ll_checkIncomingWriteback;
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 
   transition(WB, Writeback_Exclusive_Clean, E) {
     ll_checkIncomingWriteback;
     pfd_probeFilterDeallocate;
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 
   transition(WB, Unblock, NO) {
     auno_assertUnblockerNotOwner;
+    k_wakeUpDependents;
     j_popIncomingUnblockQueue;
   }
 }
diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc
index 9cd1dd47b..7d28cef22 100644
--- a/src/mem/ruby/buffers/MessageBuffer.cc
+++ b/src/mem/ruby/buffers/MessageBuffer.cc
@@ -334,6 +334,49 @@ MessageBuffer::recycle()
         g_eventQueue_ptr->getTime() + m_recycle_latency);
 }
 
+void
+MessageBuffer::reanalyzeMessages(const Address& addr)
+{
+    DEBUG_MSG(QUEUE_COMP, MedPrio, "reanalyzeMessages " + m_name);
+    assert(m_stall_msg_map.count(addr) > 0);
+
+    //
+    // Put all stalled messages associated with this address back on the
+    // prio heap
+    //
+    while(!m_stall_msg_map[addr].empty()) {
+        m_msg_counter++;
+        MessageBufferNode msgNode(g_eventQueue_ptr->getTime() + 1, 
+                                  m_msg_counter, 
+                                  m_stall_msg_map[addr].front());
+
+        m_prio_heap.push_back(msgNode);
+        push_heap(m_prio_heap.begin(), m_prio_heap.end(),
+            greater<MessageBufferNode>());
+
+        g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, msgNode.m_time);
+        m_stall_msg_map[addr].pop_front();
+    }
+}
+
+void
+MessageBuffer::stallMessage(const Address& addr)
+{
+    DEBUG_MSG(QUEUE_COMP, MedPrio, "stalling " + m_name);
+    assert(isReady());
+    assert(addr.getOffset() == 0);
+    MsgPtr message = m_prio_heap.front().m_msgptr;
+
+    pop();
+
+    //
+    // Note: no event is scheduled to analyze the map at a later time.
+    // Instead the controller is responsible to call reanalyzeMessages when
+    // these addresses change state.
+    //
+    (m_stall_msg_map[addr]).push_back(message);
+}
+
 int
 MessageBuffer::setAndReturnDelayCycles(MsgPtr msg_ptr)
 {
diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh
index e4bee5cf6..e09abeb7d 100644
--- a/src/mem/ruby/buffers/MessageBuffer.hh
+++ b/src/mem/ruby/buffers/MessageBuffer.hh
@@ -45,6 +45,7 @@
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/slicc_interface/Message.hh"
+#include "mem/ruby/common/Address.hh"
 
 class MessageBuffer
 {
@@ -58,6 +59,9 @@ class MessageBuffer
         m_recycle_latency = recycle_latency;
     }
 
+    void reanalyzeMessages(const Address& addr);
+    void stallMessage(const Address& addr);
+
     // TRUE if head of queue timestamp <= SystemTime
     bool
     isReady() const
@@ -150,6 +154,11 @@ class MessageBuffer
     // Data Members (m_ prefix)
     Consumer* m_consumer_ptr;  // Consumer to signal a wakeup(), can be NULL
     std::vector<MessageBufferNode> m_prio_heap;
+    
+    typedef m5::hash_map< Address, std::list<MsgPtr> > StallMsgMapType;
+    typedef std::vector<MsgPtr>::iterator MsgListIter;
+
+    StallMsgMapType m_stall_msg_map;
     std::string m_name;
 
     int m_max_size;
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index ad48ea4b8..5aa27bae8 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -30,6 +30,8 @@ from slicc.ast.TypeAST import TypeAST
 from slicc.symbols import Func, Type, Var
 
 class InPortDeclAST(DeclAST):
+    max_port_rank = 0
+    
     def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
         super(InPortDeclAST, self).__init__(slicc, pairs)
 
@@ -38,6 +40,9 @@ class InPortDeclAST(DeclAST):
         self.var_expr = var_expr
         self.statements = statements
         self.queue_type = TypeAST(slicc, "InPort")
+        if self.pairs.has_key("rank"):
+            InPortDeclAST.max_port_rank = max(self.pairs["rank"],
+                                              InPortDeclAST.max_port_rank)
 
     def __repr__(self):
         return "[InPortDecl: %s]" % self.ident
@@ -126,3 +131,6 @@ class InPortDeclAST(DeclAST):
             self.error("InPort declaration not part of a machine.")
 
         machine.addInPort(in_port)
+
+        # Include max_rank to be used by StateMachine.py
+        in_port["max_port_rank"] = InPortDeclAST.max_port_rank
diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py
index 18244f507..cc3091c8a 100644
--- a/src/mem/slicc/ast/PeekStatementAST.py
+++ b/src/mem/slicc/ast/PeekStatementAST.py
@@ -77,6 +77,14 @@ class PeekStatementAST(StatementAST):
     }
             ''')
 
+        if self.pairs.has_key("wake_up"):
+            address_field = self.pairs['wake_up']
+            code('''
+    if (m_waiting_buffers.count(in_msg_ptr->m_$address_field) > 0) {
+        wakeUpBuffers(in_msg_ptr->m_$address_field);
+    }
+            ''')
+
         # The other statements
         self.statements.generate(code, return_type)
         self.symtab.popFrame()
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py
new file mode 100644
index 000000000..b87726c6a
--- /dev/null
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -0,0 +1,49 @@
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class StallAndWaitStatementAST(StatementAST):
+    def __init__(self, slicc, in_port, address):
+        super(StatementAST, self).__init__(slicc)
+        self.in_port = in_port
+        self.address = address
+        
+    def __repr__(self):
+        return "[StallAndWaitStatementAst: %r]" % self.variable
+
+    def generate(self, code, return_type):
+        self.in_port.assertType("InPort")
+        self.address.assertType("Address")
+
+        in_port_code = self.in_port.var.code
+        address_code = self.address.var.code
+        code('''
+        stallBuffer(&($in_port_code), $address_code);
+        $in_port_code.stallMessage($address_code);
+        ''')
diff --git a/src/mem/slicc/ast/WakeUpDependentsStatementAST.py b/src/mem/slicc/ast/WakeUpDependentsStatementAST.py
new file mode 100644
index 000000000..33630a9a4
--- /dev/null
+++ b/src/mem/slicc/ast/WakeUpDependentsStatementAST.py
@@ -0,0 +1,46 @@
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeUpDependentsStatementAST(StatementAST):
+    def __init__(self, slicc, address):
+        super(StatementAST, self).__init__(slicc)
+        self.address = address
+        
+    def __repr__(self):
+        return "[WakeUpDependentsStatementAst: %r]" % self.variable
+
+    def generate(self, code, return_type):
+        self.address.assertType("Address")
+        address_code = self.address.var.code
+        code('''
+        if (m_waiting_buffers.count($address_code) > 0) {
+            wakeUpBuffers($address_code);
+        }
+        ''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index cc5f02b84..b854612be 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -57,6 +57,7 @@ from slicc.ast.PairAST import *
 from slicc.ast.PairListAST import *
 from slicc.ast.PeekStatementAST import *
 from slicc.ast.ReturnStatementAST import *
+from slicc.ast.StallAndWaitStatementAST import *
 from slicc.ast.StatementAST import *
 from slicc.ast.StatementListAST import *
 from slicc.ast.StaticCastAST import *
@@ -68,3 +69,4 @@ from slicc.ast.TypeFieldEnumAST import *
 from slicc.ast.TypeFieldMemberAST import *
 from slicc.ast.TypeFieldMethodAST import *
 from slicc.ast.VarExprAST import *
+from slicc.ast.WakeUpDependentsStatementAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 1505e1d0c..ce665465f 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -157,6 +157,8 @@ class SLICC(Grammar):
         'external_type' : 'EXTERN_TYPE',
         'enumeration' : 'ENUM',
         'peek' : 'PEEK',
+        'stall_and_wait' : 'STALL_AND_WAIT',
+        'wake_up_dependents' : 'WAKE_UP_DEPENDENTS',
         'enqueue' : 'ENQUEUE',
         'copy_head' : 'COPY_HEAD',
         'check_allocate' : 'CHECK_ALLOCATE',
@@ -499,7 +501,8 @@ class SLICC(Grammar):
 
     def p_pair__assign(self, p):
         """pair : ident '=' STRING
-                | ident '=' ident"""
+                | ident '=' ident
+                | ident '=' NUMBER"""
         p[0] = ast.PairAST(self, p[1], p[3])
 
     def p_pair__literal(self, p):
@@ -547,6 +550,14 @@ class SLICC(Grammar):
         "statement : ENQUEUE '(' var ',' type pairs ')' statements"
         p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[6], p[8])
 
+    def p_statement__stall_and_wait(self, p):
+        "statement : STALL_AND_WAIT '(' var ',' var ')' SEMI"
+        p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5])
+
+    def p_statement__wake_up_dependents(self, p):
+        "statement : WAKE_UP_DEPENDENTS '(' var ')' SEMI"
+        p[0] = ast.WakeUpDependentsStatementAST(self, p[3])
+
     def p_statement__peek(self, p):
         "statement : PEEK '(' var ',' type pairs ')' statements"
         p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index d5a824905..e57275527 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -238,6 +238,8 @@ public:
     const std::string toString() const;
     const std::string getName() const;
     const MachineType getMachineType() const;
+    void stallBuffer(MessageBuffer* buf, Address addr);
+    void wakeUpBuffers(Address addr);
     void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
     void print(std::ostream& out) const;
     void printConfig(std::ostream& out) const;
@@ -280,6 +282,11 @@ Network* m_net_ptr;
 MachineID m_machineID;
 bool m_is_blocking;
 std::map<Address, MessageBuffer*> m_block_map;
+typedef std::vector<MessageBuffer*> MsgVecType;
+typedef m5::hash_map< Address, MsgVecType* > WaitingBufType;
+WaitingBufType m_waiting_buffers;
+int m_max_in_port_rank;
+int m_cur_in_port_rank;
 static ${ident}_ProfileDumper s_profileDumper;
 ${ident}_Profiler m_profiler;
 static int m_num_controllers;
@@ -378,6 +385,12 @@ $c_ident::$c_ident(const Params *p)
     m_number_of_TBEs = p->number_of_TBEs;
     m_is_blocking = false;
 ''')
+        #
+        # max_port_rank is used to size vectors and thus should be one plus the
+        # largest port rank
+        #
+        max_port_rank = self.in_ports[0].pairs["max_port_rank"] + 1
+        code('    m_max_in_port_rank = $max_port_rank;')
         code.indent()
 
         #
@@ -621,6 +634,35 @@ $c_ident::getMachineType() const
 }
 
 void
+$c_ident::stallBuffer(MessageBuffer* buf, Address addr)
+{
+    if (m_waiting_buffers.count(addr) == 0) {
+        MsgVecType* msgVec = new MsgVecType;
+        msgVec->resize(m_max_in_port_rank, NULL);
+        m_waiting_buffers[addr] = msgVec;
+    }
+    (*(m_waiting_buffers[addr]))[m_cur_in_port_rank] = buf;
+}
+
+void
+$c_ident::wakeUpBuffers(Address addr)
+{
+    //
+    // Wake up all possible lower rank (i.e. lower priority) buffers that could
+    // be waiting on this message.
+    // 
+    for (int in_port_rank = m_cur_in_port_rank - 1;
+         in_port_rank >= 0;
+         in_port_rank--) {
+        if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
+            (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr);
+        }
+    }
+    delete m_waiting_buffers[addr];
+    m_waiting_buffers.erase(addr);
+}
+
+void
 $c_ident::blockOnQueue(Address addr, MessageBuffer* port)
 {
     m_is_blocking = true;
@@ -757,6 +799,10 @@ ${ident}_Controller::wakeup()
         for port in self.in_ports:
             code.indent()
             code('// ${ident}InPort $port')
+            if port.pairs.has_key("rank"):
+                code('m_cur_in_port_rank = ${{port.pairs["rank"]}};')
+            else:
+                code('m_cur_in_port_rank = 0;')
             code('${{port["c_code_in_port"]}}')
             code.dedent()