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authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
commit03286e9d4e797c7ca824a72627a947a42e01795f (patch)
tree6c873877ad9e5af85dcb7d319570c47d2622ad41
parent92ae620be8b46742042dcfe6dfaf38ecac24ad09 (diff)
downloadgem5-03286e9d4e797c7ca824a72627a947a42e01795f.tar.xz
CPU: Make Exec trace to print predication result (if false) for memory instructions
-rw-r--r--src/cpu/base_dyn_inst.hh4
-rw-r--r--src/cpu/exetrace.cc4
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rw-r--r--src/cpu/simple/base.hh7
-rw-r--r--src/sim/insttracer.hh4
5 files changed, 21 insertions, 1 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a992664d0..41cb13949 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -805,6 +805,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
void setPredicate(bool val)
{
predicate = val;
+
+ if (traceData) {
+ traceData->setPredicate(val);
+ }
}
/** Sets the ASID. */
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 28c7861ef..051ee57a0 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -111,6 +111,10 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
+ if (IsOn(ExecResult) && predicate == false) {
+ outs << "Predicated False";
+ }
+
if (IsOn(ExecResult) && data_status != DataInvalid) {
ccprintf(outs, " D=%#018x", data.as_int);
}
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 9e6bbe92f..7330ba2ef 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -458,6 +458,9 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
+ DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
+ inst->seqNum,
+ (load_fault != NoFault ? "fault" : "predication"));
if (!(inst->hasRequest() && inst->uncacheable()) ||
inst->isAtCommit()) {
inst->setExecuted();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 90cb81c0c..24527f9eb 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -295,7 +295,12 @@ class BaseSimpleCPU : public BaseCPU
void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
void setPredicate(bool val)
- { return thread->setPredicate(val); }
+ {
+ thread->setPredicate(val);
+ if (traceData) {
+ traceData->setPredicate(val);
+ }
+ }
MiscReg readMiscRegNoEffect(int misc_reg)
{
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index a8cdff671..c3f3eb323 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -58,6 +58,7 @@ class InstRecord
StaticInstPtr macroStaticInst;
MicroPC upc;
bool misspeculating;
+ bool predicate;
// The remaining fields are only valid for particular instruction
// types (e.g, addresses for memory ops) or when particular
@@ -102,6 +103,7 @@ class InstRecord
fetch_seq_valid = false;
cp_seq_valid = false;
+ predicate = false;
}
virtual ~InstRecord() { }
@@ -128,6 +130,8 @@ class InstRecord
void setCPSeq(InstSeqNum seq)
{ cp_seq = seq; cp_seq_valid = true; }
+ void setPredicate(bool val) { predicate = val; }
+
virtual void dump() = 0;
public: