Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.

arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
    Added news where faults are created.
arch/alpha/ev5.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
    Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
    Added a new where an UnimplementedFault is created.
base/refcnt.hh:
    Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
    Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
    Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
    Added news where MachineCheckFaults are created.
dev/pcidev.hh:
    Added news where MachineCheckFaults are generated.
dev/sinic.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
    Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
    Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
    Changed Fault from a FaultBase * to a RefCountingPtr.

--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d

20 files changed, 333 insertions, 214 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d00186d95..b2a829711 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -322,7 +322,7 @@ AlphaITB::translate(MemReqPtr &req) const
         if (!validVirtualAddress(req->vaddr)) {
             fault(req->vaddr, req->xc);
             acv++;
-            return ItbAcvFault;
+            return new ItbAcvFault;
         }
 
 
@@ -339,7 +339,7 @@ AlphaITB::translate(MemReqPtr &req) const
                 AlphaISA::mode_kernel) {
                 fault(req->vaddr, req->xc);
                 acv++;
-                return ItbAcvFault;
+                return new ItbAcvFault;
             }
 
             req->paddr = req->vaddr & PAddrImplMask;
@@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const
             if (!pte) {
                 fault(req->vaddr, req->xc);
                 misses++;
-                return ItbPageFault;
+                return new ItbPageFault;
             }
 
             req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -371,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const
                 // instruction access fault
                 fault(req->vaddr, req->xc);
                 acv++;
-                return ItbAcvFault;
+                return new ItbAcvFault;
             }
 
             hits++;
@@ -380,7 +380,7 @@ AlphaITB::translate(MemReqPtr &req) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return MachineCheckFault;
+        return new MachineCheckFault;
 
     checkCacheability(req);
 
@@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
         fault(req, write ? MM_STAT_WR_MASK : 0);
         DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
                 req->size);
-        return AlignmentFault;
+        return new AlignmentFault;
     }
 
     if (pc & 0x1) {
@@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                   MM_STAT_ACV_MASK);
 
             if (write) { write_acv++; } else { read_acv++; }
-            return DtbPageFault;
+            return new DtbPageFault;
         }
 
         // Check for "superpage" mapping
@@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                 fault(req, ((write ? MM_STAT_WR_MASK : 0) |
                             MM_STAT_ACV_MASK));
                 if (write) { write_acv++; } else { read_acv++; }
-                return DtbAcvFault;
+                return new DtbAcvFault;
             }
 
             req->paddr = req->vaddr & PAddrImplMask;
@@ -575,7 +575,9 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                 fault(req, (write ? MM_STAT_WR_MASK : 0) |
                       MM_STAT_DTB_MISS_MASK);
                 if (write) { write_misses++; } else { read_misses++; }
-                return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault;
+                return (req->flags & VPTE) ?
+                    (Fault)(new PDtbMissFault) :
+                    (Fault)(new NDtbMissFault);
             }
 
             req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -588,25 +590,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                           MM_STAT_ACV_MASK |
                           (pte->fonw ? MM_STAT_FONW_MASK : 0));
                     write_acv++;
-                    return DtbPageFault;
+                    return new DtbPageFault;
                 }
                 if (pte->fonw) {
                     fault(req, MM_STAT_WR_MASK |
                           MM_STAT_FONW_MASK);
                     write_acv++;
-                    return DtbPageFault;
+                    return new DtbPageFault;
                 }
             } else {
                 if (!(pte->xre & MODE2MASK(mode))) {
                     fault(req, MM_STAT_ACV_MASK |
                           (pte->fonr ? MM_STAT_FONR_MASK : 0));
                     read_acv++;
-                    return DtbAcvFault;
+                    return new DtbAcvFault;
                 }
                 if (pte->fonr) {
                     fault(req, MM_STAT_FONR_MASK);
                     read_acv++;
-                    return DtbPageFault;
+                    return new DtbPageFault;
                 }
             }
         }
@@ -619,7 +621,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return MachineCheckFault;
+        return new MachineCheckFault;
 
     checkCacheability(req);
 
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 4777907e0..3f1c17adc 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -76,7 +76,7 @@ AlphaISA::initCPU(RegFile *regs)
     // CPU comes up with PAL regs enabled
     swap_palshadow(regs, true);
 
-    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
+    regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect();
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
@@ -89,10 +89,10 @@ AlphaISA::fault_addr(Fault fault)
 {
         //Check for the system wide faults
         if(fault == NoFault) return 0x0000;
-        else if(fault == MachineCheckFault) return 0x0401;
-        else if(fault == AlignmentFault) return 0x0301;
+        else if(fault->isA<MachineCheckFault>()) return 0x0401;
+        else if(fault->isA<AlignmentFault>()) return 0x0301;
         //Deal with the alpha specific faults
-        return ((AlphaFault*)fault)->vect;
+        return ((AlphaFault *)(fault.get()))->vect();
 };
 
 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
@@ -158,7 +158,7 @@ AlphaISA::processInterrupts(CPU *cpu)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        cpu->trap(InterruptFault);
+        cpu->trap(new InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
@@ -179,22 +179,22 @@ AlphaISA::zeroRegisters(CPU *cpu)
 void
 ExecContext::ev5_trap(Fault fault)
 {
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", fault->name));
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
+    cpu->recordEvent(csprintf("Fault %s", fault->name()));
 
     assert(!misspeculating());
     kernelStats->fault(fault);
 
-    if (fault == ArithmeticFault)
+    if (fault->isA<ArithmeticFault>())
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = regs.ipr;
 
     // exception restart address
-    if (fault != InterruptFault || !inPalMode())
+    if (!fault->isA<InterruptFault>() || !inPalMode())
         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 
-    if (fault == PalFault || fault == ArithmeticFault /* ||
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
         fault == InterruptFault && !inPalMode() */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
@@ -214,11 +214,11 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
     InternalProcReg *ipr = regs->ipr;
     bool use_pc = (fault == NoFault);
 
-    if (fault == ArithmeticFault)
+    if (fault->isA<ArithmeticFault>())
         panic("arithmetic faults NYI...");
 
     // compute exception restart address
-    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
+    if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
         // traps...  skip faulting instruction
         ipr[IPR_EXC_ADDR] = regs->pc + 4;
     } else {
@@ -241,7 +241,7 @@ ExecContext::hwrei()
     uint64_t *ipr = regs.ipr;
 
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -353,12 +353,12 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
     }
 
@@ -523,7 +523,7 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -625,7 +625,7 @@ ExecContext::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     // no error...
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index fa4950198..bbddadabf 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -28,36 +28,67 @@
 
 #include "arch/alpha/faults.hh"
 
-ResetFaultType * const ResetFault =
-    new ResetFaultType("reset", 1, 0x0001);
-ArithmeticFaultType * const ArithmeticFault =
-    new ArithmeticFaultType("arith", 3, 0x0501);
-InterruptFaultType * const InterruptFault =
-    new InterruptFaultType("interrupt", 4, 0x0101);
-NDtbMissFaultType * const NDtbMissFault =
-    new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
-PDtbMissFaultType * const PDtbMissFault =
-    new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
-DtbPageFaultType * const DtbPageFault =
-    new DtbPageFaultType("dfault", 8, 0x0381);
-DtbAcvFaultType * const DtbAcvFault =
-    new DtbAcvFaultType("dfault", 9, 0x0381);
-ItbMissFaultType * const ItbMissFault =
-    new ItbMissFaultType("itbmiss", 10, 0x0181);
-ItbPageFaultType * const ItbPageFault =
-    new ItbPageFaultType("itbmiss", 11, 0x0181);
-ItbAcvFaultType * const ItbAcvFault =
-    new ItbAcvFaultType("iaccvio", 12, 0x0081);
-UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
-    new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
-FloatEnableFaultType * const FloatEnableFault =
-    new FloatEnableFaultType("fen", 14, 0x0581);
-PalFaultType * const PalFault =
-    new PalFaultType("pal", 15, 0x2001);
-IntegerOverflowFaultType * const IntegerOverflowFault =
-    new IntegerOverflowFaultType("intover", 16, 0x0501);
-
-Fault * ListOfFaults[] = {
+FaultName AlphaFault::_name = "alphafault";
+FaultVect AlphaFault::_vect = 0x0000;
+FaultStat AlphaFault::_stat;
+
+FaultName ResetFault::_name = "reset";
+FaultVect ResetFault::_vect = 0x0001;
+FaultStat ResetFault::_stat;
+
+FaultName ArithmeticFault::_name = "arith";
+FaultVect ArithmeticFault::_vect = 0x0501;
+FaultStat ArithmeticFault::_stat;
+
+FaultName InterruptFault::_name = "interrupt";
+FaultVect InterruptFault::_vect = 0x0101;
+FaultStat InterruptFault::_stat;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_stat;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
+FaultVect PDtbMissFault::_vect = 0x0281;
+FaultStat PDtbMissFault::_stat;
+
+FaultName DtbPageFault::_name = "dfault";
+FaultVect DtbPageFault::_vect = 0x0381;
+FaultStat DtbPageFault::_stat;
+
+FaultName DtbAcvFault::_name = "dfault";
+FaultVect DtbAcvFault::_vect = 0x0381;
+FaultStat DtbAcvFault::_stat;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_stat;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_stat;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_stat;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_stat;
+
+FaultName FloatEnableFault::_name = "fen";
+FaultVect FloatEnableFault::_vect = 0x0581;
+FaultStat FloatEnableFault::_stat;
+
+FaultName PalFault::_name = "pal";
+FaultVect PalFault::_vect = 0x2001;
+FaultStat PalFault::_stat;
+
+FaultName IntegerOverflowFault::_name = "intover";
+FaultVect IntegerOverflowFault::_vect = 0x0501;
+FaultStat IntegerOverflowFault::_stat;
+
+/*Fault * ListOfFaults[] = {
         (Fault *)&NoFault,
         (Fault *)&ResetFault,
         (Fault *)&MachineCheckFault,
@@ -77,4 +108,4 @@ Fault * ListOfFaults[] = {
         (Fault *)&IntegerOverflowFault,
         };
 
-int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 3e25adc4e..bd5163a7d 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -30,131 +30,192 @@
 #define __ALPHA_FAULTS_HH__
 
 #include "sim/faults.hh"
-#include "arch/isa_traits.hh" //For the Addr type
+
+// The reasoning behind the name and vect functions is in sim/faults.hh
+
+typedef const Addr FaultVect;
 
 class AlphaFault : public FaultBase
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    AlphaFault(char * newName, int newId, Addr newVect)
-        : FaultBase(newName, newId), vect(newVect)
-    {;}
-
-    Addr vect;
+    FaultName name() {return _name;}
+    virtual FaultVect vect() {return _vect;}
+    virtual FaultStat & stat() {return _stat;}
 };
 
-extern class ResetFaultType : public AlphaFault
+class ResetFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    ResetFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const ResetFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class ArithmeticFaultType : public AlphaFault
+class ArithmeticFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    ArithmeticFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const ArithmeticFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class InterruptFaultType : public AlphaFault
+class InterruptFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    InterruptFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const InterruptFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class NDtbMissFaultType : public AlphaFault
+class NDtbMissFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    NDtbMissFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const NDtbMissFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class PDtbMissFaultType : public AlphaFault
+class PDtbMissFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    PDtbMissFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const PDtbMissFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class DtbPageFaultType : public AlphaFault
+class DtbPageFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    DtbPageFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const DtbPageFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class DtbAcvFaultType : public AlphaFault
+class DtbAcvFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    DtbAcvFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const DtbAcvFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class ItbMissFaultType : public AlphaFault
+class ItbMissFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    ItbMissFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const ItbMissFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class ItbPageFaultType : public AlphaFault
+class ItbPageFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    ItbPageFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const ItbPageFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class ItbAcvFaultType : public AlphaFault
+class ItbAcvFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    ItbAcvFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const ItbAcvFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class UnimplementedOpcodeFaultType : public AlphaFault
+class UnimplementedOpcodeFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const UnimplementedOpcodeFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class FloatEnableFaultType : public AlphaFault
+class FloatEnableFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    FloatEnableFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const FloatEnableFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class PalFaultType : public AlphaFault
+class PalFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    PalFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const PalFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class IntegerOverflowFaultType : public AlphaFault
+class IntegerOverflowFault : public AlphaFault
 {
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _stat;
   public:
-    IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
-        : AlphaFault(newName, newId, newVect)
-    {;}
-} * const IntegerOverflowFault;
+    FaultName name() {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern Fault * ListOfFaults[];
-extern int NumFaults;
+//Fault * ListOfFaults[];
+//int NumFaults;
 
 #endif // __FAULTS_HH__
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 37b15416b..cdcf96215 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = tmp<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc.sl = tmp<31:0>;
             }}, IntMultOp);
             0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
                 // the lower 64
                 if (!((hi == 0 && lo<63:> == 0) ||
                       (hi == mask(64) && lo<63:> == 1)))
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Rc = lo;
             }}, IntMultOp);
         }
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
 #if SS_COMPATIBLE_FP
                     0x0b: sqrts({{
                         if (Fb < 0.0)
-                            fault = ArithmeticFault;
+                            fault = new ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
 #else
                     0x0b: sqrts({{
                         if (Fb.sf < 0.0)
-                            fault = ArithmeticFault;
+                            fault = new ArithmeticFault;
                         Fc.sf = sqrt(Fb.sf);
                     }}, FloatSqrtOp);
 #endif
                     0x2b: sqrtt({{
                         if (Fb < 0.0)
-                            fault = ArithmeticFault;
+                            fault = new ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
                 }
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = Fb.uq<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = IntegerOverflowFault;
+                    fault = new IntegerOverflowFault;
                 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
             }});
 
@@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() {
              && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
-            fault = UnimplementedOpcodeFault;
+            fault = new UnimplementedOpcodeFault;
         }
         else {
             // check to see if simulator wants to do something special
@@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() {
         0x19: hw_mfpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = UnimplementedOpcodeFault;
+                fault = new UnimplementedOpcodeFault;
             }
             else {
                 Ra = xc->readIpr(ipr_index, fault);
@@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() {
         0x1d: hw_mtpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = UnimplementedOpcodeFault;
+                fault = new UnimplementedOpcodeFault;
             }
             else {
                 xc->setIpr(ipr_index, Ra);
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 7e81fb830..2ee714b0f 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -36,7 +36,7 @@ output exec {{
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
         if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
-            fault = FloatEnableFault;
+            fault = new FloatEnableFault;
         }
         return fault;
     }
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index de4ac3eaf..09df39706 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     Fault
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 4601b3684..47d166255 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 }};
 
diff --git a/base/refcnt.hh b/base/refcnt.hh
index 9d9ed4337..de589f7c5 100644
--- a/base/refcnt.hh
+++ b/base/refcnt.hh
@@ -29,6 +29,8 @@
 #ifndef __REFCNT_HH__
 #define __REFCNT_HH__
 
+#include <stddef.h> //For the NULL macro definition
+
 class RefCounted
 {
   private:
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 86314bef1..296717f2a 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -113,7 +113,7 @@ BaseDynInst<Impl>::initVars()
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
-    fault = UnimplementedOpcodeFault;
+    fault = new UnimplementedOpcodeFault;
 
     ++instcount;
 
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 7ec1ba663..c0ec1fb33 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei()
     uint64_t *ipr = getIpr();
 
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
     this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault)
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
-    this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+    DPRINTF(Fault, "Fault %s\n", fault->name());
+    this->recordEvent(csprintf("Fault %s", fault->name()));
 
-//    kernelStats.fault(fault);
+    //kernelStats.fault(fault);
 
-    if (fault == ArithmeticFault)
+    if (fault->isA<ArithmeticFault>())
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
-    if (fault != InterruptFault || !inPalMode(PC))
+    if (!fault->isA<InterruptFault>() || !inPalMode(PC))
         ipr[AlphaISA::IPR_EXC_ADDR] = PC;
 
-    if (fault == PalFault || fault == ArithmeticFault /* ||
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
         fault == InterruptFault && !PC_PAL(regs.pc) */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index ee7b8858e..7e36a6ead 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
       case TheISA::IPR_DTB_IAP:
       case TheISA::IPR_ITB_IA:
       case TheISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
     }
 
@@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
       case TheISA::IPR_ITB_PTE_TEMP:
       case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
       case TheISA::IPR_HWINT_CLR:
       case TheISA::IPR_SL_XMIT:
@@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     // no error...
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index f7a6d2c21..d6f2ffd9f 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -334,7 +334,7 @@ SimpleCPU::copySrcTranslate(Addr src)
     // translate to physical address
     Fault fault = xc->translateDataReadReq(memReq);
 
-    assert(fault != AlignmentFault);
+    assert(!fault->isA<AlignmentFault>());
 
     if (fault == NoFault) {
         xc->copySrcAddr = src;
@@ -369,7 +369,7 @@ SimpleCPU::copy(Addr dest)
     // translate to physical address
     Fault fault = xc->translateDataWriteReq(memReq);
 
-    assert(fault != AlignmentFault);
+    assert(!fault->isA<AlignmentFault>());
 
     if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
@@ -675,7 +675,7 @@ SimpleCPU::tick()
         if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
             ipr[IPR_ISR] = summary;
             ipr[IPR_INTID] = ipl;
-            xc->ev5_trap(InterruptFault);
+            xc->ev5_trap(new InterruptFault);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                     ipr[IPR_IPLR], ipl, summary);
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 0f36e63fb..87d8c4e93 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -184,7 +184,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
             }
             break;
         default:
-            return MachineCheckFault;
+            return new MachineCheckFault;
     }
 
     return NoFault;
@@ -204,7 +204,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
         val = *(uint64_t *)data;
         break;
       default:
-        return MachineCheckFault;
+        return new MachineCheckFault;
     }
 
     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -257,7 +257,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
         break;
 
       default:
-        return MachineCheckFault;
+        return new MachineCheckFault;
     }
 
     return NoFault;
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index 9427463bf..4f08c2cf9 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -272,7 +272,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
         return readBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return readBar5(req, req->paddr - BARAddrs[5], data);
-    return MachineCheckFault;
+    return new MachineCheckFault;
 }
 
 inline Fault
@@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
         return writeBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return writeBar5(req, req->paddr - BARAddrs[5], data);
-    return MachineCheckFault;
+    return new MachineCheckFault;
 }
 
 #endif // __DEV_PCIDEV_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index c499d2f49..3f7226817 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
     assert(config.command & PCI_CMD_MSE);
     Fault fault = readBar(req, data);
 
-    if (fault == MachineCheckFault) {
+    if (fault->isA<MachineCheckFault>()) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
               req->paddr, req->vaddr, req->size);
 
-        return MachineCheckFault;
+        return new MachineCheckFault;
     }
 
     return fault;
@@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
     assert(config.command & PCI_CMD_MSE);
     Fault fault = writeBar(req, data);
 
-    if (fault == MachineCheckFault) {
+    if (fault->isA<MachineCheckFault>()) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
               req->paddr, req->vaddr, req->size);
 
-        return MachineCheckFault;
+        return new MachineCheckFault;
     }
 
     return fault;
@@ -489,12 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
         panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
               info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
 
+    //These are commmented out because when the DPRINTF below isn't used,
+    //these values aren't used and gcc issues a warning. With -Werror,
+    //this prevents compilation.
     //uint32_t reg32 = *(uint32_t *)data;
-    uint64_t reg64 = *(uint64_t *)data;
+    //uint64_t reg64 = *(uint64_t *)data;
     DPRINTF(EthernetPIO,
             "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
-            info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr,
-            req->paddr, req->vaddr, req->size);
+            info.name, cpu, info.size == 4 ?
+            (*(uint32_t *)data) :
+            (*(uint32_t *)data),
+            daddr, req->paddr, req->vaddr, req->size);
 
     prepareWrite(cpu, index);
 
diff --git a/kern/kernel_stats.cc b/kern/kernel_stats.cc
index 50bbaee00..31a3049f1 100644
--- a/kern/kernel_stats.cc
+++ b/kern/kernel_stats.cc
@@ -136,7 +136,7 @@ Statistics::regStats(const string &_name)
         }
     }
 
-    _faults
+/*    _faults
         .init(NumFaults)
         .name(name() + ".faults")
         .desc("number of faults")
@@ -147,7 +147,7 @@ Statistics::regStats(const string &_name)
         const char *str = (*ListOfFaults[i])->name;
         if (str)
             _faults.subname(i, str);
-    }
+    }*/
 
     _mode
         .init(cpu_mode_num)
diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh
index 02d78e4d9..4896a0705 100644
--- a/kern/kernel_stats.hh
+++ b/kern/kernel_stats.hh
@@ -151,7 +151,7 @@ class Statistics : public Serializable
 
     Stats::Vector<> _callpal;
     Stats::Vector<> _syscall;
-    Stats::Vector<> _faults;
+//    Stats::Vector<> _faults;
 
     Stats::Vector<> _mode;
     Stats::Vector<> _modeGood;
@@ -178,10 +178,8 @@ class Statistics : public Serializable
     void hwrei() { _hwrei++; }
     void fault(Fault fault)
     {
-            if(fault == NoFault) _faults[0]++;
-            else if(fault == MachineCheckFault) _faults[2]++;
-            else if(fault == AlignmentFault) _faults[7]++;
-            else _faults[fault->id]++;
+            if(fault != NoFault)
+                fault->stat()++;
     }// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; }
     void swpipl(int ipl);
     void mode(cpu_mode newmode);
diff --git a/sim/faults.cc b/sim/faults.cc
index 58a631263..17efaf1c4 100644
--- a/sim/faults.cc
+++ b/sim/faults.cc
@@ -28,9 +28,8 @@
 
 #include "sim/faults.hh"
 
-NoFaultType * const NoFault = new NoFaultType("none");
-MachineCheckFaultType * const MachineCheckFault =
-    new MachineCheckFaultType("mchk");
-AlignmentFaultType * const AlignmentFault =
-    new AlignmentFaultType("unalign");
+FaultName MachineCheckFault::_name = "mchk";
+FaultStat MachineCheckFault::_stat;
+FaultName AlignmentFault::_name = "unalign";
+FaultStat AlignmentFault::_stat;
 
diff --git a/sim/faults.hh b/sim/faults.hh
index dbec399af..ea2e21a7d 100644
--- a/sim/faults.hh
+++ b/sim/faults.hh
@@ -29,34 +29,55 @@
 #ifndef __FAULTS_HH__
 #define __FAULTS_HH__
 
+#include "base/refcnt.hh"
+#include "sim/stats.hh"
+
 class FaultBase;
-typedef FaultBase * Fault;
+typedef RefCountingPtr<FaultBase> Fault;
+
+typedef const char * FaultName;
+typedef Stats::Scalar<> FaultStat;
+
+// Each class has it's name statically define in _name,
+// and has a virtual function to access it's name.
+// The function is necessary because otherwise, all objects
+// which are being accessed cast as a FaultBase * (namely
+// all faults returned using the Fault type) will use the
+// generic FaultBase name.
 
-class FaultBase
+class FaultBase : public RefCounted
 {
-public:
-        FaultBase(char * newName, int newId = 0) : name(newName), id(newId) {;}
-        const char * name;
-        int id;
+  public:
+    virtual FaultName name()
+    {
+        return "none";
+    }
+    virtual FaultStat & stat() = 0;
+    template<typename T>
+    bool isA() {return dynamic_cast<T *>(this);}
 };
 
-extern class NoFaultType : public FaultBase
-{
-public:
-        NoFaultType(char * newName) : FaultBase(newName) {;}
-} * const NoFault;
+static FaultBase * const NoFault __attribute__ ((unused)) = 0;
 
-extern class MachineCheckFaultType : public FaultBase
+class MachineCheckFault : public FaultBase
 {
-public:
-        MachineCheckFaultType(char * newName) : FaultBase(newName) {;}
-} * const MachineCheckFault;
+  private:
+    static FaultName _name;
+    static FaultStat _stat;
+  public:
+    FaultName name() {return _name;}
+    FaultStat & stat() {return _stat;}
+};
 
-extern class AlignmentFaultType : public FaultBase
+class AlignmentFault : public FaultBase
 {
-public:
-        AlignmentFaultType(char * newName) : FaultBase(newName) {;}
-} * const AlignmentFault;
+  private:
+    static FaultName _name;
+    static FaultStat _stat;
+  public:
+    FaultName name() {return _name;}
+    FaultStat & stat() {return _stat;}
+};
 
 
 #endif // __FAULTS_HH__