diff options
| author | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-01-22 10:42:13 -0500 |
|---|---|---|
| committer | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-01-22 10:42:13 -0500 |
| commit | 1285d639eba6b95e31fb2b4aacae524d04ddf981 (patch) | |
| tree | 5e5ac3721c5066c279b34b5de537c4a59323a087 | |
| parent | dcd8eeec3bdb2aad8ffb4a88e0a5fa5a7237eb07 (diff) | |
| download | gem5-1285d639eba6b95e31fb2b4aacae524d04ddf981.tar.xz | |
stats: update stats to after GPU checkin
319 files changed, 5525 insertions, 8354 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index d774e7e6d..9073173b3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -29,7 +30,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index a2b6d76b5..2611d2bca 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:39 -gem5 executing on zizzer, pid 26207 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:49:59 +gem5 executing on zizzer, pid 33958 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 99a6252ce..f73eb8157 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926044 # Simulator instruction rate (inst/s) -host_op_rate 926044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26632227382 # Simulator tick rate (ticks/s) -host_mem_usage 313988 # Number of bytes of host memory used -host_seconds 70.19 # Real time elapsed on the host +host_inst_rate 1016587 # Simulator instruction rate (inst/s) +host_op_rate 1016586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29236138105 # Simulator tick rate (ticks/s) +host_mem_usage 314344 # Number of bytes of host memory used +host_seconds 63.94 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 9a274ff4a..89e440df7 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -29,7 +30,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 447da0deb..29ef5c756 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26161 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:02 +gem5 executing on zizzer, pid 33997 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 92dbfb48e..be6733354 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025442 # Simulator instruction rate (inst/s) -host_op_rate 1025441 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31244562480 # Simulator tick rate (ticks/s) -host_mem_usage 310964 # Number of bytes of host memory used -host_seconds 58.55 # Real time elapsed on the host +host_inst_rate 996309 # Simulator instruction rate (inst/s) +host_op_rate 996308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30356892493 # Simulator tick rate (ticks/s) +host_mem_usage 311076 # Number of bytes of host memory used +host_seconds 60.26 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index bc0198339..532d7e553 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -29,7 +30,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 992e005bc..8c170a1b4 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:27 -gem5 executing on zizzer, pid 26155 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33973 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 15d06f64d..a1e8c67e3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.982594 # Nu sim_ticks 1982594146000 # Number of ticks simulated final_tick 1982594146000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 454315 # Simulator instruction rate (inst/s) -host_op_rate 454314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14768552865 # Simulator tick rate (ticks/s) -host_mem_usage 314396 # Number of bytes of host memory used -host_seconds 134.24 # Real time elapsed on the host +host_inst_rate 452083 # Simulator instruction rate (inst/s) +host_op_rate 452083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14696000274 # Simulator tick rate (ticks/s) +host_mem_usage 314492 # Number of bytes of host memory used +host_seconds 134.91 # Real time elapsed on the host sim_insts 60989111 # Number of instructions simulated sim_ops 60989111 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 275579678..0500c7948 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -29,7 +30,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 9671fd6ad..c20bdaa30 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26167 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:01 +gem5 executing on zizzer, pid 33982 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index b181fc0e4..bc2bfd41e 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 457137 # Simulator instruction rate (inst/s) -host_op_rate 457137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15795402578 # Simulator tick rate (ticks/s) -host_mem_usage 311136 # Number of bytes of host memory used -host_seconds 122.90 # Real time elapsed on the host +host_inst_rate 450874 # Simulator instruction rate (inst/s) +host_op_rate 450874 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15578984909 # Simulator tick rate (ticks/s) +host_mem_usage 311244 # Number of bytes of host memory used +host_seconds 124.61 # Real time elapsed on the host sim_insts 56182743 # Number of instructions simulated sim_ops 56182743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini index 8ed798848..c979f0275 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json index 3ba0565bb..1eb19f804 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json @@ -62,7 +62,7 @@ "frontend_latency": 2 }, "symbolfile": "", - "readfile": "/z/atgutier/gem5/gem5/tests/halt.sh", + "readfile": "/z/atgutier/gem5/gem5-commit/tests/halt.sh", "have_large_asid_64": false, "phys_addr_range_64": 40, "have_lpae": false, @@ -1166,6 +1166,7 @@ }, "multi_thread": false, "eventq_index": 0, + "work_begin_cpu_id_exit": -1, "iocache": { "cpu_side": { "peer": "system.iobus.master[25]", @@ -1759,11 +1760,11 @@ "system.realview.nvmem", "system.realview.vram" ], - "work_begin_cpu_id_exit": -1, + "num_work_ids": 16, "boot_loader": [ "/dist/m5/system/binaries/boot_emm.arm" ], - "num_work_ids": 16 + "exit_on_work_items": false }, "time_sync_period": 100000000000, "eventq_index": 0, diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 7eec0da3f..e4317ec15 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 800554 # Simulator instruction rate (inst/s) -host_op_rate 974547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15609662339 # Simulator tick rate (ticks/s) -host_mem_usage 562564 # Number of bytes of host memory used -host_seconds 178.34 # Real time elapsed on the host +host_inst_rate 624684 # Simulator instruction rate (inst/s) +host_op_rate 760453 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12180447765 # Simulator tick rate (ticks/s) +host_mem_usage 563036 # Number of bytes of host memory used +host_seconds 228.55 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 43999bf3e..f038e832c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 71adc2e8a..fc8f06b10 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11544 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:21 +gem5 executing on zizzer, pid 20729 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 2c3cae8d4..c3e49583c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 586939 # Simulator instruction rate (inst/s) -host_op_rate 715176 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11204428729 # Simulator tick rate (ticks/s) -host_mem_usage 574332 # Number of bytes of host memory used -host_seconds 250.16 # Real time elapsed on the host +host_inst_rate 526774 # Simulator instruction rate (inst/s) +host_op_rate 641866 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10055912327 # Simulator tick rate (ticks/s) +host_mem_usage 575028 # Number of bytes of host memory used +host_seconds 278.73 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 8ed798848..c979f0275 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 1b874fd24..3e281e699 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:33 -gem5 executing on zizzer, pid 11584 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:33 +gem5 executing on zizzer, pid 20752 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 94341d583..4c4524faa 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 616731 # Simulator instruction rate (inst/s) -host_op_rate 750771 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12025369468 # Simulator tick rate (ticks/s) -host_mem_usage 560084 # Number of bytes of host memory used -host_seconds 231.50 # Real time elapsed on the host +host_inst_rate 540254 # Simulator instruction rate (inst/s) +host_op_rate 657673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10534181577 # Simulator tick rate (ticks/s) +host_mem_usage 560556 # Number of bytes of host memory used +host_seconds 264.27 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 17dc633da..527014097 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index fa9d5b412..b84516300 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:09 -gem5 executing on zizzer, pid 11535 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:19 +gem5 executing on zizzer, pid 20717 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 38a008262..35b76497a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.871850 # Nu sim_ticks 2871850306000 # Number of ticks simulated final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357173 # Simulator instruction rate (inst/s) -host_op_rate 432014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7797571327 # Simulator tick rate (ticks/s) -host_mem_usage 598232 # Number of bytes of host memory used -host_seconds 368.30 # Real time elapsed on the host +host_inst_rate 312956 # Simulator instruction rate (inst/s) +host_op_rate 378531 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6832247646 # Simulator tick rate (ticks/s) +host_mem_usage 599868 # Number of bytes of host memory used +host_seconds 420.34 # Real time elapsed on the host sim_insts 131546959 # Number of instructions simulated sim_ops 159110973 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 72a3cff31..f7f13cbec 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index fee276a51..244ffaad4 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:09 -gem5 executing on zizzer, pid 11541 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:47:16 +gem5 executing on zizzer, pid 20794 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c15b96098..b6b1f5126 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909596 # Nu sim_ticks 2909596171500 # Number of ticks simulated final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 364808 # Simulator instruction rate (inst/s) -host_op_rate 439844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9438806072 # Simulator tick rate (ticks/s) -host_mem_usage 560272 # Number of bytes of host memory used -host_seconds 308.26 # Real time elapsed on the host +host_inst_rate 322522 # Simulator instruction rate (inst/s) +host_op_rate 388861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8344730622 # Simulator tick rate (ticks/s) +host_mem_usage 560756 # Number of bytes of host memory used +host_seconds 348.67 # Real time elapsed on the host sim_insts 112455206 # Number of instructions simulated sim_ops 135585876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index c32dad5e4..c304518f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 6dd2a3890..524799440 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11555 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:19 +gem5 executing on zizzer, pid 20712 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 2387ad56e..db18bd84f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596623 # Simulator instruction rate (inst/s) -host_op_rate 726292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11633285247 # Simulator tick rate (ticks/s) -host_mem_usage 560420 # Number of bytes of host memory used -host_seconds 239.30 # Real time elapsed on the host +host_inst_rate 540105 # Simulator instruction rate (inst/s) +host_op_rate 657491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10531274508 # Simulator tick rate (ticks/s) +host_mem_usage 560892 # Number of bytes of host memory used +host_seconds 264.34 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index e78625aa6..87f5d9e1f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -20,6 +20,7 @@ dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.d early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 8b89565b1..40c7f8e08 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:22 -gem5 executing on zizzer, pid 11577 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:19 +gem5 executing on zizzer, pid 20720 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a58edf131..5188d100d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909671 # Nu sim_ticks 2909670971500 # Number of ticks simulated final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 363443 # Simulator instruction rate (inst/s) -host_op_rate 438198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9403770867 # Simulator tick rate (ticks/s) -host_mem_usage 560672 # Number of bytes of host memory used -host_seconds 309.42 # Real time elapsed on the host +host_inst_rate 317481 # Simulator instruction rate (inst/s) +host_op_rate 382781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8214526706 # Simulator tick rate (ticks/s) +host_mem_usage 561408 # Number of bytes of host memory used +host_seconds 354.21 # Real time elapsed on the host sim_insts 112454909 # Number of instructions simulated sim_ops 135585028 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index e3329c066..7b732e972 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table eventq_index=0 +exit_on_work_items=false init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table @@ -30,7 +31,7 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 734ae5b70..a22bab273 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:47 -gem5 executing on zizzer, pid 10148 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:54 +gem5 executing on zizzer, pid 17910 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index c8d7b7f68..ed0884673 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 631335 # Simulator instruction rate (inst/s) -host_op_rate 1292481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16132023743 # Simulator tick rate (ticks/s) -host_mem_usage 604612 # Number of bytes of host memory used -host_seconds 316.89 # Real time elapsed on the host +host_inst_rate 646932 # Simulator instruction rate (inst/s) +host_op_rate 1324411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16530551683 # Simulator tick rate (ticks/s) +host_mem_usage 604676 # Number of bytes of host memory used +host_seconds 309.26 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 0e7691f12..ce3929150 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -17,6 +17,7 @@ cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table eventq_index=0 +exit_on_work_items=false init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table @@ -30,7 +31,7 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -readfile=/z/atgutier/gem5/gem5/tests/halt.sh +readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 77626de71..c701b43e7 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:47 -gem5 executing on zizzer, pid 10143 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:53 +gem5 executing on zizzer, pid 17907 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 68578a568..0929c11b9 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.194947 # Nu sim_ticks 5194947216500 # Number of ticks simulated final_tick 5194947216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 409072 # Simulator instruction rate (inst/s) -host_op_rate 788480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16545970820 # Simulator tick rate (ticks/s) -host_mem_usage 604904 # Number of bytes of host memory used -host_seconds 313.97 # Real time elapsed on the host +host_inst_rate 404245 # Simulator instruction rate (inst/s) +host_op_rate 779175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16350714303 # Simulator tick rate (ticks/s) +host_mem_usage 604972 # Number of bytes of host memory used +host_seconds 317.72 # Real time elapsed on the host sim_insts 128436556 # Number of instructions simulated sim_ops 247559476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index bd9261d3d..edd8d3427 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -7,6 +7,7 @@ cache_line_size=64 clk_domain=drivesys.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -19,7 +20,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/configs/boot/netperf-server.rcS +readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -935,6 +936,7 @@ cache_line_size=64 clk_domain=testsys.clk_domain console=/dist/m5/system/binaries/console eventq_index=0 +exit_on_work_items=false init_param=0 kernel=/dist/m5/system/binaries/vmlinux kernel_addr_check=true @@ -947,7 +949,7 @@ mmap_using_noreserve=false multi_thread=false num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/atgutier/gem5/gem5/configs/boot/netperf-stream-client.rcS +readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 8833276c4..66af1fa79 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:29 -gem5 executing on zizzer, pid 26179 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:49:59 +gem5 executing on zizzer, pid 33962 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 9eb97edfc..d62937167 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409271000 # Number of ticks simulated final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7045290 # Simulator instruction rate (inst/s) -host_op_rate 7045287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2695669073 # Simulator tick rate (ticks/s) -host_mem_usage 476352 # Number of bytes of host memory used -host_seconds 74.35 # Real time elapsed on the host +host_inst_rate 7747436 # Simulator instruction rate (inst/s) +host_op_rate 7747432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2964324473 # Simulator tick rate (ticks/s) +host_mem_usage 475456 # Number of bytes of host memory used +host_seconds 67.61 # Real time elapsed on the host sim_insts 523780905 # Number of instructions simulated sim_ops 523780905 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -619,10 +619,10 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3614433690 # Simulator instruction rate (inst/s) -host_op_rate 3613747861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2809493050 # Simulator tick rate (ticks/s) -host_mem_usage 476352 # Number of bytes of host memory used +host_inst_rate 3441354505 # Simulator instruction rate (inst/s) +host_op_rate 3440623178 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2674872126 # Simulator tick rate (ticks/s) +host_mem_usage 475456 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 523853183 # Number of instructions simulated sim_ops 523853183 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini index fb1673614..e5dcce47a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout index ae2f8fd23..f7ce5dfcd 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:52 -gem5 executing on zizzer, pid 26256 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:03 +gem5 executing on zizzer, pid 34007 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 051d35abb..8f96a67ee 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000038 # Nu sim_ticks 37553000 # Number of ticks simulated final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64031 # Simulator instruction rate (inst/s) -host_op_rate 64014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 375517232 # Simulator tick rate (ticks/s) -host_mem_usage 231080 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 69445 # Simulator instruction rate (inst/s) +host_op_rate 69425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 407253641 # Simulator tick rate (ticks/s) +host_mem_usage 231420 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 40e913ae9..71d6eb660 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 201161d66..f25c1e64c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:27 -gem5 executing on zizzer, pid 26149 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:25 +gem5 executing on zizzer, pid 34061 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index f28e78282..eafeb49bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48553 # Simulator instruction rate (inst/s) -host_op_rate 48543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 166810792 # Simulator tick rate (ticks/s) -host_mem_usage 232316 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 26026 # Simulator instruction rate (inst/s) +host_op_rate 26023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89433474 # Simulator tick rate (ticks/s) +host_mem_usage 232656 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index fb042e40a..ab97850f7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index 4b338add9..7d01b9cb4 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26169 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:02 +gem5 executing on zizzer, pid 34000 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 1c84af69c..ec5525b66 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110246 # Simulator instruction rate (inst/s) -host_op_rate 110196 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55296654 # Simulator tick rate (ticks/s) -host_mem_usage 220244 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 146057 # Simulator instruction rate (inst/s) +host_op_rate 145971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73240755 # Simulator tick rate (ticks/s) +host_mem_usage 220608 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini index 2f82cfc61..7e399d299 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -335,6 +336,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -358,6 +360,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -438,12 +441,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -515,6 +520,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1188,6 +1194,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout index 6660c12a2..f1833345c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:05:44 -gem5 started Dec 11 2015 20:06:17 -gem5 executing on zizzer, pid 37024 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level +gem5 compiled Jan 21 2016 14:01:33 +gem5 started Jan 21 2016 14:02:10 +gem5 executing on zizzer, pid 44721 +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 3c73fad9b..0ee8e01b1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000121 # Nu sim_ticks 121460 # Number of ticks simulated final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18505 # Simulator instruction rate (inst/s) -host_op_rate 18504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 351701 # Simulator tick rate (ticks/s) -host_mem_usage 388732 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host +host_inst_rate 19821 # Simulator instruction rate (inst/s) +host_op_rate 19819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 376677 # Simulator tick rate (ticks/s) +host_mem_usage 390876 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -365,36 +365,36 @@ system.ruby.delayHist::mean 0.164852 # de system.ruby.delayHist::stdev 1.012053 # delay histogram for all message system.ruby.delayHist | 9285 96.27% 96.27% | 0 0.00% 96.27% | 215 2.23% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 9645 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.377367 -system.ruby.latency_hist::gmean 2.098947 -system.ruby.latency_hist::stdev 29.666839 -system.ruby.latency_hist | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6958 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6958 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1490 -system.ruby.miss_latency_hist::mean 71.177181 -system.ruby.miss_latency_hist::gmean 66.939744 -system.ruby.miss_latency_hist::stdev 30.560087 -system.ruby.miss_latency_hist | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1490 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8448 +system.ruby.latency_hist_seqr::mean 13.377367 +system.ruby.latency_hist_seqr::gmean 2.098947 +system.ruby.latency_hist_seqr::stdev 29.666839 +system.ruby.latency_hist_seqr | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8448 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 6958 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6958 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1490 +system.ruby.miss_latency_hist_seqr::mean 71.177181 +system.ruby.miss_latency_hist_seqr::gmean 66.939744 +system.ruby.miss_latency_hist_seqr::stdev 30.560087 +system.ruby.miss_latency_hist_seqr | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses @@ -588,75 +588,75 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 -system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 33.972105 -system.ruby.LD.latency_hist::gmean 7.701642 -system.ruby.LD.latency_hist::stdev 40.478944 -system.ruby.LD.latency_hist | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1183 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 600 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 600 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 -system.ruby.LD.miss_latency_hist::samples 583 -system.ruby.LD.miss_latency_hist::mean 67.905660 -system.ruby.LD.miss_latency_hist::gmean 62.953372 -system.ruby.LD.miss_latency_hist::stdev 32.457951 -system.ruby.LD.miss_latency_hist | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 583 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 15.273988 -system.ruby.ST.latency_hist::gmean 2.701326 -system.ruby.ST.latency_hist::stdev 28.276128 -system.ruby.ST.latency_hist | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 865 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 649 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 649 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 -system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 58.162037 -system.ruby.ST.miss_latency_hist::gmean 53.494090 -system.ruby.ST.miss_latency_hist::stdev 27.387260 -system.ruby.ST.miss_latency_hist | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 216 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 9.314219 -system.ruby.IFETCH.latency_hist::gmean 1.595263 -system.ruby.IFETCH.latency_hist::stdev 25.608064 -system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 6400 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 5709 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5709 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 78.005789 -system.ruby.IFETCH.miss_latency_hist::gmean 75.617268 -system.ruby.IFETCH.miss_latency_hist::stdev 28.004761 -system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 691 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1183 +system.ruby.LD.latency_hist_seqr::mean 33.972105 +system.ruby.LD.latency_hist_seqr::gmean 7.701642 +system.ruby.LD.latency_hist_seqr::stdev 40.478944 +system.ruby.LD.latency_hist_seqr | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 600 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 600 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 583 +system.ruby.LD.miss_latency_hist_seqr::mean 67.905660 +system.ruby.LD.miss_latency_hist_seqr::gmean 62.953372 +system.ruby.LD.miss_latency_hist_seqr::stdev 32.457951 +system.ruby.LD.miss_latency_hist_seqr | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 583 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 865 +system.ruby.ST.latency_hist_seqr::mean 15.273988 +system.ruby.ST.latency_hist_seqr::gmean 2.701326 +system.ruby.ST.latency_hist_seqr::stdev 28.276128 +system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 865 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 649 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 649 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 216 +system.ruby.ST.miss_latency_hist_seqr::mean 58.162037 +system.ruby.ST.miss_latency_hist_seqr::gmean 53.494090 +system.ruby.ST.miss_latency_hist_seqr::stdev 27.387260 +system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 216 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6400 +system.ruby.IFETCH.latency_hist_seqr::mean 9.314219 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.595263 +system.ruby.IFETCH.latency_hist_seqr::stdev 25.608064 +system.ruby.IFETCH.latency_hist_seqr | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5709 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5709 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 691 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.005789 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.617268 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.004761 +system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 691 system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% system.ruby.Directory_Controller.Data 277 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 5e7327df9..87378aae3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -340,6 +341,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -363,6 +365,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -424,12 +427,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -508,6 +513,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1180,6 +1186,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 65a7be2f0..ce03b27b1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:10:49 -gem5 started Dec 11 2015 20:11:27 -gem5 executing on zizzer, pid 42477 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Jan 21 2016 14:06:59 +gem5 started Jan 21 2016 14:07:35 +gem5 executing on zizzer, pid 50076 +command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 4471f5bfb..8c7fdbc65 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu sim_ticks 108694 # Number of ticks simulated final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21195 # Simulator instruction rate (inst/s) -host_op_rate 21193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360456 # Simulator tick rate (ticks/s) -host_mem_usage 391840 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 18329 # Simulator instruction rate (inst/s) +host_op_rate 18327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 311726 # Simulator tick rate (ticks/s) +host_mem_usage 397240 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -359,36 +359,36 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 11.866241 -system.ruby.latency_hist::gmean 1.974485 -system.ruby.latency_hist::stdev 27.814086 -system.ruby.latency_hist | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 7027 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7027 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1421 -system.ruby.miss_latency_hist::mean 65.600985 -system.ruby.miss_latency_hist::gmean 57.082853 -system.ruby.miss_latency_hist::stdev 33.588801 -system.ruby.miss_latency_hist | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1421 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8448 +system.ruby.latency_hist_seqr::mean 11.866241 +system.ruby.latency_hist_seqr::gmean 1.974485 +system.ruby.latency_hist_seqr::stdev 27.814086 +system.ruby.latency_hist_seqr | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8448 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 7027 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7027 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1421 +system.ruby.miss_latency_hist_seqr::mean 65.600985 +system.ruby.miss_latency_hist_seqr::gmean 57.082853 +system.ruby.miss_latency_hist_seqr::stdev 33.588801 +system.ruby.miss_latency_hist_seqr | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses @@ -556,75 +556,75 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9456 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 -system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 27.265427 -system.ruby.LD.latency_hist::gmean 5.733715 -system.ruby.LD.latency_hist::stdev 35.817674 -system.ruby.LD.latency_hist | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1183 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 658 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 658 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 -system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 60.184762 -system.ruby.LD.miss_latency_hist::gmean 51.169278 -system.ruby.LD.miss_latency_hist::stdev 30.689440 -system.ruby.LD.miss_latency_hist | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 525 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.593064 -system.ruby.ST.latency_hist::gmean 3.080574 -system.ruby.ST.latency_hist::stdev 34.156278 -system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 865 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 615 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 615 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 -system.ruby.ST.miss_latency_hist::samples 250 -system.ruby.ST.miss_latency_hist::mean 58.412000 -system.ruby.ST.miss_latency_hist::gmean 49.053018 -system.ruby.ST.miss_latency_hist::stdev 41.173185 -system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 250 -system.ruby.IFETCH.latency_hist::bucket_size 32 -system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 8.245781 -system.ruby.IFETCH.latency_hist::gmean 1.526741 -system.ruby.IFETCH.latency_hist::stdev 23.776931 -system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00% -system.ruby.IFETCH.latency_hist::total 6400 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 5754 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5754 -system.ruby.IFETCH.miss_latency_hist::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 72.784830 -system.ruby.IFETCH.miss_latency_hist::gmean 66.158480 -system.ruby.IFETCH.miss_latency_hist::stdev 31.122591 -system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 646 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1183 +system.ruby.LD.latency_hist_seqr::mean 27.265427 +system.ruby.LD.latency_hist_seqr::gmean 5.733715 +system.ruby.LD.latency_hist_seqr::stdev 35.817674 +system.ruby.LD.latency_hist_seqr | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 658 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 658 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 525 +system.ruby.LD.miss_latency_hist_seqr::mean 60.184762 +system.ruby.LD.miss_latency_hist_seqr::gmean 51.169278 +system.ruby.LD.miss_latency_hist_seqr::stdev 30.689440 +system.ruby.LD.miss_latency_hist_seqr | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 525 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 865 +system.ruby.ST.latency_hist_seqr::mean 17.593064 +system.ruby.ST.latency_hist_seqr::gmean 3.080574 +system.ruby.ST.latency_hist_seqr::stdev 34.156278 +system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 865 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 615 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 615 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 250 +system.ruby.ST.miss_latency_hist_seqr::mean 58.412000 +system.ruby.ST.miss_latency_hist_seqr::gmean 49.053018 +system.ruby.ST.miss_latency_hist_seqr::stdev 41.173185 +system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 250 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 6400 +system.ruby.IFETCH.latency_hist_seqr::mean 8.245781 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.526741 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.776931 +system.ruby.IFETCH.latency_hist_seqr | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5754 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 646 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 72.784830 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.158480 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.122591 +system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 646 system.ruby.Directory_Controller.GETX 198 0.00% 0.00% system.ruby.Directory_Controller.GETS 984 0.00% 0.00% system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 2dfb9ce43..6857839bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -388,6 +389,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -411,6 +413,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -488,12 +491,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -567,6 +572,7 @@ slave=system.ruby.network.master[4] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1744,6 +1750,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index bb7c18a29..a72f8ac98 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:15:50 -gem5 started Dec 11 2015 20:16:20 -gem5 executing on zizzer, pid 47639 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Jan 21 2016 14:12:23 +gem5 started Jan 21 2016 14:12:59 +gem5 executing on zizzer, pid 55399 +command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index e60f5fd3d..d6192ccc7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 108253 # Number of ticks simulated final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16244 # Simulator instruction rate (inst/s) -host_op_rate 16243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275161 # Simulator tick rate (ticks/s) -host_mem_usage 389764 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host +host_inst_rate 33873 # Simulator instruction rate (inst/s) +host_op_rate 33870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 573730 # Simulator tick rate (ticks/s) +host_mem_usage 391892 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -357,38 +357,38 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 11.814039 -system.ruby.latency_hist::gmean 1.958059 -system.ruby.latency_hist::stdev 27.675120 -system.ruby.latency_hist | 7432 87.97% 87.97% | 995 11.78% 99.75% | 8 0.09% 99.85% | 3 0.04% 99.88% | 6 0.07% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 8 -system.ruby.hit_latency_hist::max_bucket 79 -system.ruby.hit_latency_hist::samples 7270 -system.ruby.hit_latency_hist::mean 1.637552 -system.ruby.hit_latency_hist::gmean 1.092853 -system.ruby.hit_latency_hist::stdev 3.762080 -system.ruby.hit_latency_hist | 7066 97.19% 97.19% | 0 0.00% 97.19% | 19 0.26% 97.46% | 184 2.53% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7270 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1178 -system.ruby.miss_latency_hist::mean 74.617997 -system.ruby.miss_latency_hist::gmean 71.587772 -system.ruby.miss_latency_hist::stdev 28.670099 -system.ruby.miss_latency_hist | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1178 -system.ruby.Directory.incomplete_times 1177 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8448 +system.ruby.latency_hist_seqr::mean 11.814039 +system.ruby.latency_hist_seqr::gmean 1.958059 +system.ruby.latency_hist_seqr::stdev 27.675120 +system.ruby.latency_hist_seqr | 7432 87.97% 87.97% | 995 11.78% 99.75% | 8 0.09% 99.85% | 3 0.04% 99.88% | 6 0.07% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8448 +system.ruby.hit_latency_hist_seqr::bucket_size 8 +system.ruby.hit_latency_hist_seqr::max_bucket 79 +system.ruby.hit_latency_hist_seqr::samples 7270 +system.ruby.hit_latency_hist_seqr::mean 1.637552 +system.ruby.hit_latency_hist_seqr::gmean 1.092853 +system.ruby.hit_latency_hist_seqr::stdev 3.762080 +system.ruby.hit_latency_hist_seqr | 7066 97.19% 97.19% | 0 0.00% 97.19% | 19 0.26% 97.46% | 184 2.53% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7270 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1178 +system.ruby.miss_latency_hist_seqr::mean 74.617997 +system.ruby.miss_latency_hist_seqr::gmean 71.587772 +system.ruby.miss_latency_hist_seqr::stdev 28.670099 +system.ruby.miss_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1178 +system.ruby.Directory.incomplete_times_seqr 1177 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1312 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 736 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses @@ -538,195 +538,195 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9560 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7736 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 208 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 -system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 28.775148 -system.ruby.LD.latency_hist::gmean 6.010104 -system.ruby.LD.latency_hist::stdev 37.379747 -system.ruby.LD.latency_hist | 842 71.17% 71.17% | 336 28.40% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1183 -system.ruby.LD.hit_latency_hist::bucket_size 4 -system.ruby.LD.hit_latency_hist::max_bucket 39 -system.ruby.LD.hit_latency_hist::samples 758 -system.ruby.LD.hit_latency_hist::mean 4.034301 -system.ruby.LD.hit_latency_hist::gmean 1.520848 -system.ruby.LD.hit_latency_hist::stdev 7.788579 -system.ruby.LD.hit_latency_hist | 658 86.81% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 100 13.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 758 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 -system.ruby.LD.miss_latency_hist::samples 425 -system.ruby.LD.miss_latency_hist::mean 72.901176 -system.ruby.LD.miss_latency_hist::gmean 69.708423 -system.ruby.LD.miss_latency_hist::stdev 27.218709 -system.ruby.LD.miss_latency_hist | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 425 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 14.011561 -system.ruby.ST.latency_hist::gmean 2.583043 -system.ruby.ST.latency_hist::stdev 26.009033 -system.ruby.ST.latency_hist | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 865 -system.ruby.ST.hit_latency_hist::bucket_size 4 -system.ruby.ST.hit_latency_hist::max_bucket 39 -system.ruby.ST.hit_latency_hist::samples 697 -system.ruby.ST.hit_latency_hist::mean 2.321377 -system.ruby.ST.hit_latency_hist::gmean 1.211206 -system.ruby.ST.hit_latency_hist::stdev 5.179814 -system.ruby.ST.hit_latency_hist | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 17 2.44% 96.27% | 26 3.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 697 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 168 -system.ruby.ST.miss_latency_hist::mean 62.511905 -system.ruby.ST.miss_latency_hist::gmean 59.804102 -system.ruby.ST.miss_latency_hist::stdev 21.242819 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 168 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 8.381875 -system.ruby.IFETCH.latency_hist::gmean 1.532979 -system.ruby.IFETCH.latency_hist::stdev 24.412953 -system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 571 8.92% 99.78% | 5 0.08% 99.86% | 2 0.03% 99.89% | 4 0.06% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 6400 -system.ruby.IFETCH.hit_latency_hist::bucket_size 8 -system.ruby.IFETCH.hit_latency_hist::max_bucket 79 -system.ruby.IFETCH.hit_latency_hist::samples 5815 -system.ruby.IFETCH.hit_latency_hist::mean 1.243164 -system.ruby.IFETCH.hit_latency_hist::gmean 1.033952 -system.ruby.IFETCH.hit_latency_hist::stdev 2.371578 -system.ruby.IFETCH.hit_latency_hist | 5754 98.95% 98.95% | 0 0.00% 98.95% | 2 0.03% 98.99% | 58 1.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5815 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 585 -system.ruby.IFETCH.miss_latency_hist::mean 79.341880 -system.ruby.IFETCH.miss_latency_hist::gmean 76.853466 -system.ruby.IFETCH.miss_latency_hist::stdev 30.381468 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 585 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 7066 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 7066 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 7066 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 8 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 79 -system.ruby.L2Cache.hit_mach_latency_hist::samples 204 -system.ruby.L2Cache.hit_mach_latency_hist::mean 23.720588 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 23.671773 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.608281 -system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 9.31% 9.31% | 184 90.20% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 204 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1178 -system.ruby.Directory.miss_mach_latency_hist::mean 74.617997 -system.ruby.Directory.miss_mach_latency_hist::gmean 71.587772 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.670099 -system.ruby.Directory.miss_mach_latency_hist | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1178 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 82 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 82.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 658 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 658 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 39 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 100 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 24 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 24.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 100 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 425 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 72.901176 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 69.708423 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 27.218709 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 425 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 654 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 654 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 4 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 39 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 43 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 22.418605 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 22.330941 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1.978847 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 26 60.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 43 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.511905 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 59.804102 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 21.242819 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 168 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 5754 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 5754 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 8 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 79 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 61 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 24.180328 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 24.114482 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 2.109567 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 3.28% 3.28% | 58 95.08% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 61 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.341880 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 76.853466 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 30.381468 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1183 +system.ruby.LD.latency_hist_seqr::mean 28.775148 +system.ruby.LD.latency_hist_seqr::gmean 6.010104 +system.ruby.LD.latency_hist_seqr::stdev 37.379747 +system.ruby.LD.latency_hist_seqr | 842 71.17% 71.17% | 336 28.40% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 +system.ruby.LD.hit_latency_hist_seqr::samples 758 +system.ruby.LD.hit_latency_hist_seqr::mean 4.034301 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.520848 +system.ruby.LD.hit_latency_hist_seqr::stdev 7.788579 +system.ruby.LD.hit_latency_hist_seqr | 658 86.81% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 100 13.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 758 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 425 +system.ruby.LD.miss_latency_hist_seqr::mean 72.901176 +system.ruby.LD.miss_latency_hist_seqr::gmean 69.708423 +system.ruby.LD.miss_latency_hist_seqr::stdev 27.218709 +system.ruby.LD.miss_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 425 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 865 +system.ruby.ST.latency_hist_seqr::mean 14.011561 +system.ruby.ST.latency_hist_seqr::gmean 2.583043 +system.ruby.ST.latency_hist_seqr::stdev 26.009033 +system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 865 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 +system.ruby.ST.hit_latency_hist_seqr::samples 697 +system.ruby.ST.hit_latency_hist_seqr::mean 2.321377 +system.ruby.ST.hit_latency_hist_seqr::gmean 1.211206 +system.ruby.ST.hit_latency_hist_seqr::stdev 5.179814 +system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 17 2.44% 96.27% | 26 3.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 697 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 168 +system.ruby.ST.miss_latency_hist_seqr::mean 62.511905 +system.ruby.ST.miss_latency_hist_seqr::gmean 59.804102 +system.ruby.ST.miss_latency_hist_seqr::stdev 21.242819 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 168 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6400 +system.ruby.IFETCH.latency_hist_seqr::mean 8.381875 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.532979 +system.ruby.IFETCH.latency_hist_seqr::stdev 24.412953 +system.ruby.IFETCH.latency_hist_seqr | 5815 90.86% 90.86% | 571 8.92% 99.78% | 5 0.08% 99.86% | 2 0.03% 99.89% | 4 0.06% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5815 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243164 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033952 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.371578 +system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.95% 98.95% | 0 0.00% 98.95% | 2 0.03% 98.99% | 58 1.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5815 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 585 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.341880 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.853466 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.381468 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 585 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7066 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7066 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7066 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.720588 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.671773 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.608281 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 9.31% 9.31% | 184 90.20% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1178 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.617997 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.587772 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.670099 +system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1178 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 24 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.901176 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.708423 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.218709 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 425 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.418605 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.330941 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.978847 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 26 60.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.511905 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.804102 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.242819 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.180328 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.114482 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.109567 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 3.28% 3.28% | 58 95.08% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.341880 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.853466 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.381468 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585 system.ruby.Directory_Controller.GETX 208 0.00% 0.00% system.ruby.Directory_Controller.GETS 1016 0.00% 0.00% system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 106f8065d..b9a8c8074 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -305,6 +306,7 @@ master=system.ruby.network.slave[3] type=RubyCache children=replacement_policy assoc=4 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -404,6 +406,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -427,6 +430,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -450,6 +454,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -511,12 +516,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1228,6 +1235,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 86036e7f0..2e0d7516c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:00:36 -gem5 started Dec 11 2015 20:01:07 -gem5 executing on zizzer, pid 31719 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +gem5 compiled Jan 21 2016 13:56:08 +gem5 started Jan 21 2016 13:56:42 +gem5 executing on zizzer, pid 39359 +command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index f0df25d0b..d98266934 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86673 # Number of ticks simulated final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24441 # Simulator instruction rate (inst/s) -host_op_rate 24439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 331452 # Simulator tick rate (ticks/s) -host_mem_usage 389356 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 26202 # Simulator instruction rate (inst/s) +host_op_rate 26199 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 355322 # Simulator tick rate (ticks/s) +host_mem_usage 391844 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -357,38 +357,38 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 9.259588 -system.ruby.latency_hist::gmean 1.841457 -system.ruby.latency_hist::stdev 22.233278 -system.ruby.latency_hist | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 7289 -system.ruby.hit_latency_hist::mean 1.278502 -system.ruby.hit_latency_hist::gmean 1.069062 -system.ruby.hit_latency_hist::stdev 1.645548 -system.ruby.hit_latency_hist | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7289 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 59.452977 -system.ruby.miss_latency_hist::gmean 56.282360 -system.ruby.miss_latency_hist::stdev 25.811948 -system.ruby.miss_latency_hist | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1159 -system.ruby.Directory.incomplete_times 1158 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8448 +system.ruby.latency_hist_seqr::mean 9.259588 +system.ruby.latency_hist_seqr::gmean 1.841457 +system.ruby.latency_hist_seqr::stdev 22.233278 +system.ruby.latency_hist_seqr | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8448 +system.ruby.hit_latency_hist_seqr::bucket_size 2 +system.ruby.hit_latency_hist_seqr::max_bucket 19 +system.ruby.hit_latency_hist_seqr::samples 7289 +system.ruby.hit_latency_hist_seqr::mean 1.278502 +system.ruby.hit_latency_hist_seqr::gmean 1.069062 +system.ruby.hit_latency_hist_seqr::stdev 1.645548 +system.ruby.hit_latency_hist_seqr | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7289 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1159 +system.ruby.miss_latency_hist_seqr::mean 59.452977 +system.ruby.miss_latency_hist_seqr::gmean 56.282360 +system.ruby.miss_latency_hist_seqr::stdev 25.811948 +system.ruby.miss_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1159 +system.ruby.Directory.incomplete_times_seqr 1158 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -506,192 +506,192 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 21.460693 -system.ruby.LD.latency_hist::gmean 5.052192 -system.ruby.LD.latency_hist::stdev 28.940454 -system.ruby.LD.latency_hist | 852 72.02% 72.02% | 242 20.46% 92.48% | 85 7.19% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1183 -system.ruby.LD.hit_latency_hist::bucket_size 2 -system.ruby.LD.hit_latency_hist::max_bucket 19 -system.ruby.LD.hit_latency_hist::samples 763 -system.ruby.LD.hit_latency_hist::mean 2.376147 -system.ruby.LD.hit_latency_hist::gmean 1.390948 -system.ruby.LD.hit_latency_hist::stdev 3.447211 -system.ruby.LD.hit_latency_hist | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 763 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 420 -system.ruby.LD.miss_latency_hist::mean 56.130952 -system.ruby.LD.miss_latency_hist::gmean 52.616261 -system.ruby.LD.miss_latency_hist::stdev 21.748058 -system.ruby.LD.miss_latency_hist | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 420 -system.ruby.ST.latency_hist::bucket_size 16 -system.ruby.ST.latency_hist::max_bucket 159 -system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 10.558382 -system.ruby.ST.latency_hist::gmean 2.225841 -system.ruby.ST.latency_hist::stdev 20.458667 -system.ruby.ST.latency_hist | 707 81.73% 81.73% | 45 5.20% 86.94% | 0 0.00% 86.94% | 76 8.79% 95.72% | 33 3.82% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 865 -system.ruby.ST.hit_latency_hist::bucket_size 2 -system.ruby.ST.hit_latency_hist::max_bucket 19 -system.ruby.ST.hit_latency_hist::samples 707 -system.ruby.ST.hit_latency_hist::mean 1.466761 -system.ruby.ST.hit_latency_hist::gmean 1.118428 -system.ruby.ST.hit_latency_hist::stdev 2.110935 -system.ruby.ST.hit_latency_hist | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 707 -system.ruby.ST.miss_latency_hist::bucket_size 16 -system.ruby.ST.miss_latency_hist::max_bucket 159 -system.ruby.ST.miss_latency_hist::samples 158 -system.ruby.ST.miss_latency_hist::mean 51.240506 -system.ruby.ST.miss_latency_hist::gmean 48.407659 -system.ruby.ST.miss_latency_hist::stdev 15.670342 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 158 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 6.828750 -system.ruby.IFETCH.latency_hist::gmean 1.489407 -system.ruby.IFETCH.latency_hist::stdev 20.190166 -system.ruby.IFETCH.latency_hist | 6294 98.34% 98.34% | 97 1.52% 99.86% | 0 0.00% 99.86% | 2 0.03% 99.89% | 5 0.08% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 6400 -system.ruby.IFETCH.hit_latency_hist::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist::samples 5819 -system.ruby.IFETCH.hit_latency_hist::mean 1.111703 -system.ruby.IFETCH.hit_latency_hist::gmean 1.027147 -system.ruby.IFETCH.hit_latency_hist::stdev 1.051067 -system.ruby.IFETCH.hit_latency_hist | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5819 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 581 -system.ruby.IFETCH.miss_latency_hist::mean 64.087780 -system.ruby.IFETCH.miss_latency_hist::gmean 61.562973 -system.ruby.IFETCH.miss_latency_hist::stdev 29.566480 -system.ruby.IFETCH.miss_latency_hist | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 581 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 7086 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 7086 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 2 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 19 -system.ruby.L2Cache.hit_mach_latency_hist::samples 203 -system.ruby.L2Cache.hit_mach_latency_hist::mean 11 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 11.000000 -system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 203 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1159 -system.ruby.Directory.miss_mach_latency_hist::mean 59.452977 -system.ruby.Directory.miss_mach_latency_hist::gmean 56.282360 -system.ruby.Directory.miss_mach_latency_hist::stdev 25.811948 -system.ruby.Directory.miss_mach_latency_hist | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1159 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 75 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 9 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 658 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 658 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 19 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20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 674 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 674 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 33 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.240506 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.407659 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.670342 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 5754 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 5754 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 65 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98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 1183 +system.ruby.LD.latency_hist_seqr::mean 21.460693 +system.ruby.LD.latency_hist_seqr::gmean 5.052192 +system.ruby.LD.latency_hist_seqr::stdev 28.940454 +system.ruby.LD.latency_hist_seqr | 852 72.02% 72.02% | 242 20.46% 92.48% | 85 7.19% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 +system.ruby.LD.hit_latency_hist_seqr::samples 763 +system.ruby.LD.hit_latency_hist_seqr::mean 2.376147 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.390948 +system.ruby.LD.hit_latency_hist_seqr::stdev 3.447211 +system.ruby.LD.hit_latency_hist_seqr | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 763 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 420 +system.ruby.LD.miss_latency_hist_seqr::mean 56.130952 +system.ruby.LD.miss_latency_hist_seqr::gmean 52.616261 +system.ruby.LD.miss_latency_hist_seqr::stdev 21.748058 +system.ruby.LD.miss_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 420 +system.ruby.ST.latency_hist_seqr::bucket_size 16 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 707 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 +system.ruby.ST.miss_latency_hist_seqr::samples 158 +system.ruby.ST.miss_latency_hist_seqr::mean 51.240506 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.407659 +system.ruby.ST.miss_latency_hist_seqr::stdev 15.670342 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 158 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6400 +system.ruby.IFETCH.latency_hist_seqr::mean 6.828750 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.489407 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nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 420 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.130952 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.616261 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 21.748058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 420 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 674 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 33 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 158 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.240506 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.407659 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 15.670342 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.087780 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.562973 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.566480 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581 system.ruby.Directory_Controller.GETX 185 0.00% 0.00% system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 07f3f8674..7cbd97c4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -346,6 +347,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -407,12 +409,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1011,6 +1015,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 283f54eb9..925eb0bfe 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:38 -gem5 executing on zizzer, pid 26203 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33967 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 10198f0c6..ee921f3ab 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107210 # Number of ticks simulated final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30588 # Simulator instruction rate (inst/s) -host_op_rate 30584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 513061 # Simulator tick rate (ticks/s) -host_mem_usage 388380 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 29228 # Simulator instruction rate (inst/s) +host_op_rate 29224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 490268 # Simulator tick rate (ticks/s) +host_mem_usage 394320 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -365,37 +365,37 @@ system.ruby.delayHist::max_bucket 9 # de system.ruby.delayHist::samples 3456 # delay histogram for all message system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 3456 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 11.690578 -system.ruby.latency_hist::gmean 2.205273 -system.ruby.latency_hist::stdev 25.830363 -system.ruby.latency_hist | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6718 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6718 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 53.204624 -system.ruby.miss_latency_hist::gmean 47.556283 -system.ruby.miss_latency_hist::stdev 33.032605 -system.ruby.miss_latency_hist | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1730 -system.ruby.Directory.incomplete_times 1729 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8448 +system.ruby.latency_hist_seqr::mean 11.690578 +system.ruby.latency_hist_seqr::gmean 2.205273 +system.ruby.latency_hist_seqr::stdev 25.830363 +system.ruby.latency_hist_seqr | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8448 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 6718 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6718 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1730 +system.ruby.miss_latency_hist_seqr::mean 53.204624 +system.ruby.miss_latency_hist_seqr::gmean 47.556283 +system.ruby.miss_latency_hist_seqr::stdev 33.032605 +system.ruby.miss_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1730 +system.ruby.Directory.incomplete_times_seqr 1729 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses @@ -475,133 +475,133 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 -system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 31.638208 -system.ruby.LD.latency_hist::gmean 10.419015 -system.ruby.LD.latency_hist::stdev 35.065266 -system.ruby.LD.latency_hist | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1183 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 456 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 456 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 -system.ruby.LD.miss_latency_hist::samples 727 -system.ruby.LD.miss_latency_hist::mean 50.855571 -system.ruby.LD.miss_latency_hist::gmean 45.315147 -system.ruby.LD.miss_latency_hist::stdev 32.287061 -system.ruby.LD.miss_latency_hist | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 727 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 16.483237 -system.ruby.ST.latency_hist::gmean 3.324735 -system.ruby.ST.latency_hist::stdev 28.016571 -system.ruby.ST.latency_hist | 592 68.44% 68.44% | 244 28.21% 96.65% | 18 2.08% 98.73% | 2 0.23% 98.96% | 5 0.58% 99.54% | 2 0.23% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 865 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 592 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 592 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 273 -system.ruby.ST.miss_latency_hist::mean 50.058608 -system.ruby.ST.miss_latency_hist::gmean 44.997273 -system.ruby.ST.miss_latency_hist::stdev 28.984216 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 273 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 7.355625 -system.ruby.IFETCH.latency_hist::gmean 1.565715 -system.ruby.IFETCH.latency_hist::stdev 21.264557 -system.ruby.IFETCH.latency_hist | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 6400 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 5670 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5670 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 730 -system.ruby.IFETCH.miss_latency_hist::mean 56.720548 -system.ruby.IFETCH.miss_latency_hist::gmean 50.941265 -system.ruby.IFETCH.miss_latency_hist::stdev 34.853032 -system.ruby.IFETCH.miss_latency_hist | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 730 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1730 -system.ruby.Directory.miss_mach_latency_hist::mean 53.204624 -system.ruby.Directory.miss_mach_latency_hist::gmean 47.556283 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.032605 -system.ruby.Directory.miss_mach_latency_hist | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1730 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.855571 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.315147 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.287061 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 50.058608 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.997273 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 28.984216 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.720548 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.941265 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.853032 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1183 +system.ruby.LD.latency_hist_seqr::mean 31.638208 +system.ruby.LD.latency_hist_seqr::gmean 10.419015 +system.ruby.LD.latency_hist_seqr::stdev 35.065266 +system.ruby.LD.latency_hist_seqr | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 592 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 273 +system.ruby.ST.miss_latency_hist_seqr::mean 50.058608 +system.ruby.ST.miss_latency_hist_seqr::gmean 44.997273 +system.ruby.ST.miss_latency_hist_seqr::stdev 28.984216 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 273 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6400 +system.ruby.IFETCH.latency_hist_seqr::mean 7.355625 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.565715 +system.ruby.IFETCH.latency_hist_seqr::stdev 21.264557 +system.ruby.IFETCH.latency_hist_seqr | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5670 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5670 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 730 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.720548 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.941265 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.853032 +system.ruby.IFETCH.miss_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 730 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1730 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.204624 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.556283 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.032605 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1730 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 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| 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 727 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.855571 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.315147 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.287061 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 727 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 50.058608 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.997273 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 28.984216 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.720548 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.941265 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.853032 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730 system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 3a556ff94..1342c10c6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 163c95e23..006646a27 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:42 -gem5 executing on zizzer, pid 26242 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:02 +gem5 executing on zizzer, pid 34003 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 8821d85ce..f47665bf0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 35667500 # Number of ticks simulated final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3576 # Simulator instruction rate (inst/s) -host_op_rate 3576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19962115 # Simulator tick rate (ticks/s) -host_mem_usage 230248 # Number of bytes of host memory used -host_seconds 1.79 # Real time elapsed on the host +host_inst_rate 102057 # Simulator instruction rate (inst/s) +host_op_rate 102013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 569174066 # Simulator tick rate (ticks/s) +host_mem_usage 230332 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index e137cc931..8e21534df 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout index f568b3f74..9179fdffe 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:29 -gem5 executing on zizzer, pid 26176 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:13 +gem5 executing on zizzer, pid 34033 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 876577feb..eadf1b794 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20075000 # Number of ticks simulated final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11823 # Simulator instruction rate (inst/s) -host_op_rate 11822 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91797329 # Simulator tick rate (ticks/s) -host_mem_usage 230008 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 31344 # Simulator instruction rate (inst/s) +host_op_rate 31334 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 243267003 # Simulator tick rate (ticks/s) +host_mem_usage 230348 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 229d282ae..7d0044f86 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index fdb59079e..0abe9b40e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:41 -gem5 executing on zizzer, pid 26235 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:12 +gem5 executing on zizzer, pid 34021 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 4bce4940b..c35fecd4e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19595 # Simulator instruction rate (inst/s) -host_op_rate 19590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101447809 # Simulator tick rate (ticks/s) -host_mem_usage 231216 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 12168 # Simulator instruction rate (inst/s) +host_op_rate 12166 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63007670 # Simulator tick rate (ticks/s) +host_mem_usage 231556 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 5fbeeb6fe..2db41bef8 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index daedf47ad..ec449ee9d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26173 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:01 +gem5 executing on zizzer, pid 33991 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 46e47f579..ff4b92b39 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48732 # Simulator instruction rate (inst/s) -host_op_rate 48711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24515166 # Simulator tick rate (ticks/s) -host_mem_usage 219316 # Number of bytes of host memory used +host_inst_rate 54662 # Simulator instruction rate (inst/s) +host_op_rate 54627 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27487977 # Simulator tick rate (ticks/s) +host_mem_usage 219680 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 99232562d..8e85722f1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -335,6 +336,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -358,6 +360,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -438,12 +441,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -515,6 +520,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1188,6 +1194,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout index 5ec510897..321d1816d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:05:44 -gem5 started Dec 11 2015 20:06:17 -gem5 executing on zizzer, pid 37027 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level +gem5 compiled Jan 21 2016 14:01:33 +gem5 started Jan 21 2016 14:02:10 +gem5 executing on zizzer, pid 44711 +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index f2413d83a..55628ad16 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu sim_ticks 45733 # Number of ticks simulated final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19080 # Simulator instruction rate (inst/s) -host_op_rate 19075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 338419 # Simulator tick rate (ticks/s) -host_mem_usage 387604 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 16358 # Simulator instruction rate (inst/s) +host_op_rate 16355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 290200 # Simulator tick rate (ticks/s) +host_mem_usage 389816 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -360,36 +360,36 @@ system.ruby.delayHist::mean 0.144518 # de system.ruby.delayHist::stdev 0.930805 # delay histogram for all message system.ruby.delayHist | 3486 96.51% 96.51% | 0 0.00% 96.51% | 81 2.24% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 45 1.25% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 3612 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 12.883728 -system.ruby.latency_hist::gmean 2.062291 -system.ruby.latency_hist::stdev 28.863704 -system.ruby.latency_hist | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2722 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2722 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 572 -system.ruby.miss_latency_hist::mean 69.435315 -system.ruby.miss_latency_hist::gmean 64.604000 -system.ruby.miss_latency_hist::stdev 30.458568 -system.ruby.miss_latency_hist | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 572 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 3295 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 3295 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 3294 +system.ruby.latency_hist_seqr::mean 12.883728 +system.ruby.latency_hist_seqr::gmean 2.062291 +system.ruby.latency_hist_seqr::stdev 28.863704 +system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 3294 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 2722 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2722 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 572 +system.ruby.miss_latency_hist_seqr::mean 69.435315 +system.ruby.miss_latency_hist_seqr::gmean 64.604000 +system.ruby.miss_latency_hist_seqr::stdev 30.458568 +system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 572 system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -583,75 +583,75 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 31.356627 -system.ruby.LD.latency_hist::gmean 7.342788 -system.ruby.LD.latency_hist::stdev 35.995277 -system.ruby.LD.latency_hist | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% -system.ruby.LD.latency_hist::total 415 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 211 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 211 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 204 -system.ruby.LD.miss_latency_hist::mean 62.754902 -system.ruby.LD.miss_latency_hist::gmean 57.734169 -system.ruby.LD.miss_latency_hist::stdev 26.340677 -system.ruby.LD.miss_latency_hist | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% -system.ruby.LD.miss_latency_hist::total 204 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 14.789116 -system.ruby.ST.latency_hist::gmean 2.517478 -system.ruby.ST.latency_hist::stdev 31.573573 -system.ruby.ST.latency_hist | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 294 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 226 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 226 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 -system.ruby.ST.miss_latency_hist::samples 68 -system.ruby.ST.miss_latency_hist::mean 60.617647 -system.ruby.ST.miss_latency_hist::gmean 54.148546 -system.ruby.ST.miss_latency_hist::stdev 39.831747 -system.ruby.ST.miss_latency_hist | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 68 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 9.701354 -system.ruby.IFETCH.latency_hist::gmean 1.644214 -system.ruby.IFETCH.latency_hist::stdev 25.994801 -system.ruby.IFETCH.latency_hist | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 2585 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2285 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2285 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 300 -system.ruby.IFETCH.miss_latency_hist::mean 75.976667 -system.ruby.IFETCH.miss_latency_hist::gmean 72.583942 -system.ruby.IFETCH.miss_latency_hist::stdev 29.223784 -system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 300 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 415 +system.ruby.LD.latency_hist_seqr::mean 31.356627 +system.ruby.LD.latency_hist_seqr::gmean 7.342788 +system.ruby.LD.latency_hist_seqr::stdev 35.995277 +system.ruby.LD.latency_hist_seqr | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% +system.ruby.LD.latency_hist_seqr::total 415 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 211 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 211 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 204 +system.ruby.LD.miss_latency_hist_seqr::mean 62.754902 +system.ruby.LD.miss_latency_hist_seqr::gmean 57.734169 +system.ruby.LD.miss_latency_hist_seqr::stdev 26.340677 +system.ruby.LD.miss_latency_hist_seqr | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 204 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 294 +system.ruby.ST.latency_hist_seqr::mean 14.789116 +system.ruby.ST.latency_hist_seqr::gmean 2.517478 +system.ruby.ST.latency_hist_seqr::stdev 31.573573 +system.ruby.ST.latency_hist_seqr | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 294 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 226 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 226 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 68 +system.ruby.ST.miss_latency_hist_seqr::mean 60.617647 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.148546 +system.ruby.ST.miss_latency_hist_seqr::stdev 39.831747 +system.ruby.ST.miss_latency_hist_seqr | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 68 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 2585 +system.ruby.IFETCH.latency_hist_seqr::mean 9.701354 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.644214 +system.ruby.IFETCH.latency_hist_seqr::stdev 25.994801 +system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 2585 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2285 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2285 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 300 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 75.976667 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 72.583942 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.223784 +system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 300 system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% system.ruby.Directory_Controller.Data 103 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 05722ae95..95074a37b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -340,6 +341,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -363,6 +365,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -424,12 +427,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -508,6 +513,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1180,6 +1186,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index d4b5e9cd4..28c1f1cb8 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:10:49 -gem5 started Dec 11 2015 20:11:27 -gem5 executing on zizzer, pid 42488 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Jan 21 2016 14:06:59 +gem5 started Jan 21 2016 14:07:35 +gem5 executing on zizzer, pid 50069 +command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 03c140254..4855f53c1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41712 # Number of ticks simulated final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16080 # Simulator instruction rate (inst/s) -host_op_rate 16077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 260182 # Simulator tick rate (ticks/s) -host_mem_usage 389928 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 12099 # Simulator instruction rate (inst/s) +host_op_rate 12098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195791 # Simulator tick rate (ticks/s) +host_mem_usage 393888 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -353,36 +353,36 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 32 -system.ruby.latency_hist::max_bucket 319 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 11.663024 -system.ruby.latency_hist::gmean 1.954156 -system.ruby.latency_hist::stdev 27.142816 -system.ruby.latency_hist | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2750 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2750 -system.ruby.miss_latency_hist::bucket_size 32 -system.ruby.miss_latency_hist::max_bucket 319 -system.ruby.miss_latency_hist::samples 544 -system.ruby.miss_latency_hist::mean 65.566176 -system.ruby.miss_latency_hist::gmean 57.783054 -system.ruby.miss_latency_hist::stdev 31.323348 -system.ruby.miss_latency_hist | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00% -system.ruby.miss_latency_hist::total 544 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 3295 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 3295 +system.ruby.latency_hist_seqr::bucket_size 32 +system.ruby.latency_hist_seqr::max_bucket 319 +system.ruby.latency_hist_seqr::samples 3294 +system.ruby.latency_hist_seqr::mean 11.663024 +system.ruby.latency_hist_seqr::gmean 1.954156 +system.ruby.latency_hist_seqr::stdev 27.142816 +system.ruby.latency_hist_seqr | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% +system.ruby.latency_hist_seqr::total 3294 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 2750 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2750 +system.ruby.miss_latency_hist_seqr::bucket_size 32 +system.ruby.miss_latency_hist_seqr::max_bucket 319 +system.ruby.miss_latency_hist_seqr::samples 544 +system.ruby.miss_latency_hist_seqr::mean 65.566176 +system.ruby.miss_latency_hist_seqr::gmean 57.783054 +system.ruby.miss_latency_hist_seqr::stdev 31.323348 +system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00% +system.ruby.miss_latency_hist_seqr::total 544 system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -550,75 +550,75 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 25.657831 -system.ruby.LD.latency_hist::gmean 5.487426 -system.ruby.LD.latency_hist::stdev 34.035908 -system.ruby.LD.latency_hist | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 415 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 233 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 233 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 182 -system.ruby.LD.miss_latency_hist::mean 57.225275 -system.ruby.LD.miss_latency_hist::gmean 48.520263 -system.ruby.LD.miss_latency_hist::stdev 29.410954 -system.ruby.LD.miss_latency_hist | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 182 -system.ruby.ST.latency_hist::bucket_size 16 -system.ruby.ST.latency_hist::max_bucket 159 -system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 18.809524 -system.ruby.ST.latency_hist::gmean 3.456048 -system.ruby.ST.latency_hist::stdev 29.072895 -system.ruby.ST.latency_hist | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 294 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 202 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 202 -system.ruby.ST.miss_latency_hist::bucket_size 16 -system.ruby.ST.miss_latency_hist::max_bucket 159 -system.ruby.ST.miss_latency_hist::samples 92 -system.ruby.ST.miss_latency_hist::mean 57.913043 -system.ruby.ST.miss_latency_hist::gmean 52.615480 -system.ruby.ST.miss_latency_hist::stdev 21.714254 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 92 -system.ruby.IFETCH.latency_hist::bucket_size 32 -system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 8.603482 -system.ruby.IFETCH.latency_hist::gmean 1.551701 -system.ruby.IFETCH.latency_hist::stdev 24.714457 -system.ruby.IFETCH.latency_hist | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% -system.ruby.IFETCH.latency_hist::total 2585 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2315 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2315 -system.ruby.IFETCH.miss_latency_hist::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 270 -system.ruby.IFETCH.miss_latency_hist::mean 73.796296 -system.ruby.IFETCH.miss_latency_hist::gmean 67.113694 -system.ruby.IFETCH.miss_latency_hist::stdev 33.225253 -system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 270 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 415 +system.ruby.LD.latency_hist_seqr::mean 25.657831 +system.ruby.LD.latency_hist_seqr::gmean 5.487426 +system.ruby.LD.latency_hist_seqr::stdev 34.035908 +system.ruby.LD.latency_hist_seqr | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 415 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 233 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 233 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 182 +system.ruby.LD.miss_latency_hist_seqr::mean 57.225275 +system.ruby.LD.miss_latency_hist_seqr::gmean 48.520263 +system.ruby.LD.miss_latency_hist_seqr::stdev 29.410954 +system.ruby.LD.miss_latency_hist_seqr | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 182 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 +system.ruby.ST.latency_hist_seqr::samples 294 +system.ruby.ST.latency_hist_seqr::mean 18.809524 +system.ruby.ST.latency_hist_seqr::gmean 3.456048 +system.ruby.ST.latency_hist_seqr::stdev 29.072895 +system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 294 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 202 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 202 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 +system.ruby.ST.miss_latency_hist_seqr::samples 92 +system.ruby.ST.miss_latency_hist_seqr::mean 57.913043 +system.ruby.ST.miss_latency_hist_seqr::gmean 52.615480 +system.ruby.ST.miss_latency_hist_seqr::stdev 21.714254 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 92 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 2585 +system.ruby.IFETCH.latency_hist_seqr::mean 8.603482 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.551701 +system.ruby.IFETCH.latency_hist_seqr::stdev 24.714457 +system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 2585 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2315 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2315 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 270 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.796296 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.113694 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.225253 +system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 270 system.ruby.Directory_Controller.GETX 80 0.00% 0.00% system.ruby.Directory_Controller.GETS 384 0.00% 0.00% system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index ed2a8fa86..7ee7deae6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -388,6 +389,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -411,6 +413,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -488,12 +491,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -567,6 +572,7 @@ slave=system.ruby.network.master[4] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1744,6 +1750,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index da0b54ada..9a1a80ba2 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:15:50 -gem5 started Dec 11 2015 20:16:20 -gem5 executing on zizzer, pid 47645 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Jan 21 2016 14:12:23 +gem5 started Jan 21 2016 14:13:00 +gem5 executing on zizzer, pid 55410 +command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 7c3e6af7f..6e16bb481 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 40527 # Number of ticks simulated final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13852 # Simulator instruction rate (inst/s) -host_op_rate 13850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 217785 # Simulator tick rate (ticks/s) -host_mem_usage 388588 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 25710 # Simulator instruction rate (inst/s) +host_op_rate 25704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 404148 # Simulator tick rate (ticks/s) +host_mem_usage 390780 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -353,38 +353,38 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 11.303279 -system.ruby.latency_hist::gmean 1.905847 -system.ruby.latency_hist::stdev 27.108694 -system.ruby.latency_hist | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 4 -system.ruby.hit_latency_hist::max_bucket 39 -system.ruby.hit_latency_hist::samples 2846 -system.ruby.hit_latency_hist::mean 1.554814 -system.ruby.hit_latency_hist::gmean 1.080771 -system.ruby.hit_latency_hist::stdev 3.499483 -system.ruby.hit_latency_hist | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2846 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 448 -system.ruby.miss_latency_hist::mean 73.232143 -system.ruby.miss_latency_hist::gmean 69.999992 -system.ruby.miss_latency_hist::stdev 29.782878 -system.ruby.miss_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 448 -system.ruby.Directory.incomplete_times 447 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 3295 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 3295 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 3294 +system.ruby.latency_hist_seqr::mean 11.303279 +system.ruby.latency_hist_seqr::gmean 1.905847 +system.ruby.latency_hist_seqr::stdev 27.108694 +system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 3294 +system.ruby.hit_latency_hist_seqr::bucket_size 4 +system.ruby.hit_latency_hist_seqr::max_bucket 39 +system.ruby.hit_latency_hist_seqr::samples 2846 +system.ruby.hit_latency_hist_seqr::mean 1.554814 +system.ruby.hit_latency_hist_seqr::gmean 1.080771 +system.ruby.hit_latency_hist_seqr::stdev 3.499483 +system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2846 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 448 +system.ruby.miss_latency_hist_seqr::mean 73.232143 +system.ruby.miss_latency_hist_seqr::gmean 69.999992 +system.ruby.miss_latency_hist_seqr::stdev 29.782878 +system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 448 +system.ruby.Directory.incomplete_times_seqr 447 system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -534,195 +534,195 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 27.009639 -system.ruby.LD.latency_hist::gmean 5.745092 -system.ruby.LD.latency_hist::stdev 35.695436 -system.ruby.LD.latency_hist | 266 64.10% 64.10% | 50 12.05% 76.14% | 86 20.72% 96.87% | 10 2.41% 99.28% | 2 0.48% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% -system.ruby.LD.latency_hist::total 415 -system.ruby.LD.hit_latency_hist::bucket_size 4 -system.ruby.LD.hit_latency_hist::max_bucket 39 -system.ruby.LD.hit_latency_hist::samples 266 -system.ruby.LD.hit_latency_hist::mean 3.834586 -system.ruby.LD.hit_latency_hist::gmean 1.482071 -system.ruby.LD.hit_latency_hist::stdev 7.549265 -system.ruby.LD.hit_latency_hist | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 266 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 149 -system.ruby.LD.miss_latency_hist::mean 68.382550 -system.ruby.LD.miss_latency_hist::gmean 64.532565 -system.ruby.LD.miss_latency_hist::stdev 27.813471 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% -system.ruby.LD.miss_latency_hist::total 149 -system.ruby.ST.latency_hist::bucket_size 16 -system.ruby.ST.latency_hist::max_bucket 159 -system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 12.595238 -system.ruby.ST.latency_hist::gmean 2.381363 -system.ruby.ST.latency_hist::stdev 23.818056 -system.ruby.ST.latency_hist | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 294 -system.ruby.ST.hit_latency_hist::bucket_size 4 -system.ruby.ST.hit_latency_hist::max_bucket 39 -system.ruby.ST.hit_latency_hist::samples 242 -system.ruby.ST.hit_latency_hist::mean 2.223140 -system.ruby.ST.hit_latency_hist::gmean 1.195990 -system.ruby.ST.hit_latency_hist::stdev 4.967926 -system.ruby.ST.hit_latency_hist | 228 94.21% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 7 2.89% 97.11% | 7 2.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 242 -system.ruby.ST.miss_latency_hist::bucket_size 16 -system.ruby.ST.miss_latency_hist::max_bucket 159 -system.ruby.ST.miss_latency_hist::samples 52 -system.ruby.ST.miss_latency_hist::mean 60.865385 -system.ruby.ST.miss_latency_hist::gmean 58.719474 -system.ruby.ST.miss_latency_hist::stdev 16.012286 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 52 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 8.634816 -system.ruby.IFETCH.latency_hist::gmean 1.556513 -system.ruby.IFETCH.latency_hist::stdev 24.922226 -system.ruby.IFETCH.latency_hist | 2338 90.44% 90.44% | 243 9.40% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 2585 -system.ruby.IFETCH.hit_latency_hist::bucket_size 4 -system.ruby.IFETCH.hit_latency_hist::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist::samples 2338 -system.ruby.IFETCH.hit_latency_hist::mean 1.226262 -system.ruby.IFETCH.hit_latency_hist::gmean 1.031758 -system.ruby.IFETCH.hit_latency_hist::stdev 2.270469 -system.ruby.IFETCH.hit_latency_hist | 2315 99.02% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2338 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 247 -system.ruby.IFETCH.miss_latency_hist::mean 78.761134 -system.ruby.IFETCH.miss_latency_hist::gmean 76.290474 -system.ruby.IFETCH.miss_latency_hist::stdev 31.873920 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 247 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 2776 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 2776 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 2776 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 4 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 39 -system.ruby.L2Cache.hit_mach_latency_hist::samples 70 -system.ruby.L2Cache.hit_mach_latency_hist::mean 23.557143 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 23.524270 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.199465 -system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 70 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 448 -system.ruby.Directory.miss_mach_latency_hist::mean 73.232143 -system.ruby.Directory.miss_mach_latency_hist::gmean 69.999992 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.782878 -system.ruby.Directory.miss_mach_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 448 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 82 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 82.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 4 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0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 149 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 +system.ruby.ST.latency_hist_seqr::samples 294 +system.ruby.ST.latency_hist_seqr::mean 12.595238 +system.ruby.ST.latency_hist_seqr::gmean 2.381363 +system.ruby.ST.latency_hist_seqr::stdev 23.818056 +system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 294 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 +system.ruby.ST.hit_latency_hist_seqr::samples 242 +system.ruby.ST.hit_latency_hist_seqr::mean 2.223140 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0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2338 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 247 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.761134 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.290474 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.873920 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 247 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 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87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 73.232143 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 69.999992 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 29.782878 +system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 448 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 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| 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.848485 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.840140 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.618527 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 68.382550 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 64.532565 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.813471 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 228 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 228 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 228 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 14 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.142857 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.058564 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.994498 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 60.865385 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 58.719474 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 16.012286 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 23 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 23 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.761134 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.290474 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.873920 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247 system.ruby.Directory_Controller.GETX 61 0.00% 0.00% system.ruby.Directory_Controller.GETS 398 0.00% 0.00% system.ruby.Directory_Controller.Lockdown 4 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 5cac5181c..8190e6bb4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -305,6 +306,7 @@ master=system.ruby.network.slave[3] type=RubyCache children=replacement_policy assoc=4 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -404,6 +406,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -427,6 +430,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -450,6 +454,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -511,12 +516,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1228,6 +1235,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 5fb683d5f..2cf0cc885 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:00:36 -gem5 started Dec 11 2015 20:01:07 -gem5 executing on zizzer, pid 31723 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +gem5 compiled Jan 21 2016 13:56:08 +gem5 started Jan 21 2016 13:56:42 +gem5 executing on zizzer, pid 39363 +command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index b02df8112..a8631d9c5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32936 # Number of ticks simulated final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23563 # Simulator instruction rate (inst/s) -host_op_rate 23558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301005 # Simulator tick rate (ticks/s) -host_mem_usage 388376 # Number of bytes of host memory used +host_inst_rate 22566 # Simulator instruction rate (inst/s) +host_op_rate 22561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 288279 # Simulator tick rate (ticks/s) +host_mem_usage 390660 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -353,38 +353,38 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 8.998786 -system.ruby.latency_hist::gmean 1.800750 -system.ruby.latency_hist::stdev 22.386902 -system.ruby.latency_hist | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 2853 -system.ruby.hit_latency_hist::mean 1.241851 -system.ruby.hit_latency_hist::gmean 1.059708 -system.ruby.hit_latency_hist::stdev 1.536503 -system.ruby.hit_latency_hist | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2853 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 441 -system.ruby.miss_latency_hist::mean 59.181406 -system.ruby.miss_latency_hist::gmean 55.608631 -system.ruby.miss_latency_hist::stdev 28.659343 -system.ruby.miss_latency_hist | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 441 -system.ruby.Directory.incomplete_times 440 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 3295 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 3295 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 3294 +system.ruby.latency_hist_seqr::mean 8.998786 +system.ruby.latency_hist_seqr::gmean 1.800750 +system.ruby.latency_hist_seqr::stdev 22.386902 +system.ruby.latency_hist_seqr | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 3294 +system.ruby.hit_latency_hist_seqr::bucket_size 2 +system.ruby.hit_latency_hist_seqr::max_bucket 19 +system.ruby.hit_latency_hist_seqr::samples 2853 +system.ruby.hit_latency_hist_seqr::mean 1.241851 +system.ruby.hit_latency_hist_seqr::gmean 1.059708 +system.ruby.hit_latency_hist_seqr::stdev 1.536503 +system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2853 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 441 +system.ruby.miss_latency_hist_seqr::mean 59.181406 +system.ruby.miss_latency_hist_seqr::gmean 55.608631 +system.ruby.miss_latency_hist_seqr::stdev 28.659343 +system.ruby.miss_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 441 +system.ruby.Directory.incomplete_times_seqr 440 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -502,192 +502,192 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 5832 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.LD.latency_hist::bucket_size 16 -system.ruby.LD.latency_hist::max_bucket 159 -system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 19.850602 -system.ruby.LD.latency_hist::gmean 4.833066 -system.ruby.LD.latency_hist::stdev 26.151303 -system.ruby.LD.latency_hist | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 415 -system.ruby.LD.hit_latency_hist::bucket_size 2 -system.ruby.LD.hit_latency_hist::max_bucket 19 -system.ruby.LD.hit_latency_hist::samples 269 -system.ruby.LD.hit_latency_hist::mean 2.338290 -system.ruby.LD.hit_latency_hist::gmean 1.378379 -system.ruby.LD.hit_latency_hist::stdev 3.411031 -system.ruby.LD.hit_latency_hist | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 269 -system.ruby.LD.miss_latency_hist::bucket_size 16 -system.ruby.LD.miss_latency_hist::max_bucket 159 -system.ruby.LD.miss_latency_hist::samples 146 -system.ruby.LD.miss_latency_hist::mean 52.116438 -system.ruby.LD.miss_latency_hist::gmean 48.763829 -system.ruby.LD.miss_latency_hist::stdev 17.717519 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 146 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 10.064626 -system.ruby.ST.latency_hist::gmean 2.035894 -system.ruby.ST.latency_hist::stdev 25.936505 -system.ruby.ST.latency_hist | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% -system.ruby.ST.latency_hist::total 294 -system.ruby.ST.hit_latency_hist::bucket_size 2 -system.ruby.ST.hit_latency_hist::max_bucket 19 -system.ruby.ST.hit_latency_hist::samples 247 -system.ruby.ST.hit_latency_hist::mean 1.445344 -system.ruby.ST.hit_latency_hist::gmean 1.112699 -system.ruby.ST.hit_latency_hist::stdev 2.066980 -system.ruby.ST.hit_latency_hist | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 247 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 47 -system.ruby.ST.miss_latency_hist::mean 55.361702 -system.ruby.ST.miss_latency_hist::gmean 48.711518 -system.ruby.ST.miss_latency_hist::stdev 42.031265 -system.ruby.ST.miss_latency_hist | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% -system.ruby.ST.miss_latency_hist::total 47 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 7.135397 -system.ruby.IFETCH.latency_hist::gmean 1.515500 -system.ruby.IFETCH.latency_hist::stdev 20.744191 -system.ruby.IFETCH.latency_hist | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 2585 -system.ruby.IFETCH.hit_latency_hist::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist::samples 2337 -system.ruby.IFETCH.hit_latency_hist::mean 1.094138 -system.ruby.IFETCH.hit_latency_hist::gmean 1.022830 -system.ruby.IFETCH.hit_latency_hist::stdev 0.965875 -system.ruby.IFETCH.hit_latency_hist | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2337 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 248 -system.ruby.IFETCH.miss_latency_hist::mean 64.064516 -system.ruby.IFETCH.miss_latency_hist::gmean 61.606137 -system.ruby.IFETCH.miss_latency_hist::stdev 29.893804 -system.ruby.IFETCH.miss_latency_hist | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 248 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 2784 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 2784 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 2 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 19 -system.ruby.L2Cache.hit_mach_latency_hist::samples 69 -system.ruby.L2Cache.hit_mach_latency_hist::mean 11 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 11.000000 -system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 69 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 441 -system.ruby.Directory.miss_mach_latency_hist::mean 59.181406 -system.ruby.Directory.miss_mach_latency_hist::gmean 55.608631 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.659343 -system.ruby.Directory.miss_mach_latency_hist | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 441 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 75 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 9 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 36 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 11 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 36 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 146 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.116438 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 48.763829 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 17.717519 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 146 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 236 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 236 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 11 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 47 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.361702 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.711518 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 42.031265 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 47 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 2315 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 2315 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 22 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 22 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 248 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 64.064516 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.606137 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 29.893804 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248 +system.ruby.LD.latency_hist_seqr::bucket_size 16 +system.ruby.LD.latency_hist_seqr::max_bucket 159 +system.ruby.LD.latency_hist_seqr::samples 415 +system.ruby.LD.latency_hist_seqr::mean 19.850602 +system.ruby.LD.latency_hist_seqr::gmean 4.833066 +system.ruby.LD.latency_hist_seqr::stdev 26.151303 +system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 415 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 +system.ruby.LD.hit_latency_hist_seqr::samples 269 +system.ruby.LD.hit_latency_hist_seqr::mean 2.338290 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.378379 +system.ruby.LD.hit_latency_hist_seqr::stdev 3.411031 +system.ruby.LD.hit_latency_hist_seqr | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 269 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 +system.ruby.LD.miss_latency_hist_seqr::samples 146 +system.ruby.LD.miss_latency_hist_seqr::mean 52.116438 +system.ruby.LD.miss_latency_hist_seqr::gmean 48.763829 +system.ruby.LD.miss_latency_hist_seqr::stdev 17.717519 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 146 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 294 +system.ruby.ST.latency_hist_seqr::mean 10.064626 +system.ruby.ST.latency_hist_seqr::gmean 2.035894 +system.ruby.ST.latency_hist_seqr::stdev 25.936505 +system.ruby.ST.latency_hist_seqr | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.ST.latency_hist_seqr::total 294 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 +system.ruby.ST.hit_latency_hist_seqr::samples 247 +system.ruby.ST.hit_latency_hist_seqr::mean 1.445344 +system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699 +system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980 +system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 247 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 47 +system.ruby.ST.miss_latency_hist_seqr::mean 55.361702 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.711518 +system.ruby.ST.miss_latency_hist_seqr::stdev 42.031265 +system.ruby.ST.miss_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 47 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 2585 +system.ruby.IFETCH.latency_hist_seqr::mean 7.135397 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.515500 +system.ruby.IFETCH.latency_hist_seqr::stdev 20.744191 +system.ruby.IFETCH.latency_hist_seqr | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 2585 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2337 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.094138 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875 +system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2337 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 248 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.064516 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.606137 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.893804 +system.ruby.IFETCH.miss_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 248 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 2784 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2784 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 69 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.181406 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.608631 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.659343 +system.ruby.Directory.miss_mach_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 441 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 36 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.116438 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 48.763829 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 17.717519 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 236 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 236 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 11 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.361702 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.711518 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 42.031265 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 22 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.064516 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.606137 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.893804 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248 system.ruby.Directory_Controller.GETX 51 0.00% 0.00% system.ruby.Directory_Controller.GETS 410 0.00% 0.00% system.ruby.Directory_Controller.PUT 425 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 01fcb0aae..4edb3028e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -346,6 +347,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -407,12 +409,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1011,6 +1015,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index b20851927..98025cd1e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:40 -gem5 executing on zizzer, pid 26219 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:26 +gem5 executing on zizzer, pid 34072 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 0efa35016..7f8b12151 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17997 # Simulator instruction rate (inst/s) -host_op_rate 17994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290838 # Simulator tick rate (ticks/s) -host_mem_usage 386736 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 23573 # Simulator instruction rate (inst/s) +host_op_rate 23567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380874 # Simulator tick rate (ticks/s) +host_mem_usage 390976 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -364,37 +364,37 @@ system.ruby.delayHist::max_bucket 9 # de system.ruby.delayHist::samples 1248 # delay histogram for all message system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 11.646934 -system.ruby.latency_hist::gmean 2.114776 -system.ruby.latency_hist::stdev 26.263922 -system.ruby.latency_hist | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2668 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2668 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 57.023962 -system.ruby.miss_latency_hist::gmean 51.467697 -system.ruby.miss_latency_hist::stdev 32.986607 -system.ruby.miss_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626 -system.ruby.Directory.incomplete_times 625 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 3295 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 3295 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 3294 +system.ruby.latency_hist_seqr::mean 11.646934 +system.ruby.latency_hist_seqr::gmean 2.114776 +system.ruby.latency_hist_seqr::stdev 26.263922 +system.ruby.latency_hist_seqr | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 3294 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 2668 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2668 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 626 +system.ruby.miss_latency_hist_seqr::mean 57.023962 +system.ruby.miss_latency_hist_seqr::gmean 51.467697 +system.ruby.miss_latency_hist_seqr::stdev 32.986607 +system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 626 +system.ruby.Directory.incomplete_times_seqr 625 system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses @@ -474,133 +474,133 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 30.537349 -system.ruby.LD.latency_hist::gmean 9.686440 -system.ruby.LD.latency_hist::stdev 30.265140 -system.ruby.LD.latency_hist | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 415 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 170 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 170 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 245 -system.ruby.LD.miss_latency_hist::mean 51.032653 -system.ruby.LD.miss_latency_hist::gmean 46.821080 -system.ruby.LD.miss_latency_hist::stdev 22.902478 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 245 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 16.663265 -system.ruby.ST.latency_hist::gmean 3.036238 -system.ruby.ST.latency_hist::stdev 32.952425 -system.ruby.ST.latency_hist | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 294 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 210 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 210 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 -system.ruby.ST.miss_latency_hist::samples 84 -system.ruby.ST.miss_latency_hist::mean 55.821429 -system.ruby.ST.miss_latency_hist::gmean 48.772534 -system.ruby.ST.miss_latency_hist::stdev 40.751129 -system.ruby.ST.miss_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 84 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 8.043714 -system.ruby.IFETCH.latency_hist::gmean 1.589638 -system.ruby.IFETCH.latency_hist::stdev 23.152025 -system.ruby.IFETCH.latency_hist | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 2585 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2288 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2288 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 297 -system.ruby.IFETCH.miss_latency_hist::mean 62.306397 -system.ruby.IFETCH.miss_latency_hist::gmean 56.498895 -system.ruby.IFETCH.miss_latency_hist::stdev 36.624977 -system.ruby.IFETCH.miss_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 297 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 626 -system.ruby.Directory.miss_mach_latency_hist::mean 57.023962 -system.ruby.Directory.miss_mach_latency_hist::gmean 51.467697 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.986607 -system.ruby.Directory.miss_mach_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 626 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.032653 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.821080 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.902478 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.821429 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.772534 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 40.751129 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 62.306397 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 56.498895 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.624977 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 415 +system.ruby.LD.latency_hist_seqr::mean 30.537349 +system.ruby.LD.latency_hist_seqr::gmean 9.686440 +system.ruby.LD.latency_hist_seqr::stdev 30.265140 +system.ruby.LD.latency_hist_seqr | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 415 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 170 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 170 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 245 +system.ruby.LD.miss_latency_hist_seqr::mean 51.032653 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.821080 +system.ruby.LD.miss_latency_hist_seqr::stdev 22.902478 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 245 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 294 +system.ruby.ST.latency_hist_seqr::mean 16.663265 +system.ruby.ST.latency_hist_seqr::gmean 3.036238 +system.ruby.ST.latency_hist_seqr::stdev 32.952425 +system.ruby.ST.latency_hist_seqr | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 294 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 210 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 210 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 84 +system.ruby.ST.miss_latency_hist_seqr::mean 55.821429 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.772534 +system.ruby.ST.miss_latency_hist_seqr::stdev 40.751129 +system.ruby.ST.miss_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 84 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 2585 +system.ruby.IFETCH.latency_hist_seqr::mean 8.043714 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.589638 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.152025 +system.ruby.IFETCH.latency_hist_seqr | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 2585 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2288 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2288 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 297 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.306397 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.498895 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.624977 +system.ruby.IFETCH.miss_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 297 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.023962 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.467697 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.986607 +system.ruby.Directory.miss_mach_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 626 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.032653 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.821080 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.902478 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.821429 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.772534 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 40.751129 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.306397 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.498895 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.624977 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 826e7e547..16a0ec4c3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index b930fc9fe..bad9ca9c2 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:50 -gem5 executing on zizzer, pid 26249 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:15 +gem5 executing on zizzer, pid 34051 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index cb87636d1..42abe9c49 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18239500 # Number of ticks simulated final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62631 # Simulator instruction rate (inst/s) -host_op_rate 62591 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 442744438 # Simulator tick rate (ticks/s) -host_mem_usage 229340 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 29160 # Simulator instruction rate (inst/s) +host_op_rate 29152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206272099 # Simulator tick rate (ticks/s) +host_mem_usage 229424 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index 746bdfc66..98b98ce6b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index 1671ade6c..b3cb615d2 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:49:24 -gem5 executing on zizzer, pid 11619 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:59 +gem5 executing on zizzer, pid 20780 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 6303bc7a9..5c45eaf46 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29949500 # Number of ticks simulated final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42320 # Simulator instruction rate (inst/s) -host_op_rate 49532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275104580 # Simulator tick rate (ticks/s) -host_mem_usage 247476 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 25443 # Simulator instruction rate (inst/s) +host_op_rate 29781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165422007 # Simulator tick rate (ticks/s) +host_mem_usage 247956 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index c9fb81947..14812c152 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index d15aafd49..4acd461b9 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:49:26 -gem5 executing on zizzer, pid 11626 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:34 +gem5 executing on zizzer, pid 20759 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ee1c5e353..3b3a0c7c5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17170000 # Number of ticks simulated final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17652 # Simulator instruction rate (inst/s) -host_op_rate 20671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65987169 # Simulator tick rate (ticks/s) -host_mem_usage 248556 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 24070 # Simulator instruction rate (inst/s) +host_op_rate 28186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89974051 # Simulator tick rate (ticks/s) +host_mem_usage 249040 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 14ac08a70..465604aeb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 3bc30bbb7..13fb06354 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:09 -gem5 executing on zizzer, pid 11532 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:22 +gem5 executing on zizzer, pid 20738 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 62ddae3c9..4d42e5502 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18741000 # Number of ticks simulated final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24610 # Simulator instruction rate (inst/s) -host_op_rate 28818 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100406204 # Simulator tick rate (ticks/s) -host_mem_usage 244944 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 27191 # Simulator instruction rate (inst/s) +host_op_rate 31839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110934081 # Simulator tick rate (ticks/s) +host_mem_usage 245436 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index b6bc069ea..49256c4fe 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index f03d755a2..dca8243ae 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:49:17 -gem5 executing on zizzer, pid 11612 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:47:11 +gem5 executing on zizzer, pid 20787 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 044fe5830..9ffa594c7 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39910 # Simulator instruction rate (inst/s) -host_op_rate 46729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23410900 # Simulator tick rate (ticks/s) -host_mem_usage 236816 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 13445 # Simulator instruction rate (inst/s) +host_op_rate 15745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7889483 # Simulator tick rate (ticks/s) +host_mem_usage 237392 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index c2e974b56..7af27520b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 74c21a407..994e2e646 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11558 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:25 +gem5 executing on zizzer, pid 20745 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 775f896c2..e53928c68 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93235 # Simulator instruction rate (inst/s) -host_op_rate 109134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54661340 # Simulator tick rate (ticks/s) -host_mem_usage 236444 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 30076 # Simulator instruction rate (inst/s) +host_op_rate 35217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17644392 # Simulator tick rate (ticks/s) +host_mem_usage 236884 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 50d692bb7..21e554bfb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 717c4455b..1bcd9c702 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:49:28 -gem5 executing on zizzer, pid 11633 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:20 +gem5 executing on zizzer, pid 20726 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 82743fe16..be08dbe1d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71050 # Simulator instruction rate (inst/s) -host_op_rate 82905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439999745 # Simulator tick rate (ticks/s) -host_mem_usage 246456 # Number of bytes of host memory used +host_inst_rate 76228 # Simulator instruction rate (inst/s) +host_op_rate 88939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 471979620 # Simulator tick rate (ticks/s) +host_mem_usage 246976 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 850f98b96..47a859a9c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 5ab07ddc0..56ffb166b 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:19 -gem5 executing on zizzer, pid 52953 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:13 +gem5 executing on zizzer, pid 60574 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ad61f594a..1a49e5b1e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22454000 # Number of ticks simulated final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32335 # Simulator instruction rate (inst/s) -host_op_rate 32329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145565694 # Simulator tick rate (ticks/s) -host_mem_usage 230124 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 37869 # Simulator instruction rate (inst/s) +host_op_rate 37861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170465178 # Simulator tick rate (ticks/s) +host_mem_usage 230476 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 461161f2d..c14cdc26c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 111a54e0f..b150c3b1d 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:19 -gem5 executing on zizzer, pid 52939 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:13 +gem5 executing on zizzer, pid 60571 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index fd627c29f..cd97b68c3 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2812000 # Number of ticks simulated final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121410 # Simulator instruction rate (inst/s) -host_op_rate 121348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60644587 # Simulator tick rate (ticks/s) -host_mem_usage 218112 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 70039 # Simulator instruction rate (inst/s) +host_op_rate 70020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35000361 # Simulator tick rate (ticks/s) +host_mem_usage 218484 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index c21ac40c6..66492880c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -348,6 +349,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -409,12 +411,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1013,6 +1017,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 5dbd9e432..64fadbc16 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:19 -gem5 executing on zizzer, pid 52942 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:13 +gem5 executing on zizzer, pid 60577 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index ef81c8d62..3ed561887 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000100 # Nu sim_ticks 100307 # Number of ticks simulated final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21348 # Simulator instruction rate (inst/s) -host_op_rate 21346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380685 # Simulator tick rate (ticks/s) -host_mem_usage 386772 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 28982 # Simulator instruction rate (inst/s) +host_op_rate 28978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 516775 # Simulator tick rate (ticks/s) +host_mem_usage 393304 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -351,37 +351,37 @@ system.ruby.delayHist::max_bucket 9 # de system.ruby.delayHist::samples 2936 # delay histogram for all message system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 2936 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7659 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 12.098329 -system.ruby.latency_hist::gmean 2.138684 -system.ruby.latency_hist::stdev 27.490264 -system.ruby.latency_hist | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7658 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6188 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 58.817007 -system.ruby.miss_latency_hist::gmean 52.469450 -system.ruby.miss_latency_hist::stdev 35.158300 -system.ruby.miss_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1470 -system.ruby.Directory.incomplete_times 1469 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 7659 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 7659 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 7658 +system.ruby.latency_hist_seqr::mean 12.098329 +system.ruby.latency_hist_seqr::gmean 2.138684 +system.ruby.latency_hist_seqr::stdev 27.490264 +system.ruby.latency_hist_seqr | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 7658 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 6188 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6188 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1470 +system.ruby.miss_latency_hist_seqr::mean 58.817007 +system.ruby.miss_latency_hist_seqr::gmean 52.469450 +system.ruby.miss_latency_hist_seqr::stdev 35.158300 +system.ruby.miss_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1470 +system.ruby.Directory.incomplete_times_seqr 1469 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses @@ -461,133 +461,133 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 33.356007 -system.ruby.LD.latency_hist::gmean 9.984943 -system.ruby.LD.latency_hist::stdev 37.413851 -system.ruby.LD.latency_hist | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00% -system.ruby.LD.latency_hist::total 1132 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 465 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 55.913043 -system.ruby.LD.miss_latency_hist::gmean 49.663893 -system.ruby.LD.miss_latency_hist::stdev 33.713440 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% -system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 12.753607 -system.ruby.ST.latency_hist::gmean 2.500911 -system.ruby.ST.latency_hist::stdev 24.939066 -system.ruby.ST.latency_hist | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 901 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 684 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 49.801843 -system.ruby.ST.miss_latency_hist::gmean 44.971096 -system.ruby.ST.miss_latency_hist::stdev 27.840525 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 217 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 7.715378 -system.ruby.IFETCH.latency_hist::gmean 1.529642 -system.ruby.IFETCH.latency_hist::stdev 23.186705 -system.ruby.IFETCH.latency_hist | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 5625 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 5039 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5039 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 65.460751 -system.ruby.IFETCH.miss_latency_hist::gmean 59.138692 -system.ruby.IFETCH.miss_latency_hist::stdev 37.945521 -system.ruby.IFETCH.miss_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 586 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 58.817007 -system.ruby.Directory.miss_mach_latency_hist::gmean 52.469450 -system.ruby.Directory.miss_mach_latency_hist::stdev 35.158300 -system.ruby.Directory.miss_mach_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1470 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 55.913043 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.663893 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.713440 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 49.801843 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.971096 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.840525 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.460751 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 59.138692 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.945521 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 1132 +system.ruby.LD.latency_hist_seqr::mean 33.356007 +system.ruby.LD.latency_hist_seqr::gmean 9.984943 +system.ruby.LD.latency_hist_seqr::stdev 37.413851 +system.ruby.LD.latency_hist_seqr | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00% +system.ruby.LD.latency_hist_seqr::total 1132 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 465 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 465 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 667 +system.ruby.LD.miss_latency_hist_seqr::mean 55.913043 +system.ruby.LD.miss_latency_hist_seqr::gmean 49.663893 +system.ruby.LD.miss_latency_hist_seqr::stdev 33.713440 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 667 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 901 +system.ruby.ST.latency_hist_seqr::mean 12.753607 +system.ruby.ST.latency_hist_seqr::gmean 2.500911 +system.ruby.ST.latency_hist_seqr::stdev 24.939066 +system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 901 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 684 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 684 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 217 +system.ruby.ST.miss_latency_hist_seqr::mean 49.801843 +system.ruby.ST.miss_latency_hist_seqr::gmean 44.971096 +system.ruby.ST.miss_latency_hist_seqr::stdev 27.840525 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 217 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 5625 +system.ruby.IFETCH.latency_hist_seqr::mean 7.715378 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.529642 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.186705 +system.ruby.IFETCH.latency_hist_seqr | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 5625 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5039 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5039 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 586 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.460751 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.138692 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.945521 +system.ruby.IFETCH.miss_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 586 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1470 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.817007 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.469450 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.158300 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1470 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 667 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.913043 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.663893 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.713440 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 667 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.801843 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.971096 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.840525 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.460751 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.138692 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.945521 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index 8be009f7f..af5da1786 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index b5a082e09..349ff71a4 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:19 -gem5 executing on zizzer, pid 52937 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:13 +gem5 executing on zizzer, pid 60580 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 4fd775f32..be6c762f8 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000034 # Nu sim_ticks 33912500 # Number of ticks simulated final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76753 # Simulator instruction rate (inst/s) -host_op_rate 76732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 462561711 # Simulator tick rate (ticks/s) -host_mem_usage 228212 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 109628 # Simulator instruction rate (inst/s) +host_op_rate 109584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 660533411 # Simulator tick rate (ticks/s) +host_mem_usage 228304 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 7183fd9dc..a50b88ac5 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 5302fc253..2fa9ce07e 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:27:54 -gem5 started Dec 11 2015 20:28:28 -gem5 executing on zizzer, pid 60772 -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing +gem5 compiled Jan 21 2016 14:25:19 +gem5 started Jan 21 2016 14:25:54 +gem5 executing on zizzer, pid 3344 +command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ae26100ce..ecbe7b72e 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19923000 # Number of ticks simulated final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39341 # Simulator instruction rate (inst/s) -host_op_rate 39333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135269529 # Simulator tick rate (ticks/s) -host_mem_usage 228324 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 47393 # Simulator instruction rate (inst/s) +host_op_rate 47385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162966075 # Simulator tick rate (ticks/s) +host_mem_usage 228528 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index 476ddb67f..ba8c1a81b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index adad2dedc..0c347fd1b 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:27:54 -gem5 started Dec 11 2015 20:28:29 -gem5 executing on zizzer, pid 60780 -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic +gem5 compiled Jan 21 2016 14:25:19 +gem5 started Jan 21 2016 14:25:54 +gem5 executing on zizzer, pid 3347 +command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index d937e4899..e25b901ab 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100862 # Simulator instruction rate (inst/s) -host_op_rate 100821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50380396 # Simulator tick rate (ticks/s) -host_mem_usage 216424 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 76704 # Simulator instruction rate (inst/s) +host_op_rate 76683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38324639 # Simulator tick rate (ticks/s) +host_mem_usage 216536 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index be4696e87..69aa27452 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 67ee685fb..4be93416d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:38 -gem5 executing on zizzer, pid 884 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:25 +gem5 executing on zizzer, pid 8711 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 338f02648..8bcf3caa4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101577 # Simulator instruction rate (inst/s) -host_op_rate 101519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51322332 # Simulator tick rate (ticks/s) -host_mem_usage 218804 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 62253 # Simulator instruction rate (inst/s) +host_op_rate 62235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31469743 # Simulator tick rate (ticks/s) +host_mem_usage 218904 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 9f0864b0f..d164e90c1 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -345,6 +346,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -406,12 +408,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1010,6 +1014,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 55b085f77..ed1dc8177 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:38 -gem5 executing on zizzer, pid 878 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:28 +gem5 executing on zizzer, pid 8746 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 299320a0d..24a3b23de 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000082 # Nu sim_ticks 81703 # Number of ticks simulated final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 35925 # Simulator instruction rate (inst/s) -host_op_rate 35919 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 550812 # Simulator tick rate (ticks/s) -host_mem_usage 387260 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 27831 # Simulator instruction rate (inst/s) +host_op_rate 27828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 426765 # Simulator tick rate (ticks/s) +host_mem_usage 393224 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -334,37 +334,37 @@ system.ruby.delayHist::max_bucket 9 # de system.ruby.delayHist::samples 2574 # delay histogram for all message system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 2574 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 6759 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 6759 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 11.089819 -system.ruby.latency_hist::gmean 2.095228 -system.ruby.latency_hist::stdev 25.111209 -system.ruby.latency_hist | 6551 96.94% 96.94% | 169 2.50% 99.44% | 28 0.41% 99.85% | 2 0.03% 99.88% | 5 0.07% 99.96% | 2 0.03% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 6758 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 5469 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 5469 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 53.899147 -system.ruby.miss_latency_hist::gmean 48.323546 -system.ruby.miss_latency_hist::stdev 32.275754 -system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1289 -system.ruby.Directory.incomplete_times 1288 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 6759 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 6759 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 6758 +system.ruby.latency_hist_seqr::mean 11.089819 +system.ruby.latency_hist_seqr::gmean 2.095228 +system.ruby.latency_hist_seqr::stdev 25.111209 +system.ruby.latency_hist_seqr | 6551 96.94% 96.94% | 169 2.50% 99.44% | 28 0.41% 99.85% | 2 0.03% 99.88% | 5 0.07% 99.96% | 2 0.03% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 6758 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 5469 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 5469 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1289 +system.ruby.miss_latency_hist_seqr::mean 53.899147 +system.ruby.miss_latency_hist_seqr::gmean 48.323546 +system.ruby.miss_latency_hist_seqr::stdev 32.275754 +system.ruby.miss_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1289 +system.ruby.Directory.incomplete_times_seqr 1288 system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses @@ -444,133 +444,133 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 -system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 28.394406 -system.ruby.LD.latency_hist::gmean 8.251059 -system.ruby.LD.latency_hist::stdev 33.266069 -system.ruby.LD.latency_hist | 656 91.75% 91.75% | 50 6.99% 98.74% | 8 1.12% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 715 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 320 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 320 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 -system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 50.587342 -system.ruby.LD.miss_latency_hist::gmean 45.603541 -system.ruby.LD.miss_latency_hist::stdev 30.035585 -system.ruby.LD.miss_latency_hist | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 395 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 673 -system.ruby.ST.latency_hist::mean 16.656761 -system.ruby.ST.latency_hist::gmean 2.888882 -system.ruby.ST.latency_hist::stdev 31.530024 -system.ruby.ST.latency_hist | 494 73.40% 73.40% | 146 21.69% 95.10% | 26 3.86% 98.96% | 0 0.00% 98.96% | 4 0.59% 99.55% | 0 0.00% 99.55% | 1 0.15% 99.70% | 0 0.00% 99.70% | 1 0.15% 99.85% | 1 0.15% 100.00% -system.ruby.ST.latency_hist::total 673 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 494 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 494 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 179 -system.ruby.ST.miss_latency_hist::mean 59.865922 -system.ruby.ST.miss_latency_hist::gmean 53.981018 -system.ruby.ST.miss_latency_hist::stdev 34.573548 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% -system.ruby.ST.miss_latency_hist::total 179 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 5370 -system.ruby.IFETCH.latency_hist::mean 8.088082 -system.ruby.IFETCH.latency_hist::gmean 1.676829 -system.ruby.IFETCH.latency_hist::stdev 21.661449 -system.ruby.IFETCH.latency_hist | 5255 97.86% 97.86% | 93 1.73% 99.59% | 16 0.30% 99.89% | 1 0.02% 99.91% | 3 0.06% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 5370 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 4655 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 4655 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 715 -system.ruby.IFETCH.miss_latency_hist::mean 54.234965 -system.ruby.IFETCH.miss_latency_hist::gmean 48.531211 -system.ruby.IFETCH.miss_latency_hist::stdev 32.684395 -system.ruby.IFETCH.miss_latency_hist | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 715 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 53.899147 -system.ruby.Directory.miss_mach_latency_hist::gmean 48.323546 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.275754 -system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1289 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.587342 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.603541 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.035585 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 59.865922 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 53.981018 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 34.573548 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 54.234965 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 48.531211 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.684395 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 715 +system.ruby.LD.latency_hist_seqr::mean 28.394406 +system.ruby.LD.latency_hist_seqr::gmean 8.251059 +system.ruby.LD.latency_hist_seqr::stdev 33.266069 +system.ruby.LD.latency_hist_seqr | 656 91.75% 91.75% | 50 6.99% 98.74% | 8 1.12% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 715 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 320 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 320 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 395 +system.ruby.LD.miss_latency_hist_seqr::mean 50.587342 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.603541 +system.ruby.LD.miss_latency_hist_seqr::stdev 30.035585 +system.ruby.LD.miss_latency_hist_seqr | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 395 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 673 +system.ruby.ST.latency_hist_seqr::mean 16.656761 +system.ruby.ST.latency_hist_seqr::gmean 2.888882 +system.ruby.ST.latency_hist_seqr::stdev 31.530024 +system.ruby.ST.latency_hist_seqr | 494 73.40% 73.40% | 146 21.69% 95.10% | 26 3.86% 98.96% | 0 0.00% 98.96% | 4 0.59% 99.55% | 0 0.00% 99.55% | 1 0.15% 99.70% | 0 0.00% 99.70% | 1 0.15% 99.85% | 1 0.15% 100.00% +system.ruby.ST.latency_hist_seqr::total 673 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 494 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 494 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 179 +system.ruby.ST.miss_latency_hist_seqr::mean 59.865922 +system.ruby.ST.miss_latency_hist_seqr::gmean 53.981018 +system.ruby.ST.miss_latency_hist_seqr::stdev 34.573548 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 179 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 5370 +system.ruby.IFETCH.latency_hist_seqr::mean 8.088082 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.676829 +system.ruby.IFETCH.latency_hist_seqr::stdev 21.661449 +system.ruby.IFETCH.latency_hist_seqr | 5255 97.86% 97.86% | 93 1.73% 99.59% | 16 0.30% 99.89% | 1 0.02% 99.91% | 3 0.06% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 5370 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 4655 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 4655 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 715 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 54.234965 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 48.531211 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.684395 +system.ruby.IFETCH.miss_latency_hist_seqr | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 715 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1289 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.899147 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 48.323546 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.275754 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1289 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 395 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.587342 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.603541 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 30.035585 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 395 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 179 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 59.865922 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 53.981018 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 34.573548 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 179 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 715 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 54.234965 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 48.531211 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 32.684395 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 715 system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 858dfb8e0..d3f83cbb3 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 16b6a8f35..0694c2e26 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:39 -gem5 executing on zizzer, pid 890 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:24 +gem5 executing on zizzer, pid 8705 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 409a230f2..a5edc52b5 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30526500 # Number of ticks simulated final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114442 # Simulator instruction rate (inst/s) -host_op_rate 114390 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 655215079 # Simulator tick rate (ticks/s) -host_mem_usage 228624 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 33063 # Simulator instruction rate (inst/s) +host_op_rate 33056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189395194 # Simulator tick rate (ticks/s) +host_mem_usage 228956 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index b620cfb03..b25d031a5 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 4accb5b64..423df5aab 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:48 -gem5 executing on zizzer, pid 10164 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:52 +gem5 executing on zizzer, pid 17884 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index fadbd8dcf..05e87fc08 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20818000 # Number of ticks simulated final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24719 # Simulator instruction rate (inst/s) -host_op_rate 44779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95631897 # Simulator tick rate (ticks/s) -host_mem_usage 249240 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 25768 # Simulator instruction rate (inst/s) +host_op_rate 46680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 99690963 # Simulator tick rate (ticks/s) +host_mem_usage 249596 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index e89a15a8e..54a08b276 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index c2b85dbb9..87f2a402c 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:46 -gem5 executing on zizzer, pid 10133 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:54 +gem5 executing on zizzer, pid 17917 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index ef351b18a..c4292eb87 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91120 # Simulator instruction rate (inst/s) -host_op_rate 165011 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95016732 # Simulator tick rate (ticks/s) -host_mem_usage 236704 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 26569 # Simulator instruction rate (inst/s) +host_op_rate 48126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27718570 # Simulator tick rate (ticks/s) +host_mem_usage 237032 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 3ad4b5b64..a9f89f42a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -379,6 +380,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -440,12 +442,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1045,6 +1049,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 49f0844c2..944308c19 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:48 -gem5 executing on zizzer, pid 10157 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:52 +gem5 executing on zizzer, pid 17892 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 23b6843ca..06e819e18 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000088 # Nu sim_ticks 87948 # Number of ticks simulated final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29086 # Simulator instruction rate (inst/s) -host_op_rate 52683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 475254 # Simulator tick rate (ticks/s) -host_mem_usage 405352 # Number of bytes of host memory used +host_inst_rate 28860 # Simulator instruction rate (inst/s) +host_op_rate 52275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 471584 # Simulator tick rate (ticks/s) +host_mem_usage 411784 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -336,37 +336,37 @@ system.ruby.delayHist::max_bucket 9 # de system.ruby.delayHist::samples 2750 # delay histogram for all message system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 2750 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8852 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8852 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8852 -system.ruby.latency_hist::mean 8.935382 -system.ruby.latency_hist::gmean 1.815175 -system.ruby.latency_hist::stdev 22.675647 -system.ruby.latency_hist | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8852 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 7475 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7475 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1377 -system.ruby.miss_latency_hist::mean 52.012346 -system.ruby.miss_latency_hist::gmean 46.179478 -system.ruby.miss_latency_hist::stdev 33.292581 -system.ruby.miss_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1377 -system.ruby.Directory.incomplete_times 1376 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 8852 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8852 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 8852 +system.ruby.latency_hist_seqr::mean 8.935382 +system.ruby.latency_hist_seqr::gmean 1.815175 +system.ruby.latency_hist_seqr::stdev 22.675647 +system.ruby.latency_hist_seqr | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8852 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 7475 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7475 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1377 +system.ruby.miss_latency_hist_seqr::mean 52.012346 +system.ruby.miss_latency_hist_seqr::gmean 46.179478 +system.ruby.miss_latency_hist_seqr::stdev 33.292581 +system.ruby.miss_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1377 +system.ruby.Directory.incomplete_times_seqr 1376 system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses @@ -446,164 +446,164 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 1045 -system.ruby.LD.latency_hist::mean 22.607656 -system.ruby.LD.latency_hist::gmean 5.952637 -system.ruby.LD.latency_hist::stdev 28.358291 -system.ruby.LD.latency_hist | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1045 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 546 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 546 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 -system.ruby.LD.miss_latency_hist::samples 499 -system.ruby.LD.miss_latency_hist::mean 46.250501 -system.ruby.LD.miss_latency_hist::gmean 41.916728 -system.ruby.LD.miss_latency_hist::stdev 24.776985 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 499 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 935 -system.ruby.ST.latency_hist::mean 15.124064 -system.ruby.ST.latency_hist::gmean 2.829099 -system.ruby.ST.latency_hist::stdev 31.003309 -system.ruby.ST.latency_hist | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 935 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 681 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 681 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 -system.ruby.ST.miss_latency_hist::samples 254 -system.ruby.ST.miss_latency_hist::mean 52.992126 -system.ruby.ST.miss_latency_hist::gmean 45.979346 -system.ruby.ST.miss_latency_hist::stdev 39.646660 -system.ruby.ST.miss_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 254 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 6864 -system.ruby.IFETCH.latency_hist::mean 6.015589 -system.ruby.IFETCH.latency_hist::gmean 1.426336 -system.ruby.IFETCH.latency_hist::stdev 19.173758 -system.ruby.IFETCH.latency_hist | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 6864 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 6241 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 6241 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 623 -system.ruby.IFETCH.miss_latency_hist::mean 56.260032 -system.ruby.IFETCH.miss_latency_hist::gmean 50.022291 -system.ruby.IFETCH.miss_latency_hist::stdev 35.712767 -system.ruby.IFETCH.miss_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 623 -system.ruby.RMW_Read.latency_hist::bucket_size 4 -system.ruby.RMW_Read.latency_hist::max_bucket 39 -system.ruby.RMW_Read.latency_hist::samples 8 -system.ruby.RMW_Read.latency_hist::mean 4.875000 -system.ruby.RMW_Read.latency_hist::gmean 1.542211 -system.ruby.RMW_Read.latency_hist::stdev 10.960155 -system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 8 -system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 -system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 7 -system.ruby.RMW_Read.hit_latency_hist::mean 1 -system.ruby.RMW_Read.hit_latency_hist::gmean 1 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 7 -system.ruby.RMW_Read.miss_latency_hist::bucket_size 4 -system.ruby.RMW_Read.miss_latency_hist::max_bucket 39 -system.ruby.RMW_Read.miss_latency_hist::samples 1 -system.ruby.RMW_Read.miss_latency_hist::mean 32 -system.ruby.RMW_Read.miss_latency_hist::gmean 32 -system.ruby.RMW_Read.miss_latency_hist::stdev nan -system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 1 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist::samples 1377 -system.ruby.Directory.miss_mach_latency_hist::mean 52.012346 -system.ruby.Directory.miss_mach_latency_hist::gmean 46.179478 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.292581 -system.ruby.Directory.miss_mach_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1377 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 46.250501 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 41.916728 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.776985 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.992126 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 45.979346 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 39.646660 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.260032 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.022291 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.712767 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 32 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 32 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 1045 +system.ruby.LD.latency_hist_seqr::mean 22.607656 +system.ruby.LD.latency_hist_seqr::gmean 5.952637 +system.ruby.LD.latency_hist_seqr::stdev 28.358291 +system.ruby.LD.latency_hist_seqr | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1045 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 546 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 546 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 499 +system.ruby.LD.miss_latency_hist_seqr::mean 46.250501 +system.ruby.LD.miss_latency_hist_seqr::gmean 41.916728 +system.ruby.LD.miss_latency_hist_seqr::stdev 24.776985 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 499 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 935 +system.ruby.ST.latency_hist_seqr::mean 15.124064 +system.ruby.ST.latency_hist_seqr::gmean 2.829099 +system.ruby.ST.latency_hist_seqr::stdev 31.003309 +system.ruby.ST.latency_hist_seqr | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 935 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 681 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 681 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 254 +system.ruby.ST.miss_latency_hist_seqr::mean 52.992126 +system.ruby.ST.miss_latency_hist_seqr::gmean 45.979346 +system.ruby.ST.miss_latency_hist_seqr::stdev 39.646660 +system.ruby.ST.miss_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 254 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6864 +system.ruby.IFETCH.latency_hist_seqr::mean 6.015589 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.426336 +system.ruby.IFETCH.latency_hist_seqr::stdev 19.173758 +system.ruby.IFETCH.latency_hist_seqr | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6864 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 6241 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 6241 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 623 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.260032 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.022291 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.712767 +system.ruby.IFETCH.miss_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 623 +system.ruby.RMW_Read.latency_hist_seqr::bucket_size 4 +system.ruby.RMW_Read.latency_hist_seqr::max_bucket 39 +system.ruby.RMW_Read.latency_hist_seqr::samples 8 +system.ruby.RMW_Read.latency_hist_seqr::mean 4.875000 +system.ruby.RMW_Read.latency_hist_seqr::gmean 1.542211 +system.ruby.RMW_Read.latency_hist_seqr::stdev 10.960155 +system.ruby.RMW_Read.latency_hist_seqr | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist_seqr::total 8 +system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1 +system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9 +system.ruby.RMW_Read.hit_latency_hist_seqr::samples 7 +system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1 +system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1 +system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist_seqr::total 7 +system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 4 +system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 39 +system.ruby.RMW_Read.miss_latency_hist_seqr::samples 1 +system.ruby.RMW_Read.miss_latency_hist_seqr::mean 32 +system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 32 +system.ruby.RMW_Read.miss_latency_hist_seqr::stdev nan +system.ruby.RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist_seqr::total 1 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1377 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.012346 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.179478 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.292581 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1377 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 499 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 46.250501 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 41.916728 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 24.776985 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 499 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 254 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.992126 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.979346 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 39.646660 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 254 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 623 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.260032 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.022291 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.712767 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 623 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::samples 1 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::mean 32 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::gmean 32 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::stdev nan +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::total 1 system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 7987e385c..ea6813a1a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 8522917e0..b229084a6 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:46 -gem5 executing on zizzer, pid 10136 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:52 +gem5 executing on zizzer, pid 17886 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 124a43d77..79b38ccd2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000031 # Nu sim_ticks 30886500 # Number of ticks simulated final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73831 # Simulator instruction rate (inst/s) -host_op_rate 133710 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423540181 # Simulator tick rate (ticks/s) -host_mem_usage 246764 # Number of bytes of host memory used +host_inst_rate 79759 # Simulator instruction rate (inst/s) +host_op_rate 144442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 457524996 # Simulator tick rate (ticks/s) +host_mem_usage 247116 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index ac8fa6553..5c9532a74 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index f46618e09..c20b17340 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:40 -gem5 executing on zizzer, pid 26224 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33979 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 8443bf393..bbd43d33a 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24832500 # Number of ticks simulated final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35835 # Simulator instruction rate (inst/s) -host_op_rate 35832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69816273 # Simulator tick rate (ticks/s) -host_mem_usage 233096 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 30698 # Simulator instruction rate (inst/s) +host_op_rate 30696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59808518 # Simulator tick rate (ticks/s) +host_mem_usage 233400 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 017b07a93..d4c0bad9a 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index f330d990e..d0519fdf1 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:36 -gem5 executing on zizzer, pid 864 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:27 +gem5 executing on zizzer, pid 8740 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 81fa56ff3..3bae9ea04 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26944000 # Number of ticks simulated final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15232 # Simulator instruction rate (inst/s) -host_op_rate 15231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28427827 # Simulator tick rate (ticks/s) -host_mem_usage 230656 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host +host_inst_rate 15105 # Simulator instruction rate (inst/s) +host_op_rate 15104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28190865 # Simulator tick rate (ticks/s) +host_mem_usage 230788 # Number of bytes of host memory used +host_seconds 0.96 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 16a218931..3f212d6b7 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index a1ec726b5..4cc5ce56f 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:37 -gem5 executing on zizzer, pid 870 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:26 +gem5 executing on zizzer, pid 8728 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 47c95be1e..af8e6136b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19080 # Simulator instruction rate (inst/s) -host_op_rate 19079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9578180 # Simulator tick rate (ticks/s) -host_mem_usage 218588 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host +host_inst_rate 20450 # Simulator instruction rate (inst/s) +host_op_rate 20449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10266040 # Simulator tick rate (ticks/s) +host_mem_usage 218684 # Number of bytes of host memory used +host_seconds 0.74 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 0fdd8baec..0ac73aa5b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 4d47e9243..e9bf8b42d 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:36 -gem5 executing on zizzer, pid 856 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:27 +gem5 executing on zizzer, pid 8737 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b0549da99..256c5877f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 44282500 # Number of ticks simulated final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17131 # Simulator instruction rate (inst/s) -host_op_rate 17131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50030483 # Simulator tick rate (ticks/s) -host_mem_usage 228520 # Number of bytes of host memory used -host_seconds 0.89 # Real time elapsed on the host +host_inst_rate 17930 # Simulator instruction rate (inst/s) +host_op_rate 17930 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52364992 # Simulator tick rate (ticks/s) +host_mem_usage 228848 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini index 41c39ad85..3db01e542 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout index ea62698e7..e1906cb05 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:27 -gem5 executing on zizzer, pid 26140 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:15 +gem5 executing on zizzer, pid 34054 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index db7487bcd..dee41c633 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000406 # Nu sim_ticks 405501000 # Number of ticks simulated final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93588 # Simulator instruction rate (inst/s) -host_op_rate 93555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5888544376 # Simulator tick rate (ticks/s) -host_mem_usage 613408 # Number of bytes of host memory used +host_inst_rate 86197 # Simulator instruction rate (inst/s) +host_op_rate 86167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5423806428 # Simulator tick rate (ticks/s) +host_mem_usage 613516 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini index 581dc1497..66f02e253 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout index 36485ea28..e33184bae 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:31 -gem5 executing on zizzer, pid 26193 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:14 +gem5 executing on zizzer, pid 34037 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index fb8d20e73..f030be200 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000062 # Nu sim_ticks 61610000 # Number of ticks simulated final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114193 # Simulator instruction rate (inst/s) -host_op_rate 114151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1091680385 # Simulator tick rate (ticks/s) -host_mem_usage 617796 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 98323 # Simulator instruction rate (inst/s) +host_op_rate 98283 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 939896452 # Simulator tick rate (ticks/s) +host_mem_usage 618136 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index d888ad621..81f94afc6 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index eaafaeb25..e03d9d874 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:21 -gem5 executing on zizzer, pid 11570 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:47:24 +gem5 executing on zizzer, pid 20809 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index 947b4dc3b..5a6464d85 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000326 # Nu sim_ticks 325849000 # Number of ticks simulated final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62964 # Simulator instruction rate (inst/s) -host_op_rate 72811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4110489437 # Simulator tick rate (ticks/s) -host_mem_usage 629232 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 67062 # Simulator instruction rate (inst/s) +host_op_rate 77548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4377845869 # Simulator tick rate (ticks/s) +host_mem_usage 629736 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index 1b7001d27..bfdad65c3 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index 2f4a76bc8..ba1e40211 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:49:14 -gem5 executing on zizzer, pid 11605 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:47:23 +gem5 executing on zizzer, pid 20801 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 6c7231539..338e36e87 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90039 # Simulator instruction rate (inst/s) -host_op_rate 104098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898984961 # Simulator tick rate (ticks/s) -host_mem_usage 633916 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 93266 # Simulator instruction rate (inst/s) +host_op_rate 107828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 931188295 # Simulator tick rate (ticks/s) +host_mem_usage 634440 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini index afecf57a2..7660b2f8f 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout index b0d2f0791..0bd088620 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:19 -gem5 executing on zizzer, pid 52945 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:13 +gem5 executing on zizzer, pid 60583 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 36dc6a645..e03fcae5a 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000368 # Nu sim_ticks 367783000 # Number of ticks simulated final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74447 # Simulator instruction rate (inst/s) -host_op_rate 74421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4865103995 # Simulator tick rate (ticks/s) -host_mem_usage 611372 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 91194 # Simulator instruction rate (inst/s) +host_op_rate 91153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5958550453 # Simulator tick rate (ticks/s) +host_mem_usage 611392 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini index 15a5935c7..1fc2588a9 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout index da2000ee1..3d3991862 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:20:45 -gem5 started Dec 11 2015 20:21:18 -gem5 executing on zizzer, pid 52934 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level +gem5 compiled Jan 21 2016 14:17:41 +gem5 started Jan 21 2016 14:18:14 +gem5 executing on zizzer, pid 60586 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 7aeaec8de..8a196fe6c 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100643 # Simulator instruction rate (inst/s) -host_op_rate 100605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053107711 # Simulator tick rate (ticks/s) -host_mem_usage 615936 # Number of bytes of host memory used +host_inst_rate 88343 # Simulator instruction rate (inst/s) +host_op_rate 88311 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 924415589 # Simulator tick rate (ticks/s) +host_mem_usage 616028 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index cf2818cc5..9e3e089f3 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index fa062e779..17e9b6a4f 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:38 -gem5 executing on zizzer, pid 888 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:25 +gem5 executing on zizzer, pid 8716 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index ebb081808..05b70a5db 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000333 # Nu sim_ticks 333033000 # Number of ticks simulated final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60032 # Simulator instruction rate (inst/s) -host_op_rate 60015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3601550992 # Simulator tick rate (ticks/s) -host_mem_usage 611780 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 75807 # Simulator instruction rate (inst/s) +host_op_rate 75776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4546866876 # Simulator tick rate (ticks/s) +host_mem_usage 611808 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index a36fa4d36..4591e667c 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index a1be39517..ad0a8825b 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:37 -gem5 executing on zizzer, pid 867 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:26 +gem5 executing on zizzer, pid 8726 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index bb0654828..bf796f4ef 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25419 # Simulator instruction rate (inst/s) -host_op_rate 25415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244292688 # Simulator tick rate (ticks/s) -host_mem_usage 616436 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 45290 # Simulator instruction rate (inst/s) +host_op_rate 45279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 435170568 # Simulator tick rate (ticks/s) +host_mem_usage 616512 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index 898e8cc18..70896c96b 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index dec723929..465ea0a99 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:48 -gem5 executing on zizzer, pid 10154 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:52 +gem5 executing on zizzer, pid 17890 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 4851e7cd4..f579e14d0 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000445 # Nu sim_ticks 445082000 # Number of ticks simulated final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54663 # Simulator instruction rate (inst/s) -host_op_rate 98678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4257260134 # Simulator tick rate (ticks/s) -host_mem_usage 629764 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 66069 # Simulator instruction rate (inst/s) +host_op_rate 119271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5145784728 # Simulator tick rate (ticks/s) +host_mem_usage 629884 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index ef341878b..6b137db47 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index c2f382d52..184ec1b39 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:47 -gem5 executing on zizzer, pid 10146 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:53 +gem5 executing on zizzer, pid 17895 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index b9497fe33..5f983df7d 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73824 # Simulator instruction rate (inst/s) -host_op_rate 133267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 721372990 # Simulator tick rate (ticks/s) -host_mem_usage 634496 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84620 # Simulator instruction rate (inst/s) +host_op_rate 152747 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 826790083 # Simulator tick rate (ticks/s) +host_mem_usage 634592 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index 98757d4d3..25f60d14c 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 19 2016 13:28:55 -gem5 started Jan 19 2016 13:29:16 -gem5 executing on zizzer, pid 48854 +gem5 compiled Jan 21 2016 14:58:44 +gem5 started Jan 21 2016 14:59:07 +gem5 executing on zizzer, pid 26194 command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index ac9e12c7a..9d77c7b26 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000663 # Nu sim_ticks 663454500 # Number of ticks simulated final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63999 # Simulator instruction rate (inst/s) -host_op_rate 131608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 634065338 # Simulator tick rate (ticks/s) -host_mem_usage 1301448 # Number of bytes of host memory used -host_seconds 1.05 # Real time elapsed on the host +host_inst_rate 74039 # Simulator instruction rate (inst/s) +host_op_rate 152254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 733530611 # Simulator tick rate (ticks/s) +host_mem_usage 1301780 # Number of bytes of host memory used +host_seconds 0.90 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -283,40 +283,64 @@ system.ruby.phys_mem.bw_total::cpu0.data 290297225 # To system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 114203 -system.ruby.outstanding_req_hist::mean 1.000035 -system.ruby.outstanding_req_hist::gmean 1.000024 -system.ruby.outstanding_req_hist::stdev 0.005918 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 114203 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 114203 -system.ruby.latency_hist::mean 4.784183 -system.ruby.latency_hist::gmean 2.131364 -system.ruby.latency_hist::stdev 23.846744 -system.ruby.latency_hist | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 114203 -system.ruby.hit_latency_hist::bucket_size 64 -system.ruby.hit_latency_hist::max_bucket 639 -system.ruby.hit_latency_hist::samples 1535 -system.ruby.hit_latency_hist::mean 208.449511 -system.ruby.hit_latency_hist::gmean 208.002927 -system.ruby.hit_latency_hist::stdev 15.847049 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 1535 -system.ruby.miss_latency_hist::bucket_size 4 -system.ruby.miss_latency_hist::max_bucket 39 -system.ruby.miss_latency_hist::samples 112668 -system.ruby.miss_latency_hist::mean 2.009426 -system.ruby.miss_latency_hist::gmean 2.002413 -system.ruby.miss_latency_hist::stdev 0.411800 -system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 112668 -system.ruby.L1Cache.incomplete_times 112609 -system.ruby.L2Cache.incomplete_times 59 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 114203 +system.ruby.outstanding_req_hist_seqr::mean 1.000035 +system.ruby.outstanding_req_hist_seqr::gmean 1.000024 +system.ruby.outstanding_req_hist_seqr::stdev 0.005918 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 114203 +system.ruby.outstanding_req_hist_coalsr::bucket_size 1 +system.ruby.outstanding_req_hist_coalsr::max_bucket 9 +system.ruby.outstanding_req_hist_coalsr::samples 28 +system.ruby.outstanding_req_hist_coalsr::mean 1.642857 +system.ruby.outstanding_req_hist_coalsr::gmean 1.455771 +system.ruby.outstanding_req_hist_coalsr::stdev 0.911421 +system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 57.14% 57.14% | 8 28.57% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_coalsr::total 28 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 114203 +system.ruby.latency_hist_seqr::mean 4.784183 +system.ruby.latency_hist_seqr::gmean 2.131364 +system.ruby.latency_hist_seqr::stdev 23.846744 +system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 114203 +system.ruby.latency_hist_coalsr::bucket_size 64 +system.ruby.latency_hist_coalsr::max_bucket 639 +system.ruby.latency_hist_coalsr::samples 28 +system.ruby.latency_hist_coalsr::mean 136.285714 +system.ruby.latency_hist_coalsr::gmean 19.975449 +system.ruby.latency_hist_coalsr::stdev 139.699905 +system.ruby.latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::total 28 +system.ruby.hit_latency_hist_seqr::bucket_size 64 +system.ruby.hit_latency_hist_seqr::max_bucket 639 +system.ruby.hit_latency_hist_seqr::samples 1535 +system.ruby.hit_latency_hist_seqr::mean 208.449511 +system.ruby.hit_latency_hist_seqr::gmean 208.002927 +system.ruby.hit_latency_hist_seqr::stdev 15.847049 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 1535 +system.ruby.miss_latency_hist_seqr::bucket_size 4 +system.ruby.miss_latency_hist_seqr::max_bucket 39 +system.ruby.miss_latency_hist_seqr::samples 112668 +system.ruby.miss_latency_hist_seqr::mean 2.009426 +system.ruby.miss_latency_hist_seqr::gmean 2.002413 +system.ruby.miss_latency_hist_seqr::stdev 0.411800 +system.ruby.miss_latency_hist_seqr | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 112668 +system.ruby.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.miss_latency_hist_coalsr::max_bucket 639 +system.ruby.miss_latency_hist_coalsr::samples 28 +system.ruby.miss_latency_hist_coalsr::mean 136.285714 +system.ruby.miss_latency_hist_coalsr::gmean 19.975449 +system.ruby.miss_latency_hist_coalsr::stdev 139.699905 +system.ruby.miss_latency_hist_coalsr | 14 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 10 35.71% 85.71% | 1 3.57% 89.29% | 3 10.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::total 28 +system.ruby.L1Cache.incomplete_times_seqr 112609 +system.ruby.L2Cache.incomplete_times_seqr 59 system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses @@ -2892,236 +2916,363 @@ system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00% system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00% system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 -system.ruby.LD.latency_hist::samples 16335 -system.ruby.LD.latency_hist::mean 4.217447 -system.ruby.LD.latency_hist::gmean 2.103537 -system.ruby.LD.latency_hist::stdev 21.286370 -system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 16335 -system.ruby.LD.hit_latency_hist::bucket_size 32 -system.ruby.LD.hit_latency_hist::max_bucket 319 -system.ruby.LD.hit_latency_hist::samples 175 -system.ruby.LD.hit_latency_hist::mean 208.468571 -system.ruby.LD.hit_latency_hist::gmean 208.231054 -system.ruby.LD.hit_latency_hist::stdev 10.632194 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 175 -system.ruby.LD.miss_latency_hist::bucket_size 4 -system.ruby.LD.miss_latency_hist::max_bucket 39 -system.ruby.LD.miss_latency_hist::samples 16160 -system.ruby.LD.miss_latency_hist::mean 2.005569 -system.ruby.LD.miss_latency_hist::gmean 2.001425 -system.ruby.LD.miss_latency_hist::stdev 0.316580 -system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 16160 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 -system.ruby.ST.latency_hist::samples 10412 -system.ruby.ST.latency_hist::mean 8.385709 -system.ruby.ST.latency_hist::gmean 2.308923 -system.ruby.ST.latency_hist::stdev 35.862445 -system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 10412 -system.ruby.ST.hit_latency_hist::bucket_size 64 -system.ruby.ST.hit_latency_hist::max_bucket 639 -system.ruby.ST.hit_latency_hist::samples 322 -system.ruby.ST.hit_latency_hist::mean 208.484472 -system.ruby.ST.hit_latency_hist::gmean 208.014366 -system.ruby.ST.hit_latency_hist::stdev 16.327683 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 322 -system.ruby.ST.miss_latency_hist::bucket_size 1 -system.ruby.ST.miss_latency_hist::max_bucket 9 -system.ruby.ST.miss_latency_hist::samples 10090 -system.ruby.ST.miss_latency_hist::mean 2 -system.ruby.ST.miss_latency_hist::gmean 2.000000 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 10090 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 87095 -system.ruby.IFETCH.latency_hist::mean 4.462093 -system.ruby.IFETCH.latency_hist::gmean 2.116390 -system.ruby.IFETCH.latency_hist::stdev 22.435279 -system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 87095 -system.ruby.IFETCH.hit_latency_hist::bucket_size 64 -system.ruby.IFETCH.hit_latency_hist::max_bucket 639 -system.ruby.IFETCH.hit_latency_hist::samples 1034 -system.ruby.IFETCH.hit_latency_hist::mean 208.444874 -system.ruby.IFETCH.hit_latency_hist::gmean 207.968565 -system.ruby.IFETCH.hit_latency_hist::stdev 16.462617 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 1034 -system.ruby.IFETCH.miss_latency_hist::bucket_size 4 -system.ruby.IFETCH.miss_latency_hist::max_bucket 39 -system.ruby.IFETCH.miss_latency_hist::samples 86061 -system.ruby.IFETCH.miss_latency_hist::mean 2.011294 -system.ruby.IFETCH.miss_latency_hist::gmean 2.002892 -system.ruby.IFETCH.miss_latency_hist::stdev 0.450747 -system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 86061 -system.ruby.RMW_Read.latency_hist::bucket_size 32 -system.ruby.RMW_Read.latency_hist::max_bucket 319 -system.ruby.RMW_Read.latency_hist::samples 341 -system.ruby.RMW_Read.latency_hist::mean 4.392962 -system.ruby.RMW_Read.latency_hist::gmean 2.111743 -system.ruby.RMW_Read.latency_hist::stdev 21.996747 -system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 4 1.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 341 -system.ruby.RMW_Read.hit_latency_hist::bucket_size 32 -system.ruby.RMW_Read.hit_latency_hist::max_bucket 319 -system.ruby.RMW_Read.hit_latency_hist::samples 4 -system.ruby.RMW_Read.hit_latency_hist::mean 206 -system.ruby.RMW_Read.hit_latency_hist::gmean 206.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 4 -system.ruby.RMW_Read.miss_latency_hist::bucket_size 1 -system.ruby.RMW_Read.miss_latency_hist::max_bucket 9 -system.ruby.RMW_Read.miss_latency_hist::samples 337 -system.ruby.RMW_Read.miss_latency_hist::mean 2 -system.ruby.RMW_Read.miss_latency_hist::gmean 2.000000 -system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 337 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.latency_hist::samples 10 -system.ruby.Locked_RMW_Read.latency_hist::mean 2 -system.ruby.Locked_RMW_Read.latency_hist::gmean 2 -system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 10 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 2 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 2 -system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 10 -system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 10 -system.ruby.Locked_RMW_Write.latency_hist::mean 2 -system.ruby.Locked_RMW_Write.latency_hist::gmean 2 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 10 -system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 -system.ruby.Locked_RMW_Write.miss_latency_hist::mean 2 -system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 2 -system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.miss_latency_hist::total 10 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.miss_mach_latency_hist::samples 112609 -system.ruby.L1Cache.miss_mach_latency_hist::mean 2 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 2.000000 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 112609 -system.ruby.L2Cache.miss_mach_latency_hist::bucket_size 4 -system.ruby.L2Cache.miss_mach_latency_hist::max_bucket 39 -system.ruby.L2Cache.miss_mach_latency_hist::samples 59 -system.ruby.L2Cache.miss_mach_latency_hist::mean 20 -system.ruby.L2Cache.miss_mach_latency_hist::gmean 20.000000 -system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.miss_mach_latency_hist::total 59 -system.ruby.Directory.hit_mach_latency_hist::bucket_size 64 -system.ruby.Directory.hit_mach_latency_hist::max_bucket 639 -system.ruby.Directory.hit_mach_latency_hist::samples 1535 -system.ruby.Directory.hit_mach_latency_hist::mean 208.449511 -system.ruby.Directory.hit_mach_latency_hist::gmean 208.002927 -system.ruby.Directory.hit_mach_latency_hist::stdev 15.847049 -system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.hit_mach_latency_hist::total 1535 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16155 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 4 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 39 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 5 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 20 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 20.000000 -system.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 5 -system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 319 -system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175 -system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 208.468571 -system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 208.231054 -system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 10.632194 -system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.hit_type_mach_latency_hist::total 175 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10090 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10090 -system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 639 -system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 322 -system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 208.484472 -system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 208.014366 -system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 16.327683 -system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.hit_type_mach_latency_hist::total 322 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 4 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 39 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 20 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 20.000000 -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 54 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 208.444874 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 207.968565 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 16.462617 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 206 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 206.000000 -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 2 -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 2 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 2 -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 16335 +system.ruby.LD.latency_hist_seqr::mean 4.217447 +system.ruby.LD.latency_hist_seqr::gmean 2.103537 +system.ruby.LD.latency_hist_seqr::stdev 21.286370 +system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 16335 +system.ruby.LD.latency_hist_coalsr::bucket_size 64 +system.ruby.LD.latency_hist_coalsr::max_bucket 639 +system.ruby.LD.latency_hist_coalsr::samples 10 +system.ruby.LD.latency_hist_coalsr::mean 119.100000 +system.ruby.LD.latency_hist_coalsr::gmean 16.830524 +system.ruby.LD.latency_hist_coalsr::stdev 153.079827 +system.ruby.LD.latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::total 10 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 32 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 319 +system.ruby.LD.hit_latency_hist_seqr::samples 175 +system.ruby.LD.hit_latency_hist_seqr::mean 208.468571 +system.ruby.LD.hit_latency_hist_seqr::gmean 208.231054 +system.ruby.LD.hit_latency_hist_seqr::stdev 10.632194 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 175 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 4 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 39 +system.ruby.LD.miss_latency_hist_seqr::samples 16160 +system.ruby.LD.miss_latency_hist_seqr::mean 2.005569 +system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425 +system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580 +system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 16160 +system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.miss_latency_hist_coalsr::samples 10 +system.ruby.LD.miss_latency_hist_coalsr::mean 119.100000 +system.ruby.LD.miss_latency_hist_coalsr::gmean 16.830524 +system.ruby.LD.miss_latency_hist_coalsr::stdev 153.079827 +system.ruby.LD.miss_latency_hist_coalsr | 6 60.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::total 10 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 10412 +system.ruby.ST.latency_hist_seqr::mean 8.385709 +system.ruby.ST.latency_hist_seqr::gmean 2.308923 +system.ruby.ST.latency_hist_seqr::stdev 35.862445 +system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 10412 +system.ruby.ST.latency_hist_coalsr::bucket_size 32 +system.ruby.ST.latency_hist_coalsr::max_bucket 319 +system.ruby.ST.latency_hist_coalsr::samples 16 +system.ruby.ST.latency_hist_coalsr::mean 125.375000 +system.ruby.ST.latency_hist_coalsr::gmean 15.803091 +system.ruby.ST.latency_hist_coalsr::stdev 128.466792 +system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::total 16 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 +system.ruby.ST.hit_latency_hist_seqr::samples 322 +system.ruby.ST.hit_latency_hist_seqr::mean 208.484472 +system.ruby.ST.hit_latency_hist_seqr::gmean 208.014366 +system.ruby.ST.hit_latency_hist_seqr::stdev 16.327683 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 322 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 +system.ruby.ST.miss_latency_hist_seqr::samples 10090 +system.ruby.ST.miss_latency_hist_seqr::mean 2 +system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 10090 +system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 +system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.miss_latency_hist_coalsr::samples 16 +system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 +system.ruby.ST.miss_latency_hist_coalsr::gmean 15.803091 +system.ruby.ST.miss_latency_hist_coalsr::stdev 128.466792 +system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::total 16 +system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 +system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 +system.ruby.ATOMIC.latency_hist_coalsr::samples 2 +system.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000 +system.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100 +system.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076 +system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ATOMIC.latency_hist_coalsr::total 2 +system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 +system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 +system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000 +system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100 +system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076 +system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 87095 +system.ruby.IFETCH.latency_hist_seqr::mean 4.462093 +system.ruby.IFETCH.latency_hist_seqr::gmean 2.116390 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.435279 +system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 87095 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.444874 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.968565 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.462617 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1034 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 86061 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 2.011294 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist_seqr::total 337 +system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 10 +system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 2 +system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 2 +system.ruby.Locked_RMW_Read.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist_seqr::total 10 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 10 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 2 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 2 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 10 +system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 10 +system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 2 +system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 2 +system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist_seqr::total 10 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0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 112609 +system.ruby.L2Cache.miss_mach_latency_hist_seqr::bucket_size 4 +system.ruby.L2Cache.miss_mach_latency_hist_seqr::max_bucket 39 +system.ruby.L2Cache.miss_mach_latency_hist_seqr::samples 59 +system.ruby.L2Cache.miss_mach_latency_hist_seqr::mean 20 +system.ruby.L2Cache.miss_mach_latency_hist_seqr::gmean 20.000000 +system.ruby.L2Cache.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 +system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 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0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 208.484472 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 208.014366 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 16.327683 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.737699 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.659216 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 267 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 267.000000 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.444874 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.968565 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.462617 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 34ba26c0c..0496a5daf 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout index 04bfae288..3e4fd6df8 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:36 -gem5 executing on zizzer, pid 11591 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:19 +gem5 executing on zizzer, pid 20715 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 01ad66d25..f57e8a542 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 678405 # Simulator instruction rate (inst/s) -host_op_rate 681784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 405392222 # Simulator tick rate (ticks/s) -host_mem_usage 371440 # Number of bytes of host memory used -host_seconds 133.55 # Real time elapsed on the host +host_inst_rate 763855 # Simulator instruction rate (inst/s) +host_op_rate 767659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 456454296 # Simulator tick rate (ticks/s) +host_mem_usage 371948 # Number of bytes of host memory used +host_seconds 118.61 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini index c371a6892..ef1559159 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout index fc6bec5e4..cd6f7e703 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:48:13 -gem5 executing on zizzer, pid 11598 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:47 +gem5 executing on zizzer, pid 20773 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index fca91080e..7302f4619 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147149 # Nu sim_ticks 147148719500 # Number of ticks simulated final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 449018 # Simulator instruction rate (inst/s) -host_op_rate 451250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 729462903 # Simulator tick rate (ticks/s) -host_mem_usage 381564 # Number of bytes of host memory used -host_seconds 201.72 # Real time elapsed on the host +host_inst_rate 392484 # Simulator instruction rate (inst/s) +host_op_rate 394434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 637618235 # Simulator tick rate (ticks/s) +host_mem_usage 382304 # Number of bytes of host memory used +host_seconds 230.78 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index e249ca1b4..6630f8e67 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout index b224febed..db6d1fe13 100755 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:36 -gem5 executing on zizzer, pid 860 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:24 +gem5 executing on zizzer, pid 8701 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index e23b7a821..b85047da6 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1196156 # Simulator instruction rate (inst/s) -host_op_rate 1196205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 599565352 # Simulator tick rate (ticks/s) -host_mem_usage 352760 # Number of bytes of host memory used -host_seconds 203.84 # Real time elapsed on the host +host_inst_rate 1145191 # Simulator instruction rate (inst/s) +host_op_rate 1145238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 574019671 # Simulator tick rate (ticks/s) +host_mem_usage 353116 # Number of bytes of host memory used +host_seconds 212.91 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index d82671fd1..b68d2ad5d 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout index a6f3b193d..593cf5faf 100755 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:47 -gem5 executing on zizzer, pid 10140 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:53 +gem5 executing on zizzer, pid 17901 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 7eb5386cc..98c94dc36 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 621138 # Simulator instruction rate (inst/s) -host_op_rate 1093725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 664233757 # Simulator tick rate (ticks/s) -host_mem_usage 379176 # Number of bytes of host memory used -host_seconds 254.35 # Real time elapsed on the host +host_inst_rate 537919 # Simulator instruction rate (inst/s) +host_op_rate 947189 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 575240737 # Simulator tick rate (ticks/s) +host_mem_usage 379572 # Number of bytes of host memory used +host_seconds 293.70 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr index 8af5388f9..e69de29bb 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout index beb85a584..03581733b 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,13 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 28 2015 15:28:59 -gem5 started Dec 28 2015 15:29:36 -gem5 executing on zizzer, pid 17011 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:02 +gem5 executing on zizzer, pid 33994 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 250015500 because a thread reached the max instruction count +Skipping test: Test requires the 'EioProcess' SimObject. diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index eda017d3a..e69de29bb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1343751 # Simulator instruction rate (inst/s) -host_op_rate 1343676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 671839384 # Simulator tick rate (ticks/s) -host_mem_usage 219380 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -sim_insts 500001 # Number of instructions simulated -sim_ops 500001 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory -system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory -system.physmem.bytes_written::total 417562 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory -system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory -system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.itb.fetch_hits 500019 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 500032 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 500001 # Number of instructions committed -system.cpu.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu.num_func_calls 14357 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu.num_int_insts 474689 # number of integer instructions -system.cpu.num_fp_insts 32 # number of float instructions -system.cpu.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 180793 # number of memory refs -system.cpu.num_load_insts 124443 # Number of load instructions -system.cpu.num_store_insts 56350 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 500032 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 59023 # Number of branches fetched -system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 500019 # Class of executed instruction -system.membus.trans_dist::ReadReq 624454 # Transaction distribution -system.membus.trans_dist::ReadResp 624454 # Transaction distribution -system.membus.trans_dist::WriteReq 56340 # Transaction distribution -system.membus.trans_dist::WriteResp 56340 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 680794 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 680794 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr index 8af5388f9..e69de29bb 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout index 5ef84b024..7a11e4e17 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -1,13 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 28 2015 15:28:59 -gem5 started Dec 28 2015 15:29:36 -gem5 executing on zizzer, pid 16987 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:26 +gem5 executing on zizzer, pid 34075 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 733071500 because a thread reached the max instruction count +Skipping test: Test requires the 'EioProcess' SimObject. diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index b40909ba4..e69de29bb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,506 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000733 # Number of seconds simulated -sim_ticks 733071500 # Number of ticks simulated -final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 615620 # Simulator instruction rate (inst/s) -host_op_rate 615603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 902538658 # Simulator tick rate (ticks/s) -host_mem_usage 229472 # Number of bytes of host memory used -host_seconds 0.81 # Real time elapsed on the host -sim_insts 500001 # Number of instructions simulated -sim_ops 500001 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 54848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 857 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.itb.fetch_hits 500020 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 500033 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 1466143 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 500001 # Number of instructions committed -system.cpu.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu.num_func_calls 14357 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu.num_int_insts 474689 # number of integer instructions -system.cpu.num_fp_insts 32 # number of float instructions -system.cpu.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 180793 # number of memory refs -system.cpu.num_load_insts 124443 # Number of load instructions -system.cpu.num_store_insts 56350 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1466143 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 59023 # Number of branches fetched -system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 500019 # Class of executed instruction -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits -system.cpu.dcache.overall_hits::total 180321 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses -system.cpu.dcache.overall_misses::total 454 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19215000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27694000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27694000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27694000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27694000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 264.585152 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.129192 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.129192 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits -system.cpu.icache.overall_hits::total 499617 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses -system.cpu.icache.overall_misses::total 403 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24986500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24986500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24986500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24986500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24986500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24986500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62001.240695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62001.240695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24583500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24583500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 264.590924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.089673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008075 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006595 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.014669 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses -system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses -system.cpu.l2cache.overall_misses::total 857 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8270500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23979000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 23979000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18742500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18742500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23979000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27013000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50992000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23979000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27013000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50992000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6880500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6880500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19949000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19949000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19949000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 42422000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19949000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 42422000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 718 # Transaction distribution -system.membus.trans_dist::ReadExReq 139 # Transaction distribution -system.membus.trans_dist::ReadExResp 139 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 857 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 857 # Request fanout histogram -system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 8be63e416..e69de29bb 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything - -gzip: stdout: Broken pipe -stdout: Broken pipe -stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 3b3d48d71..20b7b421f 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -1,19 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 28 2015 15:28:59 -gem5 started Dec 28 2015 15:29:36 -gem5 executing on zizzer, pid 16984 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33976 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 250015500 because a thread reached the max instruction count +Skipping test: Test requires the 'EioProcess' SimObject. diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 49cb88e7a..e69de29bb 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,1109 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1316987 # Simulator instruction rate (inst/s) -host_op_rate 1316968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164628751 # Simulator tick rate (ticks/s) -host_mem_usage 243288 # Number of bytes of host memory used -host_seconds 1.52 # Real time elapsed on the host -sim_insts 2000004 # Number of instructions simulated -sim_ops 2000004 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 219392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.itb.fetch_hits 500019 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_accesses 500032 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 500032 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 500001 # Number of instructions committed -system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu0.num_func_calls 14357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu0.num_int_insts 474689 # number of integer instructions -system.cpu0.num_fp_insts 32 # number of float instructions -system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu0.num_mem_refs 180793 # number of memory refs -system.cpu0.num_load_insts 124443 # Number of load instructions -system.cpu0.num_store_insts 56350 # Number of store instructions -system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 500032 # Number of busy cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.Branches 59023 # Number of branches fetched -system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 500019 # Class of executed instruction -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits -system.cpu0.dcache.overall_hits::total 180312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses -system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu0.dcache.writebacks::total 29 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits -system.cpu0.icache.overall_hits::total 499556 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses -system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 152 # number of writebacks -system.cpu0.icache.writebacks::total 152 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.write_hits 56340 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_accesses 56350 # DTB write accesses -system.cpu1.dtb.data_hits 180775 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_accesses 180793 # DTB accesses -system.cpu1.itb.fetch_hits 500019 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 500032 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 500032 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 500001 # Number of instructions committed -system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu1.num_func_calls 14357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474689 # number of integer instructions -system.cpu1.num_fp_insts 32 # number of float instructions -system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu1.num_mem_refs 180793 # number of memory refs -system.cpu1.num_load_insts 124443 # Number of load instructions -system.cpu1.num_store_insts 56350 # Number of store instructions -system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 500032 # Number of busy cycles -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.Branches 59023 # Number of branches fetched -system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu1.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 500019 # Class of executed instruction -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits -system.cpu1.dcache.overall_hits::total 180312 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses -system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu1.dcache.writebacks::total 29 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits -system.cpu1.icache.overall_hits::total 499556 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses -system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 152 # number of writebacks -system.cpu1.icache.writebacks::total 152 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.write_hits 56340 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_accesses 56350 # DTB write accesses -system.cpu2.dtb.data_hits 180775 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_accesses 180793 # DTB accesses -system.cpu2.itb.fetch_hits 500019 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_accesses 500032 # ITB accesses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 500032 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 500001 # Number of instructions committed -system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu2.num_func_calls 14357 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu2.num_int_insts 474689 # number of integer instructions -system.cpu2.num_fp_insts 32 # number of float instructions -system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu2.num_mem_refs 180793 # number of memory refs -system.cpu2.num_load_insts 124443 # Number of load instructions -system.cpu2.num_store_insts 56350 # Number of store instructions -system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 500032 # Number of busy cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.Branches 59023 # Number of branches fetched -system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu2.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 500019 # Class of executed instruction -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits -system.cpu2.dcache.overall_hits::total 180312 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses -system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu2.dcache.writebacks::total 29 # number of writebacks -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits -system.cpu2.icache.overall_hits::total 499556 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses -system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks::writebacks 152 # number of writebacks -system.cpu2.icache.writebacks::total 152 # number of writebacks -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.read_hits 124435 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_accesses 124443 # DTB read accesses -system.cpu3.dtb.write_hits 56340 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_accesses 56350 # DTB write accesses -system.cpu3.dtb.data_hits 180775 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_accesses 180793 # DTB accesses -system.cpu3.itb.fetch_hits 500019 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_accesses 500032 # ITB accesses -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 500032 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 500001 # Number of instructions committed -system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu3.num_func_calls 14357 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu3.num_int_insts 474689 # number of integer instructions -system.cpu3.num_fp_insts 32 # number of float instructions -system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu3.num_mem_refs 180793 # number of memory refs -system.cpu3.num_load_insts 124443 # Number of load instructions -system.cpu3.num_store_insts 56350 # Number of store instructions -system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 500032 # Number of busy cycles -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.Branches 59023 # Number of branches fetched -system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu3.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 500019 # Class of executed instruction -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits -system.cpu3.dcache.overall_hits::total 180312 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses -system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu3.dcache.writebacks::total 29 # number of writebacks -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits -system.cpu3.icache.overall_hits::total 499556 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses -system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks::writebacks 152 # number of writebacks -system.cpu3.icache.writebacks::total 152 # number of writebacks -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 39936 # Number of tag accesses -system.l2c.tags.data_accesses 39936 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits -system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 60 # number of overall hits -system.l2c.overall_hits::cpu0.data 9 # number of overall hits -system.l2c.overall_hits::cpu1.inst 60 # number of overall hits -system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 60 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 60 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 403 # number of overall misses -system.l2c.overall_misses::cpu0.data 454 # number of overall misses -system.l2c.overall_misses::cpu1.inst 403 # number of overall misses -system.l2c.overall_misses::cpu1.data 454 # number of overall misses -system.l2c.overall_misses::cpu2.inst 403 # number of overall misses -system.l2c.overall_misses::cpu2.data 454 # number of overall misses -system.l2c.overall_misses::cpu3.inst 403 # number of overall misses -system.l2c.overall_misses::cpu3.data 454 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadResp 2872 # Transaction distribution -system.membus.trans_dist::ReadExReq 556 # Transaction distribution -system.membus.trans_dist::ReadExResp 556 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3428 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3428 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4556 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 12d988946..e69de29bb 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -1,9 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index e8ff7d676..918548b7c 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -1,19 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 28 2015 15:28:59 -gem5 started Dec 28 2015 15:29:48 -gem5 executing on zizzer, pid 17084 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:01 +gem5 executing on zizzer, pid 33988 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 733914500 because a thread reached the max instruction count +Skipping test: Test requires the 'EioProcess' SimObject. diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 6f8a36e17..e69de29bb 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,1661 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000734 # Number of seconds simulated -sim_ticks 733914500 # Number of ticks simulated -final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 640804 # Simulator instruction rate (inst/s) -host_op_rate 640799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 235147461 # Simulator tick rate (ticks/s) -host_mem_usage 243292 # Number of bytes of host memory used -host_seconds 3.12 # Real time elapsed on the host -sim_insts 1999973 # Number of instructions simulated -sim_ops 1999973 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 219392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 298934004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140572233 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298934004 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.itb.fetch_hits 500020 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_accesses 500033 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1467829 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 500001 # Number of instructions committed -system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu0.num_func_calls 14357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu0.num_int_insts 474689 # number of integer instructions -system.cpu0.num_fp_insts 32 # number of float instructions -system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu0.num_mem_refs 180793 # number of memory refs -system.cpu0.num_load_insts 124443 # Number of load instructions -system.cpu0.num_store_insts 56350 # Number of store instructions -system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1467829 # Number of busy cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.Branches 59023 # Number of branches fetched -system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 500019 # Class of executed instruction -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 273.068294 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.068294 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.533337 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.533337 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits -system.cpu0.dcache.overall_hits::total 180312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses -system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19649000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8621000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28270000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu0.dcache.writebacks::total 29 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8482000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27807000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.116668 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.422103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits -system.cpu0.icache.overall_hits::total 499557 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses -system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25776500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25776500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25776500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25776500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25776500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25776500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 55672.786177 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 55672.786177 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 152 # number of writebacks -system.cpu0.icache.writebacks::total 152 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 25313500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 25313500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 25313500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 25313500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 25313500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 25313500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.write_hits 56339 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_accesses 56349 # DTB write accesses -system.cpu1.dtb.data_hits 180774 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_accesses 180792 # DTB accesses -system.cpu1.itb.fetch_hits 500014 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 500027 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1467829 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 499995 # Number of instructions committed -system.cpu1.committedOps 499995 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474683 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu1.num_func_calls 14357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474683 # number of integer instructions -system.cpu1.num_fp_insts 32 # number of float instructions -system.cpu1.num_int_register_reads 654276 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371538 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu1.num_mem_refs 180792 # number of memory refs -system.cpu1.num_load_insts 124443 # Number of load instructions -system.cpu1.num_store_insts 56349 # Number of store instructions -system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1467829 # Number of busy cycles -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.Branches 59022 # Number of branches fetched -system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu1.op_class::IntAlu 300383 60.08% 63.84% # Class of executed instruction -system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 500013 # Class of executed instruction -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 273.065457 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.065457 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.533331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.533331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits -system.cpu1.dcache.overall_hits::total 180311 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses -system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 19649000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8621500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8621500 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 62025.179856 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu1.dcache.writebacks::total 29 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 8482500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 8482500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 27807500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 59645.061728 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61025.179856 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 61025.179856 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 216.114546 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.943844 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.114546 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422099 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.422099 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 499551 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 499551 # number of overall hits -system.cpu1.icache.overall_hits::total 499551 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses -system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 25783000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 25783000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 25783000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 25783000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 25783000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 25783000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 500014 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 500014 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 500014 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 500014 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 500014 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 500014 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 55686.825054 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 55686.825054 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 55686.825054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 55686.825054 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 152 # number of writebacks -system.cpu1.icache.writebacks::total 152 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 25320000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 25320000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 25320000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 25320000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 25320000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 25320000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.write_hits 56339 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_accesses 56349 # DTB write accesses -system.cpu2.dtb.data_hits 180774 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_accesses 180792 # DTB accesses -system.cpu2.itb.fetch_hits 500009 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_accesses 500022 # ITB accesses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1467829 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 499990 # Number of instructions committed -system.cpu2.committedOps 499990 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 474678 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu2.num_func_calls 14357 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu2.num_int_insts 474678 # number of integer instructions -system.cpu2.num_fp_insts 32 # number of float instructions -system.cpu2.num_int_register_reads 654270 # number of times the integer registers were read -system.cpu2.num_int_register_writes 371533 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu2.num_mem_refs 180791 # number of memory refs -system.cpu2.num_load_insts 124442 # Number of load instructions -system.cpu2.num_store_insts 56349 # Number of store instructions -system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1467829 # Number of busy cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.Branches 59022 # Number of branches fetched -system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu2.op_class::IntAlu 300379 60.07% 63.84% # Class of executed instruction -system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::MemRead 124442 24.89% 88.73% # Class of executed instruction -system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 500008 # Class of executed instruction -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 273.062707 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.062707 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.533326 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.533326 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu2.dcache.demand_hits::cpu2.data 180311 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 180311 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 180311 # number of overall hits -system.cpu2.dcache.overall_hits::total 180311 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses -system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 19649000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 8621000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 28270000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 28270000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 180774 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 180774 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 60645.061728 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 62021.582734 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu2.dcache.writebacks::total 29 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 8482000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 27807000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 59645.061728 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 216.112416 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.933045 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.112416 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422095 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.422095 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 499546 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 499546 # number of overall hits -system.cpu2.icache.overall_hits::total 499546 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses -system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 25788500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 25788500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 25788500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 25788500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 25788500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 25788500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 500009 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 500009 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 500009 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 500009 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 500009 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 500009 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 55698.704104 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 55698.704104 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 55698.704104 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks::writebacks 152 # number of writebacks -system.cpu2.icache.writebacks::total 152 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 25325500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 25325500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 25325500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 25325500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 25325500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 25325500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.read_hits 124433 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_accesses 124441 # DTB read accesses -system.cpu3.dtb.write_hits 56339 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_accesses 56349 # DTB write accesses -system.cpu3.dtb.data_hits 180772 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_accesses 180790 # DTB accesses -system.cpu3.itb.fetch_hits 500006 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_accesses 500019 # ITB accesses -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1467829 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 499987 # Number of instructions committed -system.cpu3.committedOps 499987 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 474675 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu3.num_func_calls 14357 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu3.num_int_insts 474675 # number of integer instructions -system.cpu3.num_fp_insts 32 # number of float instructions -system.cpu3.num_int_register_reads 654265 # number of times the integer registers were read -system.cpu3.num_int_register_writes 371530 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu3.num_mem_refs 180790 # number of memory refs -system.cpu3.num_load_insts 124441 # Number of load instructions -system.cpu3.num_store_insts 56349 # Number of store instructions -system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1467829 # Number of busy cycles -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.Branches 59022 # Number of branches fetched -system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu3.op_class::IntAlu 300377 60.07% 63.84% # Class of executed instruction -system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 500005 # Class of executed instruction -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 273.059955 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.059955 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.533320 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.533320 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu3.dcache.demand_hits::cpu3.data 180309 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 180309 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 180309 # number of overall hits -system.cpu3.dcache.overall_hits::total 180309 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses -system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 19649500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 19649500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 8621000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 28270500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 28270500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 180772 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 180772 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 62021.582734 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu3.dcache.writebacks::total 29 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 19325500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 19325500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 8482000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 27807500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 59646.604938 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 59646.604938 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 61021.582734 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 216.110261 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 1078.926566 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.110261 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422090 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.422090 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 499543 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 499543 # number of overall hits -system.cpu3.icache.overall_hits::total 499543 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses -system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 25793000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 25793000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 25793000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 25793000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 25793000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 25793000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 500006 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 500006 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 500006 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 500006 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 500006 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 500006 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 55708.423326 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 55708.423326 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 55708.423326 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 55708.423326 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 55708.423326 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 55708.423326 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks::writebacks 152 # number of writebacks -system.cpu3.icache.writebacks::total 152 # number of writebacks -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 25330000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 25330000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 25330000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 25330000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 25330000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 25330000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 54708.423326 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1940.317854 # Cycle average of tags in use -system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.170012 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 264.661885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 216.132475 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 264.659128 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 216.130297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 264.656363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 216.128138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 264.653570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 216.125986 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029607 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 24 # 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number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 22475500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 19971000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 22476500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 169753500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 19954000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22475500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 19959500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 22476000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 19965500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 22475500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 19971000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 22476500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 169753500 # number of overall MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.870410 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.972222 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49510.791367 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49514.388489 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49510.791367 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49514.388489 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 49512.589928 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49534.739454 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49503.174603 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49503.174603 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49503.174603 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49504.761905 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49503.571429 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadResp 2872 # Transaction distribution -system.membus.trans_dist::ReadExReq 556 # Transaction distribution -system.membus.trans_dist::ReadExResp 556 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3442 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3442 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3442 # Request fanout histogram -system.membus.reqLayer0.occupancy 3471468 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17140000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3704 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 3704 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3704 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3002000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 1d1155cf0..f3f0e1367 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout index 7fb142340..44c2c4d4d 100755 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26163 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:14 +gem5 executing on zizzer, pid 34044 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 7fb444027..d462b7494 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1206963 # Simulator instruction rate (inst/s) -host_op_rate 1206963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 603481628 # Simulator tick rate (ticks/s) -host_mem_usage 226620 # Number of bytes of host memory used -host_seconds 330.30 # Real time elapsed on the host +host_inst_rate 1276946 # Simulator instruction rate (inst/s) +host_op_rate 1276946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 638473293 # Simulator tick rate (ticks/s) +host_mem_usage 226984 # Number of bytes of host memory used +host_seconds 312.20 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 1dacb5c99..694634224 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 8ba85de56..e7f118d3b 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:38 -gem5 executing on zizzer, pid 881 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:28 +gem5 executing on zizzer, pid 8743 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 40e15bce7..459938f5d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107836000 # Number of ticks simulated final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74115 # Simulator instruction rate (inst/s) -host_op_rate 74115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8039101 # Simulator tick rate (ticks/s) -host_mem_usage 247436 # Number of bytes of host memory used -host_seconds 13.41 # Real time elapsed on the host +host_inst_rate 68965 # Simulator instruction rate (inst/s) +host_op_rate 68965 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7480497 # Simulator tick rate (ticks/s) +host_mem_usage 247424 # Number of bytes of host memory used +host_seconds 14.42 # Real time elapsed on the host sim_insts 994171 # Number of instructions simulated sim_ops 994171 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index a24a3b568..ff2e64cda 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 3d91e2cf9..05f972a06 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:39 -gem5 executing on zizzer, pid 893 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:25 +gem5 executing on zizzer, pid 8720 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 0d4d33600..903a3bff1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159037 # Simulator instruction rate (inst/s) -host_op_rate 159036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20593264 # Simulator tick rate (ticks/s) -host_mem_usage 242980 # Number of bytes of host memory used -host_seconds 4.26 # Real time elapsed on the host +host_inst_rate 140858 # Simulator instruction rate (inst/s) +host_op_rate 140857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18239325 # Simulator tick rate (ticks/s) +host_mem_usage 243264 # Number of bytes of host memory used +host_seconds 4.81 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 33ac29f0d..02edfa409 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 9f598bc3b..0436b2616 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:37 -gem5 executing on zizzer, pid 872 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:26 +gem5 executing on zizzer, pid 8732 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a5263a5a3..813d17b05 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000265 # Nu sim_ticks 264840500 # Number of ticks simulated final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139043 # Simulator instruction rate (inst/s) -host_op_rate 139043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55594555 # Simulator tick rate (ticks/s) -host_mem_usage 242988 # Number of bytes of host memory used -host_seconds 4.76 # Real time elapsed on the host +host_inst_rate 127010 # Simulator instruction rate (inst/s) +host_op_rate 127009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50783237 # Simulator tick rate (ticks/s) +host_mem_usage 243272 # Number of bytes of host memory used +host_seconds 5.22 # Real time elapsed on the host sim_insts 662366 # Number of instructions simulated sim_ops 662366 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini index 97f58a0cc..3223dc0b2 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -384,6 +385,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -407,6 +409,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -487,12 +490,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -547,6 +552,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -570,6 +576,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -650,12 +657,14 @@ slave=system.ruby.network.master[3] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -710,6 +719,7 @@ version=2 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -733,6 +743,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -813,12 +824,14 @@ slave=system.ruby.network.master[5] [system.ruby.l1_cntrl2.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl2.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -873,6 +886,7 @@ version=3 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -896,6 +910,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -976,12 +991,14 @@ slave=system.ruby.network.master[7] [system.ruby.l1_cntrl3.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl3.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1036,6 +1053,7 @@ version=4 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1059,6 +1077,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1139,12 +1158,14 @@ slave=system.ruby.network.master[9] [system.ruby.l1_cntrl4.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl4.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1199,6 +1220,7 @@ version=5 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1222,6 +1244,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1302,12 +1325,14 @@ slave=system.ruby.network.master[11] [system.ruby.l1_cntrl5.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl5.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1362,6 +1387,7 @@ version=6 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1385,6 +1411,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1465,12 +1492,14 @@ slave=system.ruby.network.master[13] [system.ruby.l1_cntrl6.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl6.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1525,6 +1554,7 @@ version=7 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1548,6 +1578,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1628,12 +1659,14 @@ slave=system.ruby.network.master[15] [system.ruby.l1_cntrl7.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl7.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1705,6 +1738,7 @@ slave=system.ruby.network.master[17] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -5227,6 +5261,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout index 46a3394b3..891cb5deb 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:05:44 -gem5 started Dec 11 2015 20:06:16 -gem5 executing on zizzer, pid 37021 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level +gem5 compiled Jan 21 2016 14:01:33 +gem5 started Jan 21 2016 14:02:10 +gem5 executing on zizzer, pid 44714 +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 6dedc1551..1566487a2 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu sim_ticks 10021833 # Number of ticks simulated final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 77650 # Simulator tick rate (ticks/s) -host_mem_usage 393812 # Number of bytes of host memory used -host_seconds 129.06 # Real time elapsed on the host +host_tick_rate 66575 # Simulator tick rate (ticks/s) +host_mem_usage 401248 # Number of bytes of host memory used +host_seconds 150.54 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory @@ -310,37 +310,37 @@ system.ruby.delayHist::mean 6.537266 # de system.ruby.delayHist::stdev 17.581596 # delay histogram for all message system.ruby.delayHist | 4675734 93.80% 93.80% | 147874 2.97% 96.76% | 121251 2.43% 99.19% | 34910 0.70% 99.89% | 4283 0.09% 99.98% | 711 0.01% 99.99% | 211 0.00% 100.00% | 36 0.00% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 4985028 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 624868 -system.ruby.outstanding_req_hist::mean 15.998456 -system.ruby.outstanding_req_hist::gmean 15.997188 -system.ruby.outstanding_req_hist::stdev 0.126020 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 624743 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 624868 -system.ruby.latency_hist::bucket_size 1024 -system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 624741 -system.ruby.latency_hist::mean 2053.034201 -system.ruby.latency_hist::gmean 1585.285080 -system.ruby.latency_hist::stdev 1206.859039 -system.ruby.latency_hist | 164671 26.36% 26.36% | 154480 24.73% 51.09% | 150906 24.15% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 624741 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 10 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 10 -system.ruby.miss_latency_hist::bucket_size 1024 -system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 624731 -system.ruby.miss_latency_hist::mean 2053.067048 -system.ruby.miss_latency_hist::gmean 1585.472070 -system.ruby.miss_latency_hist::stdev 1206.840773 -system.ruby.miss_latency_hist | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 624731 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 624868 +system.ruby.outstanding_req_hist_seqr::mean 15.998456 +system.ruby.outstanding_req_hist_seqr::gmean 15.997188 +system.ruby.outstanding_req_hist_seqr::stdev 0.126020 +system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 624743 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 624868 +system.ruby.latency_hist_seqr::bucket_size 1024 +system.ruby.latency_hist_seqr::max_bucket 10239 +system.ruby.latency_hist_seqr::samples 624741 +system.ruby.latency_hist_seqr::mean 2053.034201 +system.ruby.latency_hist_seqr::gmean 1585.285080 +system.ruby.latency_hist_seqr::stdev 1206.859039 +system.ruby.latency_hist_seqr | 164671 26.36% 26.36% | 154480 24.73% 51.09% | 150906 24.15% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 624741 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 10 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 10 +system.ruby.miss_latency_hist_seqr::bucket_size 1024 +system.ruby.miss_latency_hist_seqr::max_bucket 10239 +system.ruby.miss_latency_hist_seqr::samples 624731 +system.ruby.miss_latency_hist_seqr::mean 2053.067048 +system.ruby.miss_latency_hist_seqr::gmean 1585.472070 +system.ruby.miss_latency_hist_seqr::stdev 1206.840773 +system.ruby.miss_latency_hist_seqr | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 624731 system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78237 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78237 # Number of cache demand accesses @@ -966,52 +966,52 @@ system.ruby.delayVCHist.vnet_2::mean 0.008929 # de system.ruby.delayVCHist.vnet_2::stdev 0.133339 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 609846 99.55% 99.55% | 0 0.00% 99.55% | 2735 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 612581 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 1024 -system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 401903 -system.ruby.LD.latency_hist::mean 2053.043401 -system.ruby.LD.latency_hist::gmean 1585.283402 -system.ruby.LD.latency_hist::stdev 1206.884955 -system.ruby.LD.latency_hist | 106001 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 401903 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 7 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 7 -system.ruby.LD.miss_latency_hist::bucket_size 1024 -system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 401896 -system.ruby.LD.miss_latency_hist::mean 2053.079142 -system.ruby.LD.miss_latency_hist::gmean 1585.486872 -system.ruby.LD.miss_latency_hist::stdev 1206.865080 -system.ruby.LD.miss_latency_hist | 105994 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401896 -system.ruby.ST.latency_hist::bucket_size 1024 -system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 222838 -system.ruby.ST.latency_hist::mean 2053.017609 -system.ruby.ST.latency_hist::gmean 1585.288106 -system.ruby.ST.latency_hist::stdev 1206.815003 -system.ruby.ST.latency_hist | 58670 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 222838 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 3 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 3 -system.ruby.ST.miss_latency_hist::bucket_size 1024 -system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 222835 -system.ruby.ST.miss_latency_hist::mean 2053.045235 -system.ruby.ST.miss_latency_hist::gmean 1585.445376 -system.ruby.ST.miss_latency_hist::stdev 1206.799639 -system.ruby.ST.miss_latency_hist | 58667 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222835 +system.ruby.LD.latency_hist_seqr::bucket_size 1024 +system.ruby.LD.latency_hist_seqr::max_bucket 10239 +system.ruby.LD.latency_hist_seqr::samples 401903 +system.ruby.LD.latency_hist_seqr::mean 2053.043401 +system.ruby.LD.latency_hist_seqr::gmean 1585.283402 +system.ruby.LD.latency_hist_seqr::stdev 1206.884955 +system.ruby.LD.latency_hist_seqr | 106001 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 401903 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 7 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 7 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 1024 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 10239 +system.ruby.LD.miss_latency_hist_seqr::samples 401896 +system.ruby.LD.miss_latency_hist_seqr::mean 2053.079142 +system.ruby.LD.miss_latency_hist_seqr::gmean 1585.486872 +system.ruby.LD.miss_latency_hist_seqr::stdev 1206.865080 +system.ruby.LD.miss_latency_hist_seqr | 105994 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 401896 +system.ruby.ST.latency_hist_seqr::bucket_size 1024 +system.ruby.ST.latency_hist_seqr::max_bucket 10239 +system.ruby.ST.latency_hist_seqr::samples 222838 +system.ruby.ST.latency_hist_seqr::mean 2053.017609 +system.ruby.ST.latency_hist_seqr::gmean 1585.288106 +system.ruby.ST.latency_hist_seqr::stdev 1206.815003 +system.ruby.ST.latency_hist_seqr | 58670 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 222838 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 3 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 3 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 1024 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 10239 +system.ruby.ST.miss_latency_hist_seqr::samples 222835 +system.ruby.ST.miss_latency_hist_seqr::mean 2053.045235 +system.ruby.ST.miss_latency_hist_seqr::gmean 1585.445376 +system.ruby.ST.miss_latency_hist_seqr::stdev 1206.799639 +system.ruby.ST.miss_latency_hist_seqr | 58667 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 222835 system.ruby.Directory_Controller.Fetch 619101 0.00% 0.00% system.ruby.Directory_Controller.Data 222171 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 619097 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index 0bfb381db..903deb35a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -389,6 +390,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -412,6 +414,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -473,12 +476,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -528,6 +533,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -551,6 +557,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -612,12 +619,14 @@ slave=system.ruby.network.master[3] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -667,6 +676,7 @@ version=2 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -690,6 +700,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -751,12 +762,14 @@ slave=system.ruby.network.master[5] [system.ruby.l1_cntrl2.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl2.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -806,6 +819,7 @@ version=3 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -829,6 +843,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -890,12 +905,14 @@ slave=system.ruby.network.master[7] [system.ruby.l1_cntrl3.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl3.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -945,6 +962,7 @@ version=4 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -968,6 +986,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1029,12 +1048,14 @@ slave=system.ruby.network.master[9] [system.ruby.l1_cntrl4.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl4.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1084,6 +1105,7 @@ version=5 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1107,6 +1129,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1168,12 +1191,14 @@ slave=system.ruby.network.master[11] [system.ruby.l1_cntrl5.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl5.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1223,6 +1248,7 @@ version=6 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1246,6 +1272,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1307,12 +1334,14 @@ slave=system.ruby.network.master[13] [system.ruby.l1_cntrl6.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl6.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1362,6 +1391,7 @@ version=7 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1385,6 +1415,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1446,12 +1477,14 @@ slave=system.ruby.network.master[15] [system.ruby.l1_cntrl7.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl7.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1530,6 +1563,7 @@ slave=system.ruby.network.master[17] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -5051,6 +5085,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 27065a784..fd9d5cd32 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:10:49 -gem5 started Dec 11 2015 20:11:27 -gem5 executing on zizzer, pid 42472 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory +gem5 compiled Jan 21 2016 14:06:59 +gem5 started Jan 21 2016 14:07:35 +gem5 executing on zizzer, pid 50082 +command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 362b50c13..10214a209 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007437 # Nu sim_ticks 7436579 # Number of ticks simulated final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 35364 # Simulator tick rate (ticks/s) -host_mem_usage 396444 # Number of bytes of host memory used -host_seconds 210.29 # Real time elapsed on the host +host_tick_rate 32317 # Simulator tick rate (ticks/s) +host_mem_usage 403848 # Number of bytes of host memory used +host_seconds 230.12 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory @@ -303,37 +303,37 @@ system.cpu6.num_writes 55046 # nu system.cpu7.num_reads 99437 # number of read accesses completed system.cpu7.num_writes 55128 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 627422 -system.ruby.outstanding_req_hist::mean 15.998440 -system.ruby.outstanding_req_hist::gmean 15.997176 -system.ruby.outstanding_req_hist::stdev 0.125852 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 35 0.01% 0.02% | 627283 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 627422 -system.ruby.latency_hist::bucket_size 2048 -system.ruby.latency_hist::max_bucket 20479 -system.ruby.latency_hist::samples 627294 -system.ruby.latency_hist::mean 1517.095464 -system.ruby.latency_hist::gmean 959.020860 -system.ruby.latency_hist::stdev 1631.310093 -system.ruby.latency_hist | 473909 75.55% 75.55% | 104367 16.64% 92.19% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% -system.ruby.latency_hist::total 627294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 141 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 141 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 141 -system.ruby.miss_latency_hist::bucket_size 2048 -system.ruby.miss_latency_hist::max_bucket 20479 -system.ruby.miss_latency_hist::samples 627153 -system.ruby.miss_latency_hist::mean 1517.436321 -system.ruby.miss_latency_hist::gmean 960.502379 -system.ruby.miss_latency_hist::stdev 1631.335046 -system.ruby.miss_latency_hist | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% -system.ruby.miss_latency_hist::total 627153 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 627422 +system.ruby.outstanding_req_hist_seqr::mean 15.998440 +system.ruby.outstanding_req_hist_seqr::gmean 15.997176 +system.ruby.outstanding_req_hist_seqr::stdev 0.125852 +system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 35 0.01% 0.02% | 627283 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 627422 +system.ruby.latency_hist_seqr::bucket_size 2048 +system.ruby.latency_hist_seqr::max_bucket 20479 +system.ruby.latency_hist_seqr::samples 627294 +system.ruby.latency_hist_seqr::mean 1517.095464 +system.ruby.latency_hist_seqr::gmean 959.020860 +system.ruby.latency_hist_seqr::stdev 1631.310093 +system.ruby.latency_hist_seqr | 473909 75.55% 75.55% | 104367 16.64% 92.19% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.latency_hist_seqr::total 627294 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 141 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 141 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 141 +system.ruby.miss_latency_hist_seqr::bucket_size 2048 +system.ruby.miss_latency_hist_seqr::max_bucket 20479 +system.ruby.miss_latency_hist_seqr::samples 627153 +system.ruby.miss_latency_hist_seqr::mean 1517.436321 +system.ruby.miss_latency_hist_seqr::gmean 960.502379 +system.ruby.miss_latency_hist_seqr::stdev 1631.335046 +system.ruby.miss_latency_hist_seqr | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 627153 system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78254 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78276 # Number of cache demand accesses @@ -1047,52 +1047,52 @@ system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::1 492648 system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::2 15983640 system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1 1776032 system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2 4926328 -system.ruby.LD.latency_hist::bucket_size 2048 -system.ruby.LD.latency_hist::max_bucket 20479 -system.ruby.LD.latency_hist::samples 403304 -system.ruby.LD.latency_hist::mean 1518.773717 -system.ruby.LD.latency_hist::gmean 957.355041 -system.ruby.LD.latency_hist::stdev 1636.976329 -system.ruby.LD.latency_hist | 304613 75.53% 75.53% | 66895 16.59% 92.12% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% -system.ruby.LD.latency_hist::total 403304 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 106 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 106 -system.ruby.LD.miss_latency_hist::bucket_size 2048 -system.ruby.LD.miss_latency_hist::max_bucket 20479 -system.ruby.LD.miss_latency_hist::samples 403198 -system.ruby.LD.miss_latency_hist::mean 1519.172736 -system.ruby.LD.miss_latency_hist::gmean 959.084223 -system.ruby.LD.miss_latency_hist::stdev 1637.006477 -system.ruby.LD.miss_latency_hist | 304507 75.52% 75.52% | 66895 16.59% 92.11% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403198 -system.ruby.ST.latency_hist::bucket_size 2048 -system.ruby.ST.latency_hist::max_bucket 20479 -system.ruby.ST.latency_hist::samples 223990 -system.ruby.ST.latency_hist::mean 1514.073695 -system.ruby.ST.latency_hist::gmean 962.027552 -system.ruby.ST.latency_hist::stdev 1621.057112 -system.ruby.ST.latency_hist | 169296 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.25% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% -system.ruby.ST.latency_hist::total 223990 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 35 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 35 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 35 -system.ruby.ST.miss_latency_hist::bucket_size 2048 -system.ruby.ST.miss_latency_hist::max_bucket 20479 -system.ruby.ST.miss_latency_hist::samples 223955 -system.ruby.ST.miss_latency_hist::mean 1514.310161 -system.ruby.ST.miss_latency_hist::gmean 963.060847 -system.ruby.ST.miss_latency_hist::stdev 1621.073408 -system.ruby.ST.miss_latency_hist | 169261 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.26% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223955 +system.ruby.LD.latency_hist_seqr::bucket_size 2048 +system.ruby.LD.latency_hist_seqr::max_bucket 20479 +system.ruby.LD.latency_hist_seqr::samples 403304 +system.ruby.LD.latency_hist_seqr::mean 1518.773717 +system.ruby.LD.latency_hist_seqr::gmean 957.355041 +system.ruby.LD.latency_hist_seqr::stdev 1636.976329 +system.ruby.LD.latency_hist_seqr | 304613 75.53% 75.53% | 66895 16.59% 92.12% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 403304 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 106 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 106 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 2048 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 20479 +system.ruby.LD.miss_latency_hist_seqr::samples 403198 +system.ruby.LD.miss_latency_hist_seqr::mean 1519.172736 +system.ruby.LD.miss_latency_hist_seqr::gmean 959.084223 +system.ruby.LD.miss_latency_hist_seqr::stdev 1637.006477 +system.ruby.LD.miss_latency_hist_seqr | 304507 75.52% 75.52% | 66895 16.59% 92.11% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 403198 +system.ruby.ST.latency_hist_seqr::bucket_size 2048 +system.ruby.ST.latency_hist_seqr::max_bucket 20479 +system.ruby.ST.latency_hist_seqr::samples 223990 +system.ruby.ST.latency_hist_seqr::mean 1514.073695 +system.ruby.ST.latency_hist_seqr::gmean 962.027552 +system.ruby.ST.latency_hist_seqr::stdev 1621.057112 +system.ruby.ST.latency_hist_seqr | 169296 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.25% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 223990 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 35 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 35 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 35 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 2048 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 20479 +system.ruby.ST.miss_latency_hist_seqr::samples 223955 +system.ruby.ST.miss_latency_hist_seqr::mean 1514.310161 +system.ruby.ST.miss_latency_hist_seqr::gmean 963.060847 +system.ruby.ST.miss_latency_hist_seqr::stdev 1621.073408 +system.ruby.ST.miss_latency_hist_seqr | 169261 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.26% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 223955 system.ruby.Directory_Controller.GETX 222027 0.00% 0.00% system.ruby.Directory_Controller.GETS 393786 0.00% 0.00% system.ruby.Directory_Controller.PUTX 221899 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index 4fe1555ba..e15bb00e9 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -437,6 +438,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -460,6 +462,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -537,12 +540,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -593,6 +598,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -616,6 +622,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -693,12 +700,14 @@ slave=system.ruby.network.master[4] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -749,6 +758,7 @@ version=2 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -772,6 +782,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -849,12 +860,14 @@ slave=system.ruby.network.master[7] [system.ruby.l1_cntrl2.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl2.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -905,6 +918,7 @@ version=3 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -928,6 +942,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1005,12 +1020,14 @@ slave=system.ruby.network.master[10] [system.ruby.l1_cntrl3.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl3.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1061,6 +1078,7 @@ version=4 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1084,6 +1102,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1161,12 +1180,14 @@ slave=system.ruby.network.master[13] [system.ruby.l1_cntrl4.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl4.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1217,6 +1238,7 @@ version=5 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1240,6 +1262,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1317,12 +1340,14 @@ slave=system.ruby.network.master[16] [system.ruby.l1_cntrl5.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl5.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1373,6 +1398,7 @@ version=6 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1396,6 +1422,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1473,12 +1500,14 @@ slave=system.ruby.network.master[19] [system.ruby.l1_cntrl6.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl6.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1529,6 +1558,7 @@ version=7 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1552,6 +1582,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1629,12 +1660,14 @@ slave=system.ruby.network.master[22] [system.ruby.l1_cntrl7.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl7.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1708,6 +1741,7 @@ slave=system.ruby.network.master[25] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -8380,6 +8414,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index e5779a67d..1ed754ff1 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:15:50 -gem5 started Dec 11 2015 20:16:20 -gem5 executing on zizzer, pid 47643 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token +gem5 compiled Jan 21 2016 14:12:23 +gem5 started Jan 21 2016 14:12:59 +gem5 executing on zizzer, pid 55396 +command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 455b39cd6..8f87abafb 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.006099 # Nu sim_ticks 6099346 # Number of ticks simulated final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 38144 # Simulator tick rate (ticks/s) -host_mem_usage 397068 # Number of bytes of host memory used -host_seconds 159.90 # Real time elapsed on the host +host_tick_rate 34740 # Simulator tick rate (ticks/s) +host_mem_usage 404344 # Number of bytes of host memory used +host_seconds 175.57 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory @@ -307,40 +307,40 @@ system.cpu6.num_writes 55461 # nu system.cpu7.num_reads 99244 # number of read accesses completed system.cpu7.num_writes 55110 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626716 -system.ruby.outstanding_req_hist::mean 15.998460 -system.ruby.outstanding_req_hist::gmean 15.997196 -system.ruby.outstanding_req_hist::stdev 0.125834 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 626591 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626716 -system.ruby.latency_hist::bucket_size 512 -system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 626588 -system.ruby.latency_hist::mean 1245.772554 -system.ruby.latency_hist::gmean 1012.769806 -system.ruby.latency_hist::stdev 668.694211 -system.ruby.latency_hist | 107920 17.22% 17.22% | 148908 23.76% 40.99% | 141299 22.55% 63.54% | 142667 22.77% 86.31% | 76272 12.17% 98.48% | 9413 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626588 -system.ruby.hit_latency_hist::bucket_size 512 -system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 2961 -system.ruby.hit_latency_hist::mean 1105.733874 -system.ruby.hit_latency_hist::gmean 581.668757 -system.ruby.hit_latency_hist::stdev 707.726656 -system.ruby.hit_latency_hist | 739 24.96% 24.96% | 664 22.42% 47.38% | 645 21.78% 69.17% | 594 20.06% 89.23% | 287 9.69% 98.92% | 32 1.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2961 -system.ruby.miss_latency_hist::bucket_size 512 -system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 623627 -system.ruby.miss_latency_hist::mean 1246.437462 -system.ruby.miss_latency_hist::gmean 1015.439930 -system.ruby.miss_latency_hist::stdev 668.434071 -system.ruby.miss_latency_hist | 107181 17.19% 17.19% | 148244 23.77% 40.96% | 140654 22.55% 63.51% | 142073 22.78% 86.29% | 75985 12.18% 98.48% | 9381 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623627 -system.ruby.L1Cache.incomplete_times 2150 -system.ruby.Directory.incomplete_times 621474 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 626716 +system.ruby.outstanding_req_hist_seqr::mean 15.998460 +system.ruby.outstanding_req_hist_seqr::gmean 15.997196 +system.ruby.outstanding_req_hist_seqr::stdev 0.125834 +system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 626591 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 626716 +system.ruby.latency_hist_seqr::bucket_size 512 +system.ruby.latency_hist_seqr::max_bucket 5119 +system.ruby.latency_hist_seqr::samples 626588 +system.ruby.latency_hist_seqr::mean 1245.772554 +system.ruby.latency_hist_seqr::gmean 1012.769806 +system.ruby.latency_hist_seqr::stdev 668.694211 +system.ruby.latency_hist_seqr | 107920 17.22% 17.22% | 148908 23.76% 40.99% | 141299 22.55% 63.54% | 142667 22.77% 86.31% | 76272 12.17% 98.48% | 9413 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 626588 +system.ruby.hit_latency_hist_seqr::bucket_size 512 +system.ruby.hit_latency_hist_seqr::max_bucket 5119 +system.ruby.hit_latency_hist_seqr::samples 2961 +system.ruby.hit_latency_hist_seqr::mean 1105.733874 +system.ruby.hit_latency_hist_seqr::gmean 581.668757 +system.ruby.hit_latency_hist_seqr::stdev 707.726656 +system.ruby.hit_latency_hist_seqr | 739 24.96% 24.96% | 664 22.42% 47.38% | 645 21.78% 69.17% | 594 20.06% 89.23% | 287 9.69% 98.92% | 32 1.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 2961 +system.ruby.miss_latency_hist_seqr::bucket_size 512 +system.ruby.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.miss_latency_hist_seqr::samples 623627 +system.ruby.miss_latency_hist_seqr::mean 1246.437462 +system.ruby.miss_latency_hist_seqr::gmean 1015.439930 +system.ruby.miss_latency_hist_seqr::stdev 668.434071 +system.ruby.miss_latency_hist_seqr | 107181 17.19% 17.19% | 148244 23.77% 40.96% | 140654 22.55% 63.51% | 142073 22.78% 86.29% | 75985 12.18% 98.48% | 9381 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 623627 +system.ruby.L1Cache.incomplete_times_seqr 2150 +system.ruby.Directory.incomplete_times_seqr 621474 system.ruby.l1_cntrl0.L1Dcache.demand_hits 20 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 78435 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78455 # Number of cache demand accesses @@ -1058,170 +1058,170 @@ system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 21130200 system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 2544992 system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 2335664 -system.ruby.LD.latency_hist::bucket_size 512 -system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403224 -system.ruby.LD.latency_hist::mean 1244.872599 -system.ruby.LD.latency_hist::gmean 1012.118608 -system.ruby.LD.latency_hist::stdev 668.165886 -system.ruby.LD.latency_hist | 69390 17.21% 17.21% | 96033 23.82% 41.03% | 90972 22.56% 63.59% | 91905 22.79% 86.38% | 48739 12.09% 98.47% | 6121 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403224 -system.ruby.LD.hit_latency_hist::bucket_size 512 -system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 1892 -system.ruby.LD.hit_latency_hist::mean 1091.609408 -system.ruby.LD.hit_latency_hist::gmean 566.194555 -system.ruby.LD.hit_latency_hist::stdev 701.385932 -system.ruby.LD.hit_latency_hist | 479 25.32% 25.32% | 427 22.57% 47.89% | 425 22.46% 70.35% | 371 19.61% 89.96% | 172 9.09% 99.05% | 18 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1892 -system.ruby.LD.miss_latency_hist::bucket_size 512 -system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 401332 -system.ruby.LD.miss_latency_hist::mean 1245.595128 -system.ruby.LD.miss_latency_hist::gmean 1014.893956 -system.ruby.LD.miss_latency_hist::stdev 667.922999 -system.ruby.LD.miss_latency_hist | 68911 17.17% 17.17% | 95606 23.82% 40.99% | 90547 22.56% 63.55% | 91534 22.81% 86.36% | 48567 12.10% 98.46% | 6103 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401332 -system.ruby.ST.latency_hist::bucket_size 512 -system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223364 -system.ruby.ST.latency_hist::mean 1247.397181 -system.ruby.ST.latency_hist::gmean 1013.946431 -system.ruby.ST.latency_hist::stdev 669.645339 -system.ruby.ST.latency_hist | 38530 17.25% 17.25% | 52875 23.67% 40.92% | 50327 22.53% 63.45% | 50762 22.73% 86.18% | 27533 12.33% 98.51% | 3292 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223364 -system.ruby.ST.hit_latency_hist::bucket_size 512 -system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1069 -system.ruby.ST.hit_latency_hist::mean 1130.732460 -system.ruby.ST.hit_latency_hist::gmean 610.100104 -system.ruby.ST.hit_latency_hist::stdev 718.461557 -system.ruby.ST.hit_latency_hist | 260 24.32% 24.32% | 237 22.17% 46.49% | 220 20.58% 67.07% | 223 20.86% 87.93% | 115 10.76% 98.69% | 14 1.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1069 -system.ruby.ST.miss_latency_hist::bucket_size 512 -system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222295 -system.ruby.ST.miss_latency_hist::mean 1247.958213 -system.ruby.ST.miss_latency_hist::gmean 1016.426377 -system.ruby.ST.miss_latency_hist::stdev 669.354592 -system.ruby.ST.miss_latency_hist | 38270 17.22% 17.22% | 52638 23.68% 40.90% | 50107 22.54% 63.44% | 50539 22.74% 86.17% | 27418 12.33% 98.51% | 3278 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222295 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 198 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 198 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 198 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 2150 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1253.348372 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 981.859616 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 675.772818 -system.ruby.L1Cache.miss_mach_latency_hist | 390 18.14% 18.14% | 450 20.93% 39.07% | 525 24.42% 63.49% | 485 22.56% 86.05% | 255 11.86% 97.91% | 45 2.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 2150 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 2763 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1184.900471 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 917.900956 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 665.600614 -system.ruby.L2Cache.hit_mach_latency_hist | 541 19.58% 19.58% | 664 24.03% 43.61% | 645 23.34% 66.96% | 594 21.50% 88.45% | 287 10.39% 98.84% | 32 1.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 2763 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 621477 -system.ruby.Directory.miss_mach_latency_hist::mean 1246.413554 -system.ruby.Directory.miss_mach_latency_hist::gmean 1015.558072 -system.ruby.Directory.miss_mach_latency_hist::stdev 668.408968 -system.ruby.Directory.miss_mach_latency_hist | 106791 17.18% 17.18% | 147794 23.78% 40.96% | 140129 22.55% 63.51% | 141588 22.78% 86.29% | 75730 12.19% 98.48% | 9336 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 621477 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 3 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 3 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 3 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 3 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 3 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 3 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 88 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 87.863425 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 6 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 132 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 132 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 132 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 1339 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1280.535474 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1006.733527 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 680.945391 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 229 17.10% 17.10% | 276 20.61% 37.71% | 333 24.87% 62.58% | 304 22.70% 85.29% | 164 12.25% 97.54% | 33 2.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 1339 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1760 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1173.405114 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 910.831654 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 657.956416 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 347 19.72% 19.72% | 427 24.26% 43.98% | 425 24.15% 68.12% | 371 21.08% 89.20% | 172 9.77% 98.98% | 18 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1760 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 399993 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1245.478163 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1014.921384 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 667.876777 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 68682 17.17% 17.17% | 95330 23.83% 41.00% | 90214 22.55% 63.56% | 91230 22.81% 86.37% | 48403 12.10% 98.47% | 6070 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 399993 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 66 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 66 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 811 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1208.461159 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 942.129361 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 665.132497 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 161 19.85% 19.85% | 174 21.45% 41.31% | 192 23.67% 64.98% | 181 22.32% 87.30% | 91 11.22% 98.52% | 12 1.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 811 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 1003 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1205.071785 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 930.438584 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 678.666440 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 194 19.34% 19.34% | 237 23.63% 42.97% | 220 21.93% 64.91% | 223 22.23% 87.14% | 115 11.47% 98.60% | 14 1.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 1003 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221484 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1248.102838 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1016.708923 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.367212 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 38109 17.21% 17.21% | 52464 23.69% 40.89% | 49915 22.54% 63.43% | 50358 22.74% 86.17% | 27327 12.34% 98.51% | 3266 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221484 +system.ruby.LD.latency_hist_seqr::bucket_size 512 +system.ruby.LD.latency_hist_seqr::max_bucket 5119 +system.ruby.LD.latency_hist_seqr::samples 403224 +system.ruby.LD.latency_hist_seqr::mean 1244.872599 +system.ruby.LD.latency_hist_seqr::gmean 1012.118608 +system.ruby.LD.latency_hist_seqr::stdev 668.165886 +system.ruby.LD.latency_hist_seqr | 69390 17.21% 17.21% | 96033 23.82% 41.03% | 90972 22.56% 63.59% | 91905 22.79% 86.38% | 48739 12.09% 98.47% | 6121 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 403224 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 512 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.hit_latency_hist_seqr::samples 1892 +system.ruby.LD.hit_latency_hist_seqr::mean 1091.609408 +system.ruby.LD.hit_latency_hist_seqr::gmean 566.194555 +system.ruby.LD.hit_latency_hist_seqr::stdev 701.385932 +system.ruby.LD.hit_latency_hist_seqr | 479 25.32% 25.32% | 427 22.57% 47.89% | 425 22.46% 70.35% | 371 19.61% 89.96% | 172 9.09% 99.05% | 18 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 1892 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 512 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.miss_latency_hist_seqr::samples 401332 +system.ruby.LD.miss_latency_hist_seqr::mean 1245.595128 +system.ruby.LD.miss_latency_hist_seqr::gmean 1014.893956 +system.ruby.LD.miss_latency_hist_seqr::stdev 667.922999 +system.ruby.LD.miss_latency_hist_seqr | 68911 17.17% 17.17% | 95606 23.82% 40.99% | 90547 22.56% 63.55% | 91534 22.81% 86.36% | 48567 12.10% 98.46% | 6103 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 401332 +system.ruby.ST.latency_hist_seqr::bucket_size 512 +system.ruby.ST.latency_hist_seqr::max_bucket 5119 +system.ruby.ST.latency_hist_seqr::samples 223364 +system.ruby.ST.latency_hist_seqr::mean 1247.397181 +system.ruby.ST.latency_hist_seqr::gmean 1013.946431 +system.ruby.ST.latency_hist_seqr::stdev 669.645339 +system.ruby.ST.latency_hist_seqr | 38530 17.25% 17.25% | 52875 23.67% 40.92% | 50327 22.53% 63.45% | 50762 22.73% 86.18% | 27533 12.33% 98.51% | 3292 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 223364 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 512 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.hit_latency_hist_seqr::samples 1069 +system.ruby.ST.hit_latency_hist_seqr::mean 1130.732460 +system.ruby.ST.hit_latency_hist_seqr::gmean 610.100104 +system.ruby.ST.hit_latency_hist_seqr::stdev 718.461557 +system.ruby.ST.hit_latency_hist_seqr | 260 24.32% 24.32% | 237 22.17% 46.49% | 220 20.58% 67.07% | 223 20.86% 87.93% | 115 10.76% 98.69% | 14 1.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 1069 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.miss_latency_hist_seqr::samples 222295 +system.ruby.ST.miss_latency_hist_seqr::mean 1247.958213 +system.ruby.ST.miss_latency_hist_seqr::gmean 1016.426377 +system.ruby.ST.miss_latency_hist_seqr::stdev 669.354592 +system.ruby.ST.miss_latency_hist_seqr | 38270 17.22% 17.22% | 52638 23.68% 40.90% | 50107 22.54% 63.44% | 50539 22.74% 86.17% | 27418 12.33% 98.51% | 3278 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 222295 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 198 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 198 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 198 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 2150 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1253.348372 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 981.859616 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 675.772818 +system.ruby.L1Cache.miss_mach_latency_hist_seqr | 390 18.14% 18.14% | 450 20.93% 39.07% | 525 24.42% 63.49% | 485 22.56% 86.05% | 255 11.86% 97.91% | 45 2.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 2150 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 512 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 2763 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 1184.900471 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 917.900956 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 665.600614 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 541 19.58% 19.58% | 664 24.03% 43.61% | 645 23.34% 66.96% | 594 21.50% 88.45% | 287 10.39% 98.84% | 32 1.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 2763 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 621477 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 1246.413554 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 1015.558072 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 668.408968 +system.ruby.Directory.miss_mach_latency_hist_seqr | 106791 17.18% 17.18% | 147794 23.78% 40.96% | 140129 22.55% 63.51% | 141588 22.78% 86.29% | 75730 12.19% 98.48% | 9336 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 621477 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 3 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 3 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 3 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 88 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 87.863425 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 6 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 3 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 132 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 132 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 132 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 1339 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 1280.535474 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1006.733527 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 680.945391 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 229 17.10% 17.10% | 276 20.61% 37.71% | 333 24.87% 62.58% | 304 22.70% 85.29% | 164 12.25% 97.54% | 33 2.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 1339 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 1760 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 1173.405114 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 910.831654 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 657.956416 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 347 19.72% 19.72% | 427 24.26% 43.98% | 425 24.15% 68.12% | 371 21.08% 89.20% | 172 9.77% 98.98% | 18 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 1760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 399993 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1245.478163 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 1014.921384 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 667.876777 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 68682 17.17% 17.17% | 95330 23.83% 41.00% | 90214 22.55% 63.56% | 91230 22.81% 86.37% | 48403 12.10% 98.47% | 6070 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 399993 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 66 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 66 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 811 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1208.461159 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 942.129361 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 665.132497 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 161 19.85% 19.85% | 174 21.45% 41.31% | 192 23.67% 64.98% | 181 22.32% 87.30% | 91 11.22% 98.52% | 12 1.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 811 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 1003 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 1205.071785 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 930.438584 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 678.666440 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 194 19.34% 19.34% | 237 23.63% 42.97% | 220 21.93% 64.91% | 223 22.23% 87.14% | 115 11.47% 98.60% | 14 1.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 1003 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 221484 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1248.102838 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 1016.708923 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 669.367212 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 38109 17.21% 17.21% | 52464 23.69% 40.89% | 49915 22.54% 63.43% | 50358 22.74% 86.17% | 27327 12.34% 98.51% | 3266 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 221484 system.ruby.Directory_Controller.GETX 240452 0.00% 0.00% system.ruby.Directory_Controller.GETS 432599 0.00% 0.00% system.ruby.Directory_Controller.Lockdown 146609 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 5583f0918..2292d0c6a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -354,6 +355,7 @@ master=system.ruby.network.slave[24] type=RubyCache children=replacement_policy assoc=4 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -453,6 +455,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -476,6 +479,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -499,6 +503,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -560,12 +565,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -626,6 +633,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -649,6 +657,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -672,6 +681,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -733,12 +743,14 @@ slave=system.ruby.network.master[3] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -799,6 +811,7 @@ version=2 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -822,6 +835,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -845,6 +859,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -906,12 +921,14 @@ slave=system.ruby.network.master[5] [system.ruby.l1_cntrl2.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl2.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl2.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -972,6 +989,7 @@ version=3 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -995,6 +1013,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1018,6 +1037,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1079,12 +1099,14 @@ slave=system.ruby.network.master[7] [system.ruby.l1_cntrl3.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl3.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl3.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1145,6 +1167,7 @@ version=4 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1168,6 +1191,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1191,6 +1215,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1252,12 +1277,14 @@ slave=system.ruby.network.master[9] [system.ruby.l1_cntrl4.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl4.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl4.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1318,6 +1345,7 @@ version=5 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1341,6 +1369,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1364,6 +1393,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1425,12 +1455,14 @@ slave=system.ruby.network.master[11] [system.ruby.l1_cntrl5.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl5.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl5.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1491,6 +1523,7 @@ version=6 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1514,6 +1547,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1537,6 +1571,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1598,12 +1633,14 @@ slave=system.ruby.network.master[13] [system.ruby.l1_cntrl6.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl6.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl6.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1664,6 +1701,7 @@ version=7 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1687,6 +1725,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1710,6 +1749,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1771,12 +1811,14 @@ slave=system.ruby.network.master[15] [system.ruby.l1_cntrl7.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl7.L1Dcache dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl7.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -7395,6 +7437,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 823860a85..a1cb70e56 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:00:36 -gem5 started Dec 11 2015 20:01:07 -gem5 executing on zizzer, pid 31717 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer +gem5 compiled Jan 21 2016 13:56:08 +gem5 started Jan 21 2016 13:56:42 +gem5 executing on zizzer, pid 39366 +command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 0e775479f..760ab889a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu sim_ticks 4722948 # Number of ticks simulated final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 25861 # Simulator tick rate (ticks/s) -host_mem_usage 397392 # Number of bytes of host memory used -host_seconds 182.63 # Real time elapsed on the host +host_tick_rate 22839 # Simulator tick rate (ticks/s) +host_mem_usage 403984 # Number of bytes of host memory used +host_seconds 206.79 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory @@ -292,40 +292,40 @@ system.cpu6.num_writes 55532 # nu system.cpu7.num_reads 99124 # number of read accesses completed system.cpu7.num_writes 55205 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 630039 -system.ruby.outstanding_req_hist::mean 15.998449 -system.ruby.outstanding_req_hist::gmean 15.997191 -system.ruby.outstanding_req_hist::stdev 0.125577 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 33 0.01% 0.02% | 629902 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 630039 -system.ruby.latency_hist::bucket_size 512 -system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 629911 -system.ruby.latency_hist::mean 959.551335 -system.ruby.latency_hist::gmean 653.122123 -system.ruby.latency_hist::stdev 680.118422 -system.ruby.latency_hist | 216304 34.34% 34.34% | 132336 21.01% 55.35% | 131857 20.93% 76.28% | 106965 16.98% 93.26% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 629911 -system.ruby.hit_latency_hist::bucket_size 128 -system.ruby.hit_latency_hist::max_bucket 1279 -system.ruby.hit_latency_hist::samples 662 -system.ruby.hit_latency_hist::mean 64.490937 -system.ruby.hit_latency_hist::gmean 13.604512 -system.ruby.hit_latency_hist::stdev 143.889590 -system.ruby.hit_latency_hist | 564 85.20% 85.20% | 45 6.80% 91.99% | 27 4.08% 96.07% | 10 1.51% 97.58% | 5 0.76% 98.34% | 4 0.60% 98.94% | 4 0.60% 99.55% | 2 0.30% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% -system.ruby.hit_latency_hist::total 662 -system.ruby.miss_latency_hist::bucket_size 512 -system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 629249 -system.ruby.miss_latency_hist::mean 960.492981 -system.ruby.miss_latency_hist::gmean 655.787621 -system.ruby.miss_latency_hist::stdev 679.839862 -system.ruby.miss_latency_hist | 215658 34.27% 34.27% | 132321 21.03% 55.30% | 131856 20.95% 76.26% | 106965 17.00% 93.25% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 629249 -system.ruby.L1Cache.incomplete_times 962 -system.ruby.Directory.incomplete_times 176578 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 630039 +system.ruby.outstanding_req_hist_seqr::mean 15.998449 +system.ruby.outstanding_req_hist_seqr::gmean 15.997191 +system.ruby.outstanding_req_hist_seqr::stdev 0.125577 +system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 33 0.01% 0.02% | 629902 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 630039 +system.ruby.latency_hist_seqr::bucket_size 512 +system.ruby.latency_hist_seqr::max_bucket 5119 +system.ruby.latency_hist_seqr::samples 629911 +system.ruby.latency_hist_seqr::mean 959.551335 +system.ruby.latency_hist_seqr::gmean 653.122123 +system.ruby.latency_hist_seqr::stdev 680.118422 +system.ruby.latency_hist_seqr | 216304 34.34% 34.34% | 132336 21.01% 55.35% | 131857 20.93% 76.28% | 106965 16.98% 93.26% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 629911 +system.ruby.hit_latency_hist_seqr::bucket_size 128 +system.ruby.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.hit_latency_hist_seqr::samples 662 +system.ruby.hit_latency_hist_seqr::mean 64.490937 +system.ruby.hit_latency_hist_seqr::gmean 13.604512 +system.ruby.hit_latency_hist_seqr::stdev 143.889590 +system.ruby.hit_latency_hist_seqr | 564 85.20% 85.20% | 45 6.80% 91.99% | 27 4.08% 96.07% | 10 1.51% 97.58% | 5 0.76% 98.34% | 4 0.60% 98.94% | 4 0.60% 99.55% | 2 0.30% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% +system.ruby.hit_latency_hist_seqr::total 662 +system.ruby.miss_latency_hist_seqr::bucket_size 512 +system.ruby.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.miss_latency_hist_seqr::samples 629249 +system.ruby.miss_latency_hist_seqr::mean 960.492981 +system.ruby.miss_latency_hist_seqr::gmean 655.787621 +system.ruby.miss_latency_hist_seqr::stdev 679.839862 +system.ruby.miss_latency_hist_seqr | 215658 34.27% 34.27% | 132321 21.03% 55.30% | 131856 20.95% 76.26% | 106965 17.00% 93.25% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 629249 +system.ruby.L1Cache.incomplete_times_seqr 962 +system.ruby.Directory.incomplete_times_seqr 176578 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -959,209 +959,209 @@ system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15897960 system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4748376 system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2970224 system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5045576 -system.ruby.LD.latency_hist::bucket_size 512 -system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 406290 -system.ruby.LD.latency_hist::mean 960.374656 -system.ruby.LD.latency_hist::gmean 653.723269 -system.ruby.LD.latency_hist::stdev 680.173118 -system.ruby.LD.latency_hist | 139274 34.28% 34.28% | 85290 20.99% 55.27% | 85200 20.97% 76.24% | 69101 17.01% 93.25% | 24962 6.14% 99.39% | 2420 0.60% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 406290 -system.ruby.LD.hit_latency_hist::bucket_size 128 -system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 444 -system.ruby.LD.hit_latency_hist::mean 62.301802 -system.ruby.LD.hit_latency_hist::gmean 13.718667 -system.ruby.LD.hit_latency_hist::stdev 132.474944 -system.ruby.LD.hit_latency_hist | 374 84.23% 84.23% | 34 7.66% 91.89% | 20 4.50% 96.40% | 8 1.80% 98.20% | 5 1.13% 99.32% | 1 0.23% 99.55% | 1 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% -system.ruby.LD.hit_latency_hist::total 444 -system.ruby.LD.miss_latency_hist::bucket_size 512 -system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 405846 -system.ruby.LD.miss_latency_hist::mean 961.357158 -system.ruby.LD.miss_latency_hist::gmean 656.492523 -system.ruby.LD.miss_latency_hist::stdev 679.881694 -system.ruby.LD.miss_latency_hist | 138838 34.21% 34.21% | 85283 21.01% 55.22% | 85199 20.99% 76.22% | 69101 17.03% 93.24% | 24962 6.15% 99.39% | 2420 0.60% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 405846 -system.ruby.ST.latency_hist::bucket_size 512 -system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223621 -system.ruby.ST.latency_hist::mean 958.055469 -system.ruby.ST.latency_hist::gmean 652.031334 -system.ruby.ST.latency_hist::stdev 680.018005 -system.ruby.ST.latency_hist | 77030 34.45% 34.45% | 47046 21.04% 55.48% | 46657 20.86% 76.35% | 37864 16.93% 93.28% | 13697 6.13% 99.41% | 1304 0.58% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223621 -system.ruby.ST.hit_latency_hist::bucket_size 128 -system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 218 -system.ruby.ST.hit_latency_hist::mean 68.949541 -system.ruby.ST.hit_latency_hist::gmean 13.374942 -system.ruby.ST.hit_latency_hist::stdev 164.954210 -system.ruby.ST.hit_latency_hist | 190 87.16% 87.16% | 11 5.05% 92.20% | 7 3.21% 95.41% | 2 0.92% 96.33% | 0 0.00% 96.33% | 3 1.38% 97.71% | 3 1.38% 99.08% | 2 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 218 -system.ruby.ST.miss_latency_hist::bucket_size 512 -system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 223403 -system.ruby.ST.miss_latency_hist::mean 958.923072 -system.ruby.ST.miss_latency_hist::gmean 654.508995 -system.ruby.ST.miss_latency_hist::stdev 679.762571 -system.ruby.ST.miss_latency_hist | 76820 34.39% 34.39% | 47038 21.06% 55.44% | 46657 20.88% 76.33% | 37864 16.95% 93.27% | 13697 6.13% 99.41% | 1304 0.58% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223403 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 126 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 126 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 126 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 22929 -system.ruby.L1Cache.miss_mach_latency_hist::mean 917.294474 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 599.636042 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 676.350403 -system.ruby.L1Cache.miss_mach_latency_hist | 8471 36.94% 36.94% | 4760 20.76% 57.70% | 4639 20.23% 77.94% | 3735 16.29% 94.23% | 1218 5.31% 99.54% | 105 0.46% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 22929 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 21967 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 769.291483 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 161.408765 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 672.554554 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 9332 42.48% 42.48% | 4595 20.92% 63.40% | 4421 20.13% 83.53% | 2933 13.35% 96.88% | 655 2.98% 99.86% | 31 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 21967 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 21967 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.655074 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.745857 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 75.819936 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19070 86.81% 86.81% | 2265 10.31% 97.12% | 517 2.35% 99.48% | 68 0.31% 99.79% | 39 0.18% 99.96% | 8 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 21967 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size 32 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 21967 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 86.871580 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 72.228308 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.302472 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3616 16.46% 16.46% | 4690 21.35% 37.81% | 5205 23.69% 61.51% | 3592 16.35% 77.86% | 2696 12.27% 90.13% | 1595 7.26% 97.39% | 528 2.40% 99.80% | 42 0.19% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 21967 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 32 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 21967 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 9.646606 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.383574 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 20003 91.06% 91.06% | 858 3.91% 94.97% | 665 3.03% 97.99% | 325 1.48% 99.47% | 99 0.45% 99.92% | 15 0.07% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 21967 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279 -system.ruby.L2Cache.hit_mach_latency_hist::samples 536 -system.ruby.L2Cache.hit_mach_latency_hist::mean 79.416045 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 25.129455 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 156.229930 -system.ruby.L2Cache.hit_mach_latency_hist | 438 81.72% 81.72% | 45 8.40% 90.11% | 27 5.04% 95.15% | 10 1.87% 97.01% | 5 0.93% 97.95% | 4 0.75% 98.69% | 4 0.75% 99.44% | 2 0.37% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 536 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 606320 -system.ruby.Directory.miss_mach_latency_hist::mean 962.126605 -system.ruby.Directory.miss_mach_latency_hist::gmean 658.011306 -system.ruby.Directory.miss_mach_latency_hist::stdev 679.918169 -system.ruby.Directory.miss_mach_latency_hist | 207187 34.17% 34.17% | 127561 21.04% 55.21% | 127217 20.98% 76.19% | 103230 17.03% 93.22% | 37441 6.18% 99.39% | 3619 0.60% 99.99% | 65 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 606320 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 429742 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 784.153017 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 182.710086 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 666.397335 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 178531 41.54% 41.54% | 92185 21.45% 63.00% | 88049 20.49% 83.48% | 57641 13.41% 96.90% | 12707 2.96% 99.85% | 623 0.14% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 429742 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 64 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 639 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 429742 -system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.305988 -system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.466522 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 20.935609 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 399534 92.97% 92.97% | 29865 6.95% 99.92% | 276 0.06% 99.98% | 52 0.01% 100.00% | 9 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 429742 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 32 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 429742 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 62.043489 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 53.541478 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 33.955511 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 102053 23.75% 23.75% | 148225 34.49% 58.24% | 106521 24.79% 83.03% | 50471 11.74% 94.77% | 18432 4.29% 99.06% | 3871 0.90% 99.96% | 168 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 429742 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 128 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 1279 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 429742 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 141.234122 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 102.647241 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 226604 52.73% 52.73% | 153344 35.68% 88.41% | 35970 8.37% 96.78% | 9098 2.12% 98.90% | 4598 1.07% 99.97% | 128 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 429742 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 83 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 83 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 83 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13098 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 918.714613 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 600.249224 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 672.644684 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 4798 36.63% 36.63% | 2729 20.84% 57.47% | 2722 20.78% 78.25% | 2123 16.21% 94.46% | 664 5.07% 99.53% | 61 0.47% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13098 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 361 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 76.396122 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 25.049504 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 143.283503 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 291 80.61% 80.61% | 34 9.42% 90.03% | 20 5.54% 95.57% | 8 2.22% 97.78% | 5 1.39% 99.17% | 1 0.28% 99.45% | 1 0.28% 99.72% | 0 0.00% 99.72% | 0 0.00% 99.72% | 1 0.28% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 361 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 392748 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 962.779271 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 658.456401 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 680.076496 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 134040 34.13% 34.13% | 82554 21.02% 55.15% | 82477 21.00% 76.15% | 66978 17.05% 93.20% | 24298 6.19% 99.39% | 2359 0.60% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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1.71% 97.14% | 3 1.71% 98.86% | 2 1.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 175 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213572 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 960.926385 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 657.193585 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 679.626872 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 73147 34.25% 34.25% | 45007 21.07% 55.32% | 44740 20.95% 76.27% | 36252 16.97% 93.25% | 13143 6.15% 99.40% | 1260 0.59% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213572 +system.ruby.LD.latency_hist_seqr::bucket_size 512 +system.ruby.LD.latency_hist_seqr::max_bucket 5119 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0.00% 99.77% | 1 0.23% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 444 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 512 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.miss_latency_hist_seqr::samples 405846 +system.ruby.LD.miss_latency_hist_seqr::mean 961.357158 +system.ruby.LD.miss_latency_hist_seqr::gmean 656.492523 +system.ruby.LD.miss_latency_hist_seqr::stdev 679.881694 +system.ruby.LD.miss_latency_hist_seqr | 138838 34.21% 34.21% | 85283 21.01% 55.22% | 85199 20.99% 76.22% | 69101 17.03% 93.24% | 24962 6.15% 99.39% | 2420 0.60% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 405846 +system.ruby.ST.latency_hist_seqr::bucket_size 512 +system.ruby.ST.latency_hist_seqr::max_bucket 5119 +system.ruby.ST.latency_hist_seqr::samples 223621 +system.ruby.ST.latency_hist_seqr::mean 958.055469 +system.ruby.ST.latency_hist_seqr::gmean 652.031334 +system.ruby.ST.latency_hist_seqr::stdev 680.018005 +system.ruby.ST.latency_hist_seqr | 77030 34.45% 34.45% | 47046 21.04% 55.48% | 46657 20.86% 76.35% | 37864 16.93% 93.28% | 13697 6.13% 99.41% | 1304 0.58% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 223621 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.hit_latency_hist_seqr::samples 218 +system.ruby.ST.hit_latency_hist_seqr::mean 68.949541 +system.ruby.ST.hit_latency_hist_seqr::gmean 13.374942 +system.ruby.ST.hit_latency_hist_seqr::stdev 164.954210 +system.ruby.ST.hit_latency_hist_seqr | 190 87.16% 87.16% | 11 5.05% 92.20% | 7 3.21% 95.41% | 2 0.92% 96.33% | 0 0.00% 96.33% | 3 1.38% 97.71% | 3 1.38% 99.08% | 2 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 218 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 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0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 126 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 22929 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 917.294474 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 599.636042 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 676.350403 +system.ruby.L1Cache.miss_mach_latency_hist_seqr | 8471 36.94% 36.94% | 4760 20.76% 57.70% | 4639 20.23% 77.94% | 3735 16.29% 94.23% | 1218 5.31% 99.54% | 105 0.46% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 22929 +system.ruby.L1Cache.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 512 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+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 429742 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::mean 784.153017 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::gmean 182.710086 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev 666.397335 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 178531 41.54% 41.54% | 92185 21.45% 63.00% | 88049 20.49% 83.48% | 57641 13.41% 96.90% | 12707 2.96% 99.85% | 623 0.14% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 429742 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 64 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 639 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 429742 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::mean 18.305988 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::gmean 12.466522 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev 20.935609 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 399534 92.97% 92.97% | 29865 6.95% 99.92% | 276 0.06% 99.98% | 52 0.01% 100.00% | 9 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 429742 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 32 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 319 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 429742 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 62.043489 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 53.541478 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev 33.955511 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 102053 23.75% 23.75% | 148225 34.49% 58.24% | 106521 24.79% 83.03% | 50471 11.74% 94.77% | 18432 4.29% 99.06% | 3871 0.90% 99.96% | 168 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 429742 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 128 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 1279 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 429742 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 141.234122 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 102.647241 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 226604 52.73% 52.73% | 153344 35.68% 88.41% | 35970 8.37% 96.78% | 9098 2.12% 98.90% | 4598 1.07% 99.97% | 128 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 429742 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 83 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 83 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 13098 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 918.714613 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 600.249224 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 672.644684 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 4798 36.63% 36.63% | 2729 20.84% 57.47% | 2722 20.78% 78.25% | 2123 16.21% 94.46% | 664 5.07% 99.53% | 61 0.47% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 13098 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 361 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 76.396122 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 25.049504 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 143.283503 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 291 80.61% 80.61% | 34 9.42% 90.03% | 20 5.54% 95.57% | 8 2.22% 97.78% | 5 1.39% 99.17% | 1 0.28% 99.45% | 1 0.28% 99.72% | 0 0.00% 99.72% | 0 0.00% 99.72% | 1 0.28% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 361 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 392748 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 962.779271 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 658.456401 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 680.076496 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 134040 34.13% 34.13% | 82554 21.02% 55.15% | 82477 21.00% 76.15% | 66978 17.05% 93.20% | 24298 6.19% 99.39% | 2359 0.60% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 392748 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 43 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 43 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 43 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 9831 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 915.402401 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 598.820063 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 681.285952 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3673 37.36% 37.36% | 2031 20.66% 58.02% | 1917 19.50% 77.52% | 1612 16.40% 93.92% | 554 5.64% 99.55% | 44 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 9831 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 175 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 85.645714 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 25.295189 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 180.313043 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 147 84.00% 84.00% | 11 6.29% 90.29% | 7 4.00% 94.29% | 2 1.14% 95.43% | 0 0.00% 95.43% | 3 1.71% 97.14% | 3 1.71% 98.86% | 2 1.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 175 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 213572 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 960.926385 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 657.193585 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 679.626872 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73147 34.25% 34.25% | 45007 21.07% 55.32% | 44740 20.95% 76.27% | 36252 16.97% 93.25% | 13143 6.15% 99.40% | 1260 0.59% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 213572 system.ruby.Directory_Controller.GETX 227359 0.00% 0.00% system.ruby.Directory_Controller.GETS 412013 0.00% 0.00% system.ruby.Directory_Controller.PUT 607708 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index 76624d8ec..8fe2e9afa 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -395,6 +396,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -456,12 +458,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -501,6 +505,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -562,12 +567,14 @@ slave=system.ruby.network.master[3] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl1.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -607,6 +614,7 @@ version=2 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -668,12 +676,14 @@ slave=system.ruby.network.master[5] [system.ruby.l1_cntrl2.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl2.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl2.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -713,6 +723,7 @@ version=3 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -774,12 +785,14 @@ slave=system.ruby.network.master[7] [system.ruby.l1_cntrl3.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl3.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl3.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -819,6 +832,7 @@ version=4 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -880,12 +894,14 @@ slave=system.ruby.network.master[9] [system.ruby.l1_cntrl4.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl4.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl4.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -925,6 +941,7 @@ version=5 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -986,12 +1003,14 @@ slave=system.ruby.network.master[11] [system.ruby.l1_cntrl5.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl5.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl5.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1031,6 +1050,7 @@ version=6 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1092,12 +1112,14 @@ slave=system.ruby.network.master[13] [system.ruby.l1_cntrl6.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl6.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl6.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1137,6 +1159,7 @@ version=7 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1198,12 +1221,14 @@ slave=system.ruby.network.master[15] [system.ruby.l1_cntrl7.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl7.cacheMemory dcache_hit_latency=1 deadlock_threshold=1000000 eventq_index=0 icache=system.ruby.l1_cntrl7.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -5925,6 +5950,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 3922932b4..00118fafb 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:41 -gem5 executing on zizzer, pid 26230 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:03 +gem5 executing on zizzer, pid 34009 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index eec812c12..edf017693 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu sim_ticks 7678882 # Number of ticks simulated final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 64715 # Simulator tick rate (ticks/s) -host_mem_usage 392924 # Number of bytes of host memory used -host_seconds 118.66 # Real time elapsed on the host +host_tick_rate 60394 # Simulator tick rate (ticks/s) +host_mem_usage 401808 # Number of bytes of host memory used +host_seconds 127.15 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory @@ -290,32 +290,32 @@ system.ruby.delayHist::mean 2.261395 # de system.ruby.delayHist::stdev 7.584807 # delay histogram for all message system.ruby.delayHist | 1243450 98.62% 98.62% | 11474 0.91% 99.53% | 5225 0.41% 99.95% | 542 0.04% 99.99% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 1260795 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628584 -system.ruby.outstanding_req_hist::mean 15.998449 -system.ruby.outstanding_req_hist::gmean 15.997188 -system.ruby.outstanding_req_hist::stdev 0.125710 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 628449 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628584 -system.ruby.latency_hist::bucket_size 512 -system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 628456 -system.ruby.latency_hist::mean 1563.811233 -system.ruby.latency_hist::gmean 1541.792365 -system.ruby.latency_hist::stdev 262.265559 -system.ruby.latency_hist | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 628456 -system.ruby.miss_latency_hist::bucket_size 512 -system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 628456 -system.ruby.miss_latency_hist::mean 1563.811233 -system.ruby.miss_latency_hist::gmean 1541.792365 -system.ruby.miss_latency_hist::stdev 262.265559 -system.ruby.miss_latency_hist | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 628456 -system.ruby.L1Cache.incomplete_times 8337 -system.ruby.Directory.incomplete_times 620116 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 628584 +system.ruby.outstanding_req_hist_seqr::mean 15.998449 +system.ruby.outstanding_req_hist_seqr::gmean 15.997188 +system.ruby.outstanding_req_hist_seqr::stdev 0.125710 +system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 628449 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 628584 +system.ruby.latency_hist_seqr::bucket_size 512 +system.ruby.latency_hist_seqr::max_bucket 5119 +system.ruby.latency_hist_seqr::samples 628456 +system.ruby.latency_hist_seqr::mean 1563.811233 +system.ruby.latency_hist_seqr::gmean 1541.792365 +system.ruby.latency_hist_seqr::stdev 262.265559 +system.ruby.latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 628456 +system.ruby.miss_latency_hist_seqr::bucket_size 512 +system.ruby.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.miss_latency_hist_seqr::samples 628456 +system.ruby.miss_latency_hist_seqr::mean 1563.811233 +system.ruby.miss_latency_hist_seqr::gmean 1541.792365 +system.ruby.miss_latency_hist_seqr::stdev 262.265559 +system.ruby.miss_latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 628456 +system.ruby.L1Cache.incomplete_times_seqr 8337 +system.ruby.Directory.incomplete_times_seqr 620116 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses @@ -604,109 +604,109 @@ system.ruby.delayVCHist.vnet_2::mean 4.240058 # de system.ruby.delayVCHist.vnet_2::stdev 10.251834 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 614994 97.26% 97.26% | 11474 1.81% 99.07% | 5225 0.83% 99.90% | 542 0.09% 99.98% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 632339 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 512 -system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 404420 -system.ruby.LD.latency_hist::mean 1563.542728 -system.ruby.LD.latency_hist::gmean 1541.515221 -system.ruby.LD.latency_hist::stdev 262.248075 -system.ruby.LD.latency_hist | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 404420 -system.ruby.LD.miss_latency_hist::bucket_size 512 -system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 404420 -system.ruby.LD.miss_latency_hist::mean 1563.542728 -system.ruby.LD.miss_latency_hist::gmean 1541.515221 -system.ruby.LD.miss_latency_hist::stdev 262.248075 -system.ruby.LD.miss_latency_hist | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 404420 -system.ruby.ST.latency_hist::bucket_size 512 -system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 224036 -system.ruby.ST.latency_hist::mean 1564.295926 -system.ruby.ST.latency_hist::gmean 1542.292779 -system.ruby.ST.latency_hist::stdev 262.297007 -system.ruby.ST.latency_hist | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 224036 -system.ruby.ST.miss_latency_hist::bucket_size 512 -system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 224036 -system.ruby.ST.miss_latency_hist::mean 1564.295926 -system.ruby.ST.miss_latency_hist::gmean 1542.292779 -system.ruby.ST.miss_latency_hist::stdev 262.297007 -system.ruby.ST.miss_latency_hist | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 224036 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8337 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1457.519731 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1434.160972 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 261.316891 -system.ruby.L1Cache.miss_mach_latency_hist | 1 0.01% 0.01% | 260 3.12% 3.13% | 5041 60.47% 63.60% | 2865 34.36% 97.96% | 168 2.02% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8337 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 620119 -system.ruby.Directory.miss_mach_latency_hist::mean 1565.240236 -system.ruby.Directory.miss_mach_latency_hist::gmean 1543.293101 -system.ruby.Directory.miss_mach_latency_hist::stdev 261.984881 -system.ruby.Directory.miss_mach_latency_hist | 76 0.01% 0.01% | 5844 0.94% 0.95% | 293021 47.25% 48.21% | 294571 47.50% 95.71% | 26418 4.26% 99.97% | 189 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 620119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 3 -system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 3 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 3 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 3 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 3 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 3 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 80 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 79.895697 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 5 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5455 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1456.778185 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1433.055554 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 263.122030 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 1 0.02% 0.02% | 6 0.11% 0.13% | 171 3.13% 3.26% | 1270 23.28% 26.54% | 2035 37.31% 63.85% | 1383 25.35% 89.20% | 473 8.67% 97.87% | 103 1.89% 99.76% | 13 0.24% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5455 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398965 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1565.002506 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1543.053698 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 261.935038 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 48 0.01% 0.01% | 3704 0.93% 0.94% | 188763 47.31% 48.25% | 189451 47.49% 95.74% | 16872 4.23% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398965 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2882 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1458.923317 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1436.255624 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 257.905109 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 83 2.88% 2.88% | 1736 60.24% 63.12% | 1009 35.01% 98.13% | 52 1.80% 99.93% | 2 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2882 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221154 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1565.669104 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1543.725080 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 262.074821 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 28 0.01% 0.01% | 2140 0.97% 0.98% | 104258 47.14% 48.12% | 105120 47.53% 95.66% | 9546 4.32% 99.97% | 62 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221154 +system.ruby.LD.latency_hist_seqr::bucket_size 512 +system.ruby.LD.latency_hist_seqr::max_bucket 5119 +system.ruby.LD.latency_hist_seqr::samples 404420 +system.ruby.LD.latency_hist_seqr::mean 1563.542728 +system.ruby.LD.latency_hist_seqr::gmean 1541.515221 +system.ruby.LD.latency_hist_seqr::stdev 262.248075 +system.ruby.LD.latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 404420 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 512 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.miss_latency_hist_seqr::samples 404420 +system.ruby.LD.miss_latency_hist_seqr::mean 1563.542728 +system.ruby.LD.miss_latency_hist_seqr::gmean 1541.515221 +system.ruby.LD.miss_latency_hist_seqr::stdev 262.248075 +system.ruby.LD.miss_latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 404420 +system.ruby.ST.latency_hist_seqr::bucket_size 512 +system.ruby.ST.latency_hist_seqr::max_bucket 5119 +system.ruby.ST.latency_hist_seqr::samples 224036 +system.ruby.ST.latency_hist_seqr::mean 1564.295926 +system.ruby.ST.latency_hist_seqr::gmean 1542.292779 +system.ruby.ST.latency_hist_seqr::stdev 262.297007 +system.ruby.ST.latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 224036 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.miss_latency_hist_seqr::samples 224036 +system.ruby.ST.miss_latency_hist_seqr::mean 1564.295926 +system.ruby.ST.miss_latency_hist_seqr::gmean 1542.292779 +system.ruby.ST.miss_latency_hist_seqr::stdev 262.297007 +system.ruby.ST.miss_latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 224036 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 8337 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1457.519731 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 1434.160972 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 261.316891 +system.ruby.L1Cache.miss_mach_latency_hist_seqr | 1 0.01% 0.01% | 260 3.12% 3.13% | 5041 60.47% 63.60% | 2865 34.36% 97.96% | 168 2.02% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 8337 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 620119 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 1565.240236 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 1543.293101 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 261.984881 +system.ruby.Directory.miss_mach_latency_hist_seqr | 76 0.01% 0.01% | 5844 0.94% 0.95% | 293021 47.25% 48.21% | 294571 47.50% 95.71% | 26418 4.26% 99.97% | 189 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 620119 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 3 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 3 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 3 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 3 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 80 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 79.895697 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 5 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 3 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 256 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 2559 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 5455 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 1456.778185 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1433.055554 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 263.122030 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 1 0.02% 0.02% | 6 0.11% 0.13% | 171 3.13% 3.26% | 1270 23.28% 26.54% | 2035 37.31% 63.85% | 1383 25.35% 89.20% | 473 8.67% 97.87% | 103 1.89% 99.76% | 13 0.24% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 5455 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 398965 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1565.002506 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.053698 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 261.935038 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 48 0.01% 0.01% | 3704 0.93% 0.94% | 188763 47.31% 48.25% | 189451 47.49% 95.74% | 16872 4.23% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 398965 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 2882 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1458.923317 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1436.255624 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 257.905109 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 2.88% 2.88% | 1736 60.24% 63.12% | 1009 35.01% 98.13% | 52 1.80% 99.93% | 2 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 2882 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 221154 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1565.669104 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.725080 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 262.074821 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 28 0.01% 0.01% | 2140 0.97% 0.98% | 104258 47.14% 48.12% | 105120 47.53% 95.66% | 9546 4.32% 99.97% | 62 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 221154 system.ruby.Directory_Controller.GETX 695129 0.00% 0.00% system.ruby.Directory_Controller.PUTX 620103 0.00% 0.00% system.ruby.Directory_Controller.PUTX_NotOwner 3899 0.00% 0.00% diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini index 4f3bc1d29..aa83b8fc1 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout index 0a8b6ce7e..78aee4704 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:23:08 -gem5 started Dec 11 2015 20:23:21 -gem5 executing on zizzer, pid 55319 -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter +gem5 compiled Jan 21 2016 14:20:17 +gem5 started Jan 21 2016 14:20:32 +gem5 executing on zizzer, pid 63114 +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 0128931d4..6281c21fd 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000541 # Nu sim_ticks 540820000 # Number of ticks simulated final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 45415693 # Simulator tick rate (ticks/s) -host_mem_usage 216096 # Number of bytes of host memory used -host_seconds 11.91 # Real time elapsed on the host +host_tick_rate 46544616 # Simulator tick rate (ticks/s) +host_mem_usage 216108 # Number of bytes of host memory used +host_seconds 11.62 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini index 66e654794..144cd4765 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout index 3c0bc5944..b41d812d8 100755 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:23:08 -gem5 started Dec 11 2015 20:23:21 -gem5 executing on zizzer, pid 55313 -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest +gem5 compiled Jan 21 2016 14:20:17 +gem5 started Jan 21 2016 14:20:31 +gem5 executing on zizzer, pid 63111 +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 03d50ce4b..ffbbc56b2 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000534 # Nu sim_ticks 534039500 # Number of ticks simulated final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 46247904 # Simulator tick rate (ticks/s) -host_mem_usage 215924 # Number of bytes of host memory used -host_seconds 11.55 # Real time elapsed on the host +host_tick_rate 46952087 # Simulator tick rate (ticks/s) +host_mem_usage 215976 # Number of bytes of host memory used +host_seconds 11.37 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index f73c1465e..333ab1c3b 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout index b76f1c9ca..222f46a4b 100755 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:27 -gem5 executing on zizzer, pid 26143 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:01 +gem5 executing on zizzer, pid 33985 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 590b870a6..381569cba 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163222 # Simulator instruction rate (inst/s) -host_op_rate 1163221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 582277557 # Simulator tick rate (ticks/s) -host_mem_usage 229020 # Number of bytes of host memory used -host_seconds 75.95 # Real time elapsed on the host +host_inst_rate 1271644 # Simulator instruction rate (inst/s) +host_op_rate 1271643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 636550745 # Simulator tick rate (ticks/s) +host_mem_usage 229384 # Number of bytes of host memory used +host_seconds 69.47 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index c9d39a11e..936d3f6e3 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout index f5449c46a..d1b551788 100755 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:28 -gem5 executing on zizzer, pid 26157 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33970 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 56e4f6cd2..8e6ab353a 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.134742 # Nu sim_ticks 134741611500 # Number of ticks simulated final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 541440 # Simulator instruction rate (inst/s) -host_op_rate 541439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825830456 # Simulator tick rate (ticks/s) -host_mem_usage 239292 # Number of bytes of host memory used -host_seconds 163.16 # Real time elapsed on the host +host_inst_rate 536259 # Simulator instruction rate (inst/s) +host_op_rate 536259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 817928903 # Simulator tick rate (ticks/s) +host_mem_usage 239376 # Number of bytes of host memory used +host_seconds 164.74 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 86fd36f82..0946d7533 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout index 03614c8bd..84e37158c 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11551 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:23 +gem5 executing on zizzer, pid 20742 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 8b7851044..ecfc0b9ca 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011500 # Number of ticks simulated final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 581361 # Simulator instruction rate (inst/s) -host_op_rate 743480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 401384017 # Simulator tick rate (ticks/s) -host_mem_usage 246028 # Number of bytes of host memory used -host_seconds 121.98 # Real time elapsed on the host +host_inst_rate 622932 # Simulator instruction rate (inst/s) +host_op_rate 796644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 430085915 # Simulator tick rate (ticks/s) +host_mem_usage 246536 # Number of bytes of host memory used +host_seconds 113.84 # Real time elapsed on the host sim_insts 70913182 # Number of instructions simulated sim_ops 90688137 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 3bbe596b7..5ef054f5d 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index fccc99f61..de3c6dccc 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11561 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:19 +gem5 executing on zizzer, pid 20723 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 23f0e2552..564642e9d 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu sim_ticks 128076812500 # Number of ticks simulated final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 359737 # Simulator instruction rate (inst/s) -host_op_rate 459283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 654705413 # Simulator tick rate (ticks/s) -host_mem_usage 256212 # Number of bytes of host memory used -host_seconds 195.63 # Real time elapsed on the host +host_inst_rate 329011 # Simulator instruction rate (inst/s) +host_op_rate 420055 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598785355 # Simulator tick rate (ticks/s) +host_mem_usage 256952 # Number of bytes of host memory used +host_seconds 213.89 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 976a05da7..b68bc2a7d 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout index dfe2a44d4..51bf0b517 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:40 -gem5 executing on zizzer, pid 899 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:25 +gem5 executing on zizzer, pid 8713 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 37d45b976..ba8d2e144 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148672000 # Number of ticks simulated final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114079 # Simulator instruction rate (inst/s) -host_op_rate 1128504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 564907393 # Simulator tick rate (ticks/s) -host_mem_usage 228612 # Number of bytes of host memory used -host_seconds 120.64 # Real time elapsed on the host +host_inst_rate 1099944 # Simulator instruction rate (inst/s) +host_op_rate 1114186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 557740246 # Simulator tick rate (ticks/s) +host_mem_usage 228968 # Number of bytes of host memory used +host_seconds 122.19 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index a09a4d576..4aa8d2f80 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout index 7bf2d7cc7..a1ad3bacc 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:39 -gem5 executing on zizzer, pid 896 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:26 +gem5 executing on zizzer, pid 8734 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 4cb4d965d..c506601b8 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu sim_ticks 203115876500 # Number of ticks simulated final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 554782 # Simulator instruction rate (inst/s) -host_op_rate 561966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 838437229 # Simulator tick rate (ticks/s) -host_mem_usage 239012 # Number of bytes of host memory used -host_seconds 242.26 # Real time elapsed on the host +host_inst_rate 563415 # Simulator instruction rate (inst/s) +host_op_rate 570710 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 851483432 # Simulator tick rate (ticks/s) +host_mem_usage 239344 # Number of bytes of host memory used +host_seconds 238.54 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout index 62d7346d7..bb54d1884 100755 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 19 2016 13:28:55 -gem5 started Jan 19 2016 13:29:16 -gem5 executing on zizzer, pid 48851 +gem5 compiled Jan 21 2016 14:58:44 +gem5 started Jan 21 2016 14:59:07 +gem5 executing on zizzer, pid 26197 command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt index 75065fd02..2da8cfc3e 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000014 # Nu sim_ticks 14181 # Number of ticks simulated final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 88786 # Simulator tick rate (ticks/s) -host_mem_usage 463996 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 116506 # Simulator tick rate (ticks/s) +host_mem_usage 464616 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory @@ -239,39 +239,63 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 63 -system.ruby.outstanding_req_hist::mean 12.920635 -system.ruby.outstanding_req_hist::gmean 11.694862 -system.ruby.outstanding_req_hist::stdev 4.228557 -system.ruby.outstanding_req_hist | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 14 22.22% 57.14% | 27 42.86% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 63 -system.ruby.latency_hist::bucket_size 1024 -system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 48 -system.ruby.latency_hist::mean 3351.354167 -system.ruby.latency_hist::gmean 1865.352879 -system.ruby.latency_hist::stdev 1934.275107 -system.ruby.latency_hist | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 18 37.50% 87.50% | 6 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 48 -system.ruby.hit_latency_hist::bucket_size 1024 -system.ruby.hit_latency_hist::max_bucket 10239 -system.ruby.hit_latency_hist::samples 42 -system.ruby.hit_latency_hist::mean 3684.428571 -system.ruby.hit_latency_hist::gmean 2778.454716 -system.ruby.hit_latency_hist::stdev 1783.107224 -system.ruby.hit_latency_hist | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 42 -system.ruby.miss_latency_hist::bucket_size 512 -system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 6 -system.ruby.miss_latency_hist::mean 1019.833333 -system.ruby.miss_latency_hist::gmean 114.673945 -system.ruby.miss_latency_hist::stdev 1281.644790 -system.ruby.miss_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 6 -system.ruby.L1Cache.incomplete_times 6 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 63 +system.ruby.outstanding_req_hist_seqr::mean 12.920635 +system.ruby.outstanding_req_hist_seqr::gmean 11.694862 +system.ruby.outstanding_req_hist_seqr::stdev 4.228557 +system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 14 22.22% 57.14% | 27 42.86% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 63 +system.ruby.outstanding_req_hist_coalsr::bucket_size 2 +system.ruby.outstanding_req_hist_coalsr::max_bucket 19 +system.ruby.outstanding_req_hist_coalsr::samples 885 +system.ruby.outstanding_req_hist_coalsr::mean 2.610169 +system.ruby.outstanding_req_hist_coalsr::gmean 2.223354 +system.ruby.outstanding_req_hist_coalsr::stdev 1.538535 +system.ruby.outstanding_req_hist_coalsr | 219 24.75% 24.75% | 478 54.01% 78.76% | 135 15.25% 94.01% | 43 4.86% 98.87% | 9 1.02% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_coalsr::total 885 +system.ruby.latency_hist_seqr::bucket_size 1024 +system.ruby.latency_hist_seqr::max_bucket 10239 +system.ruby.latency_hist_seqr::samples 48 +system.ruby.latency_hist_seqr::mean 3351.354167 +system.ruby.latency_hist_seqr::gmean 1865.352879 +system.ruby.latency_hist_seqr::stdev 1934.275107 +system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 18 37.50% 87.50% | 6 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 48 +system.ruby.latency_hist_coalsr::bucket_size 128 +system.ruby.latency_hist_coalsr::max_bucket 1279 +system.ruby.latency_hist_coalsr::samples 872 +system.ruby.latency_hist_coalsr::mean 222.089450 +system.ruby.latency_hist_coalsr::gmean 114.436171 +system.ruby.latency_hist_coalsr::stdev 241.512900 +system.ruby.latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::total 872 +system.ruby.hit_latency_hist_seqr::bucket_size 1024 +system.ruby.hit_latency_hist_seqr::max_bucket 10239 +system.ruby.hit_latency_hist_seqr::samples 42 +system.ruby.hit_latency_hist_seqr::mean 3684.428571 +system.ruby.hit_latency_hist_seqr::gmean 2778.454716 +system.ruby.hit_latency_hist_seqr::stdev 1783.107224 +system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 42 +system.ruby.miss_latency_hist_seqr::bucket_size 512 +system.ruby.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.miss_latency_hist_seqr::samples 6 +system.ruby.miss_latency_hist_seqr::mean 1019.833333 +system.ruby.miss_latency_hist_seqr::gmean 114.673945 +system.ruby.miss_latency_hist_seqr::stdev 1281.644790 +system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 6 +system.ruby.miss_latency_hist_coalsr::bucket_size 128 +system.ruby.miss_latency_hist_coalsr::max_bucket 1279 +system.ruby.miss_latency_hist_coalsr::samples 872 +system.ruby.miss_latency_hist_coalsr::mean 222.089450 +system.ruby.miss_latency_hist_coalsr::gmean 114.436171 +system.ruby.miss_latency_hist_coalsr::stdev 241.512900 +system.ruby.miss_latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::total 872 +system.ruby.L1Cache.incomplete_times_seqr 6 system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses @@ -801,110 +825,213 @@ system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% system.ruby.Directory_Controller.B.RdBlkM 4 0.00% 0.00% system.ruby.Directory_Controller.B.RdBlk 1 0.00% 0.00% system.ruby.Directory_Controller.B.CoreUnblock 303 0.00% 0.00% -system.ruby.LD.latency_hist::bucket_size 1024 -system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 1 -system.ruby.LD.latency_hist::mean 5324 -system.ruby.LD.latency_hist::gmean 5324.000000 -system.ruby.LD.latency_hist::stdev nan -system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1 -system.ruby.LD.hit_latency_hist::bucket_size 1024 -system.ruby.LD.hit_latency_hist::max_bucket 10239 -system.ruby.LD.hit_latency_hist::samples 1 -system.ruby.LD.hit_latency_hist::mean 5324 -system.ruby.LD.hit_latency_hist::gmean 5324.000000 -system.ruby.LD.hit_latency_hist::stdev nan -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1 -system.ruby.ST.latency_hist::bucket_size 1024 -system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 46 -system.ruby.ST.latency_hist::mean 3269.239130 -system.ruby.ST.latency_hist::gmean 1783.447677 -system.ruby.ST.latency_hist::stdev 1934.416354 -system.ruby.ST.latency_hist | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 18 39.13% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 46 -system.ruby.ST.hit_latency_hist::bucket_size 1024 -system.ruby.ST.hit_latency_hist::max_bucket 10239 -system.ruby.ST.hit_latency_hist::samples 40 -system.ruby.ST.hit_latency_hist::mean 3606.650000 -system.ruby.ST.hit_latency_hist::gmean 2691.718970 -system.ruby.ST.hit_latency_hist::stdev 1792.166924 -system.ruby.ST.hit_latency_hist | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 40 -system.ruby.ST.miss_latency_hist::bucket_size 512 -system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 6 -system.ruby.ST.miss_latency_hist::mean 1019.833333 -system.ruby.ST.miss_latency_hist::gmean 114.673945 -system.ruby.ST.miss_latency_hist::stdev 1281.644790 -system.ruby.ST.miss_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 6 -system.ruby.IFETCH.latency_hist::bucket_size 1024 -system.ruby.IFETCH.latency_hist::max_bucket 10239 -system.ruby.IFETCH.latency_hist::samples 1 -system.ruby.IFETCH.latency_hist::mean 5156 -system.ruby.IFETCH.latency_hist::gmean 5156.000000 -system.ruby.IFETCH.latency_hist::stdev nan -system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 1 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1024 -system.ruby.IFETCH.hit_latency_hist::max_bucket 10239 -system.ruby.IFETCH.hit_latency_hist::samples 1 -system.ruby.IFETCH.hit_latency_hist::mean 5156 -system.ruby.IFETCH.hit_latency_hist::gmean 5156.000000 -system.ruby.IFETCH.hit_latency_hist::stdev nan -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 1 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 6 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1019.833333 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 114.673945 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 1281.644790 -system.ruby.L1Cache.miss_mach_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 6 -system.ruby.Directory.hit_mach_latency_hist::bucket_size 1024 -system.ruby.Directory.hit_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.hit_mach_latency_hist::samples 42 -system.ruby.Directory.hit_mach_latency_hist::mean 3684.428571 -system.ruby.Directory.hit_mach_latency_hist::gmean 2778.454716 -system.ruby.Directory.hit_mach_latency_hist::stdev 1783.107224 -system.ruby.Directory.hit_mach_latency_hist | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.hit_mach_latency_hist::total 42 -system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 1024 -system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 10239 -system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 1 -system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 5324 -system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 5324.000000 -system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev nan -system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.hit_type_mach_latency_hist::total 1 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 6 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1019.833333 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 114.673945 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 1281.644790 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 6 -system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 1024 -system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 10239 -system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 40 -system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 3606.650000 -system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 2691.718970 -system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 1792.166924 -system.ruby.ST.Directory.hit_type_mach_latency_hist | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.hit_type_mach_latency_hist::total 40 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 1024 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 10239 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 5156 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 5156.000000 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev nan -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1 +system.ruby.LD.latency_hist_seqr::bucket_size 1024 +system.ruby.LD.latency_hist_seqr::max_bucket 10239 +system.ruby.LD.latency_hist_seqr::samples 1 +system.ruby.LD.latency_hist_seqr::mean 5324 +system.ruby.LD.latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.latency_hist_seqr::stdev nan +system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1 +system.ruby.LD.latency_hist_coalsr::bucket_size 128 +system.ruby.LD.latency_hist_coalsr::max_bucket 1279 +system.ruby.LD.latency_hist_coalsr::samples 69 +system.ruby.LD.latency_hist_coalsr::mean 111.289855 +system.ruby.LD.latency_hist_coalsr::gmean 81.460116 +system.ruby.LD.latency_hist_coalsr::stdev 88.701101 +system.ruby.LD.latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::total 69 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239 +system.ruby.LD.hit_latency_hist_seqr::samples 1 +system.ruby.LD.hit_latency_hist_seqr::mean 5324 +system.ruby.LD.hit_latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.hit_latency_hist_seqr::stdev nan +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 1 +system.ruby.LD.miss_latency_hist_coalsr::bucket_size 128 +system.ruby.LD.miss_latency_hist_coalsr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_coalsr::samples 69 +system.ruby.LD.miss_latency_hist_coalsr::mean 111.289855 +system.ruby.LD.miss_latency_hist_coalsr::gmean 81.460116 +system.ruby.LD.miss_latency_hist_coalsr::stdev 88.701101 +system.ruby.LD.miss_latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::total 69 +system.ruby.ST.latency_hist_seqr::bucket_size 1024 +system.ruby.ST.latency_hist_seqr::max_bucket 10239 +system.ruby.ST.latency_hist_seqr::samples 46 +system.ruby.ST.latency_hist_seqr::mean 3269.239130 +system.ruby.ST.latency_hist_seqr::gmean 1783.447677 +system.ruby.ST.latency_hist_seqr::stdev 1934.416354 +system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 18 39.13% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 46 +system.ruby.ST.latency_hist_coalsr::bucket_size 128 +system.ruby.ST.latency_hist_coalsr::max_bucket 1279 +system.ruby.ST.latency_hist_coalsr::samples 803 +system.ruby.ST.latency_hist_coalsr::mean 231.610212 +system.ruby.ST.latency_hist_coalsr::gmean 117.827816 +system.ruby.ST.latency_hist_coalsr::stdev 248.057845 +system.ruby.ST.latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::total 803 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 10239 +system.ruby.ST.hit_latency_hist_seqr::samples 40 +system.ruby.ST.hit_latency_hist_seqr::mean 3606.650000 +system.ruby.ST.hit_latency_hist_seqr::gmean 2691.718970 +system.ruby.ST.hit_latency_hist_seqr::stdev 1792.166924 +system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 40 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.miss_latency_hist_seqr::samples 6 +system.ruby.ST.miss_latency_hist_seqr::mean 1019.833333 +system.ruby.ST.miss_latency_hist_seqr::gmean 114.673945 +system.ruby.ST.miss_latency_hist_seqr::stdev 1281.644790 +system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 6 +system.ruby.ST.miss_latency_hist_coalsr::bucket_size 128 +system.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279 +system.ruby.ST.miss_latency_hist_coalsr::samples 803 +system.ruby.ST.miss_latency_hist_coalsr::mean 231.610212 +system.ruby.ST.miss_latency_hist_coalsr::gmean 117.827816 +system.ruby.ST.miss_latency_hist_coalsr::stdev 248.057845 +system.ruby.ST.miss_latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::total 803 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 10239 +system.ruby.IFETCH.latency_hist_seqr::samples 1 +system.ruby.IFETCH.latency_hist_seqr::mean 5156 +system.ruby.IFETCH.latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.latency_hist_seqr::stdev nan +system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 1 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 5156 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1019.833333 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.673945 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1281.644790 +system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6 +system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024 +system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239 +system.ruby.Directory.hit_mach_latency_hist_seqr::samples 42 +system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3684.428571 +system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2778.454716 +system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1783.107224 +system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist_seqr::total 42 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 644 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 154.992236 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 124.686138 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 142.628867 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 516 80.12% 80.12% | 30 4.66% 84.78% | 42 6.52% 91.30% | 26 4.04% 95.34% | 17 2.64% 97.98% | 7 1.09% 99.07% | 4 0.62% 99.69% | 1 0.16% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 644 +system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 +system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 +system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 64 +system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.109375 +system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.055645 +system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.537991 +system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 61 95.31% 95.31% | 1 1.56% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP.miss_mach_latency_hist_coalsr::total 64 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 164 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 571.804878 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 508.667381 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 267.247131 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 41.46% 41.46% | 13 7.93% 49.39% | 16 9.76% 59.15% | 13 7.93% 67.07% | 29 17.68% 84.76% | 22 13.41% 98.17% | 3 1.83% 100.00% | 0 0.00% 100.00% +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 164 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5324 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 107.322581 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 101.146340 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 70.212972 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 59 95.16% 95.16% | 2 3.23% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 4 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 4 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 340.333333 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 328.169813 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 116.791838 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1019.833333 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.673945 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1281.644790 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3606.650000 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2691.718970 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1792.166924 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 582 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 160.070447 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 127.496503 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 147.403962 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 457 78.52% 78.52% | 28 4.81% 83.33% | 42 7.22% 90.55% | 26 4.47% 95.02% | 17 2.92% 97.94% | 6 1.03% 98.97% | 4 0.69% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 582 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 60 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.116667 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.059463 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.555151 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 57 95.00% 95.00% | 1 1.67% 96.67% | 0 0.00% 96.67% | 2 3.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 60 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 161 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 576.118012 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 512.838367 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 267.518863 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 66 40.99% 40.99% | 12 7.45% 48.45% | 16 9.94% 58.39% | 13 8.07% 66.46% | 29 18.01% 84.47% | 22 13.66% 98.14% | 3 1.86% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 161 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5156 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1 system.ruby.SQC_Controller.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% system.ruby.SQC_Controller.Fetch::total 27 system.ruby.SQC_Controller.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini index 49022a9e3..f9b74217d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -260,6 +261,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -283,6 +285,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -363,12 +366,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.ruby.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true ruby_system=system.ruby @@ -440,6 +445,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1113,6 +1119,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout index 4a72c4f44..db9c26437 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:05:44 -gem5 started Dec 11 2015 20:06:16 -gem5 executing on zizzer, pid 37019 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level +gem5 compiled Jan 21 2016 14:01:33 +gem5 started Jan 21 2016 14:02:10 +gem5 executing on zizzer, pid 44718 +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 7165361fa..dac1409b7 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu sim_ticks 43191 # Number of ticks simulated final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 266014 # Simulator tick rate (ticks/s) -host_mem_usage 386184 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 247811 # Simulator tick rate (ticks/s) +host_mem_usage 388428 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory @@ -273,37 +273,37 @@ system.ruby.delayHist::mean 2.675000 # de system.ruby.delayHist::stdev 5.399947 # delay histogram for all message system.ruby.delayHist | 5144 76.55% 76.55% | 51 0.76% 77.31% | 1138 16.93% 94.24% | 8 0.12% 94.36% | 323 4.81% 99.17% | 6 0.09% 99.26% | 0 0.00% 99.26% | 43 0.64% 99.90% | 0 0.00% 99.90% | 7 0.10% 100.00% # delay histogram for all message system.ruby.delayHist::total 6720 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1041 -system.ruby.outstanding_req_hist::mean 15.700288 -system.ruby.outstanding_req_hist::gmean 15.598621 -system.ruby.outstanding_req_hist::stdev 1.186661 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1041 -system.ruby.latency_hist::bucket_size 128 -system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 1025 -system.ruby.latency_hist::mean 658.597073 -system.ruby.latency_hist::gmean 361.484818 -system.ruby.latency_hist::stdev 297.350955 -system.ruby.latency_hist | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00% -system.ruby.latency_hist::total 1025 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 89 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 89 -system.ruby.miss_latency_hist::bucket_size 128 -system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 936 -system.ruby.miss_latency_hist::mean 721.125000 -system.ruby.miss_latency_hist::gmean 632.888578 -system.ruby.miss_latency_hist::stdev 227.503250 -system.ruby.miss_latency_hist | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00% -system.ruby.miss_latency_hist::total 936 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 1041 +system.ruby.outstanding_req_hist_seqr::mean 15.700288 +system.ruby.outstanding_req_hist_seqr::gmean 15.598621 +system.ruby.outstanding_req_hist_seqr::stdev 1.186661 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1041 +system.ruby.latency_hist_seqr::bucket_size 128 +system.ruby.latency_hist_seqr::max_bucket 1279 +system.ruby.latency_hist_seqr::samples 1025 +system.ruby.latency_hist_seqr::mean 658.597073 +system.ruby.latency_hist_seqr::gmean 361.484818 +system.ruby.latency_hist_seqr::stdev 297.350955 +system.ruby.latency_hist_seqr | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00% +system.ruby.latency_hist_seqr::total 1025 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 89 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 89 +system.ruby.miss_latency_hist_seqr::bucket_size 128 +system.ruby.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.miss_latency_hist_seqr::samples 936 +system.ruby.miss_latency_hist_seqr::mean 721.125000 +system.ruby.miss_latency_hist_seqr::gmean 632.888578 +system.ruby.miss_latency_hist_seqr::stdev 227.503250 +system.ruby.miss_latency_hist_seqr | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00% +system.ruby.miss_latency_hist_seqr::total 936 system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses @@ -500,68 +500,68 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 278 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 278 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 278 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 128 -system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 37 -system.ruby.LD.latency_hist::mean 621.135135 -system.ruby.LD.latency_hist::gmean 207.168110 -system.ruby.LD.latency_hist::stdev 333.448910 -system.ruby.LD.latency_hist | 8 21.62% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 13 35.14% 56.76% | 14 37.84% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 37 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 7 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 7 -system.ruby.LD.miss_latency_hist::bucket_size 128 -system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 30 -system.ruby.LD.miss_latency_hist::mean 765.833333 -system.ruby.LD.miss_latency_hist::gmean 719.114834 -system.ruby.LD.miss_latency_hist::stdev 153.429099 -system.ruby.LD.miss_latency_hist | 1 3.33% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 13 43.33% 46.67% | 14 46.67% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 30 -system.ruby.ST.latency_hist::bucket_size 128 -system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 925 -system.ruby.ST.latency_hist::mean 697.631351 -system.ruby.ST.latency_hist::gmean 404.802159 -system.ruby.ST.latency_hist::stdev 266.794551 -system.ruby.ST.latency_hist | 101 10.92% 10.92% | 7 0.76% 11.68% | 4 0.43% 12.11% | 4 0.43% 12.54% | 32 3.46% 16.00% | 289 31.24% 47.24% | 404 43.68% 90.92% | 47 5.08% 96.00% | 28 3.03% 99.03% | 9 0.97% 100.00% -system.ruby.ST.latency_hist::total 925 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 82 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 82 -system.ruby.ST.miss_latency_hist::bucket_size 128 -system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 843 -system.ruby.ST.miss_latency_hist::mean 765.393832 -system.ruby.ST.miss_latency_hist::gmean 725.861277 -system.ruby.ST.miss_latency_hist::stdev 162.026380 -system.ruby.ST.miss_latency_hist | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00% -system.ruby.ST.miss_latency_hist::total 843 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 -system.ruby.IFETCH.latency_hist::samples 63 -system.ruby.IFETCH.latency_hist::mean 107.476190 -system.ruby.IFETCH.latency_hist::gmean 95.146533 -system.ruby.IFETCH.latency_hist::stdev 52.448702 -system.ruby.IFETCH.latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 63 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist::samples 63 -system.ruby.IFETCH.miss_latency_hist::mean 107.476190 -system.ruby.IFETCH.miss_latency_hist::gmean 95.146533 -system.ruby.IFETCH.miss_latency_hist::stdev 52.448702 -system.ruby.IFETCH.miss_latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 63 +system.ruby.LD.latency_hist_seqr::bucket_size 128 +system.ruby.LD.latency_hist_seqr::max_bucket 1279 +system.ruby.LD.latency_hist_seqr::samples 37 +system.ruby.LD.latency_hist_seqr::mean 621.135135 +system.ruby.LD.latency_hist_seqr::gmean 207.168110 +system.ruby.LD.latency_hist_seqr::stdev 333.448910 +system.ruby.LD.latency_hist_seqr | 8 21.62% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 13 35.14% 56.76% | 14 37.84% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 37 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 7 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 7 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_seqr::samples 30 +system.ruby.LD.miss_latency_hist_seqr::mean 765.833333 +system.ruby.LD.miss_latency_hist_seqr::gmean 719.114834 +system.ruby.LD.miss_latency_hist_seqr::stdev 153.429099 +system.ruby.LD.miss_latency_hist_seqr | 1 3.33% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 13 43.33% 46.67% | 14 46.67% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 30 +system.ruby.ST.latency_hist_seqr::bucket_size 128 +system.ruby.ST.latency_hist_seqr::max_bucket 1279 +system.ruby.ST.latency_hist_seqr::samples 925 +system.ruby.ST.latency_hist_seqr::mean 697.631351 +system.ruby.ST.latency_hist_seqr::gmean 404.802159 +system.ruby.ST.latency_hist_seqr::stdev 266.794551 +system.ruby.ST.latency_hist_seqr | 101 10.92% 10.92% | 7 0.76% 11.68% | 4 0.43% 12.11% | 4 0.43% 12.54% | 32 3.46% 16.00% | 289 31.24% 47.24% | 404 43.68% 90.92% | 47 5.08% 96.00% | 28 3.03% 99.03% | 9 0.97% 100.00% +system.ruby.ST.latency_hist_seqr::total 925 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 82 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 82 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.miss_latency_hist_seqr::samples 843 +system.ruby.ST.miss_latency_hist_seqr::mean 765.393832 +system.ruby.ST.miss_latency_hist_seqr::gmean 725.861277 +system.ruby.ST.miss_latency_hist_seqr::stdev 162.026380 +system.ruby.ST.miss_latency_hist_seqr | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 843 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 63 +system.ruby.IFETCH.latency_hist_seqr::mean 107.476190 +system.ruby.IFETCH.latency_hist_seqr::gmean 95.146533 +system.ruby.IFETCH.latency_hist_seqr::stdev 52.448702 +system.ruby.IFETCH.latency_hist_seqr | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 63 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 63 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 107.476190 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 95.146533 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 52.448702 +system.ruby.IFETCH.miss_latency_hist_seqr | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 63 system.ruby.Directory_Controller.Fetch 902 0.00% 0.00% system.ruby.Directory_Controller.Data 811 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 902 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index e3b78cdef..a9fdb6e67 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -265,6 +266,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -288,6 +290,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -349,12 +352,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.ruby.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true ruby_system=system.ruby @@ -433,6 +438,7 @@ slave=system.ruby.network.master[3] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1105,6 +1111,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 5739a0e00..bb50cd40f 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:10:49 -gem5 started Dec 11 2015 20:11:27 -gem5 executing on zizzer, pid 42474 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory +gem5 compiled Jan 21 2016 14:06:59 +gem5 started Jan 21 2016 14:07:35 +gem5 executing on zizzer, pid 50073 +command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 91f19eaef..a72f38554 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu sim_ticks 54211 # Number of ticks simulated final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 209714 # Simulator tick rate (ticks/s) -host_mem_usage 387824 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_tick_rate 192824 # Simulator tick rate (ticks/s) +host_mem_usage 389940 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory @@ -266,37 +266,37 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 985 -system.ruby.outstanding_req_hist::mean 15.747208 -system.ruby.outstanding_req_hist::gmean 15.641156 -system.ruby.outstanding_req_hist::stdev 1.199617 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 985 -system.ruby.latency_hist::bucket_size 256 -system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 970 -system.ruby.latency_hist::mean 876.382474 -system.ruby.latency_hist::gmean 454.463576 -system.ruby.latency_hist::stdev 370.932806 -system.ruby.latency_hist | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 970 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 92 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 92 -system.ruby.miss_latency_hist::bucket_size 256 -system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 878 -system.ruby.miss_latency_hist::mean 968.108200 -system.ruby.miss_latency_hist::gmean 862.901849 -system.ruby.miss_latency_hist::stdev 251.425992 -system.ruby.miss_latency_hist | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 878 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 985 +system.ruby.outstanding_req_hist_seqr::mean 15.747208 +system.ruby.outstanding_req_hist_seqr::gmean 15.641156 +system.ruby.outstanding_req_hist_seqr::stdev 1.199617 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 985 +system.ruby.latency_hist_seqr::bucket_size 256 +system.ruby.latency_hist_seqr::max_bucket 2559 +system.ruby.latency_hist_seqr::samples 970 +system.ruby.latency_hist_seqr::mean 876.382474 +system.ruby.latency_hist_seqr::gmean 454.463576 +system.ruby.latency_hist_seqr::stdev 370.932806 +system.ruby.latency_hist_seqr | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 970 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 92 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 92 +system.ruby.miss_latency_hist_seqr::bucket_size 256 +system.ruby.miss_latency_hist_seqr::max_bucket 2559 +system.ruby.miss_latency_hist_seqr::samples 878 +system.ruby.miss_latency_hist_seqr::mean 968.108200 +system.ruby.miss_latency_hist_seqr::gmean 862.901849 +system.ruby.miss_latency_hist_seqr::stdev 251.425992 +system.ruby.miss_latency_hist_seqr | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 878 system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses @@ -467,75 +467,75 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6752 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 54288 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6040 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6736 -system.ruby.LD.latency_hist::bucket_size 128 -system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 54 -system.ruby.LD.latency_hist::mean 874.574074 -system.ruby.LD.latency_hist::gmean 437.265598 -system.ruby.LD.latency_hist::stdev 350.325488 -system.ruby.LD.latency_hist | 7 12.96% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 5 9.26% 22.22% | 29 53.70% 75.93% | 9 16.67% 92.59% | 4 7.41% 100.00% -system.ruby.LD.latency_hist::total 54 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 6 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 6 -system.ruby.LD.miss_latency_hist::bucket_size 128 -system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 48 -system.ruby.LD.miss_latency_hist::mean 983.770833 -system.ruby.LD.miss_latency_hist::gmean 935.057837 -system.ruby.LD.miss_latency_hist::stdev 169.695753 -system.ruby.LD.miss_latency_hist | 1 2.08% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 5 10.42% 12.50% | 29 60.42% 72.92% | 9 18.75% 91.67% | 4 8.33% 100.00% -system.ruby.LD.miss_latency_hist::total 48 -system.ruby.ST.latency_hist::bucket_size 256 -system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 870 -system.ruby.ST.latency_hist::mean 919.120690 -system.ruby.ST.latency_hist::gmean 509.527867 -system.ruby.ST.latency_hist::stdev 331.108106 -system.ruby.ST.latency_hist | 93 10.69% 10.69% | 6 0.69% 11.38% | 4 0.46% 11.84% | 354 40.69% 52.53% | 405 46.55% 99.08% | 8 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 870 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 84 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 84 -system.ruby.ST.miss_latency_hist::bucket_size 256 -system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 786 -system.ruby.ST.miss_latency_hist::mean 1017.240458 -system.ruby.ST.miss_latency_hist::gmean 991.935880 -system.ruby.ST.miss_latency_hist::stdev 146.709443 -system.ruby.ST.miss_latency_hist | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 354 45.04% 47.46% | 405 51.53% 98.98% | 8 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 786 -system.ruby.IFETCH.latency_hist::bucket_size 32 -system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 46 -system.ruby.IFETCH.latency_hist::mean 70.195652 -system.ruby.IFETCH.latency_hist::gmean 54.673545 -system.ruby.IFETCH.latency_hist::stdev 37.753363 -system.ruby.IFETCH.latency_hist | 4 8.70% 8.70% | 14 30.43% 39.13% | 21 45.65% 84.78% | 1 2.17% 86.96% | 4 8.70% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 46 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2 -system.ruby.IFETCH.miss_latency_hist::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 44 -system.ruby.IFETCH.miss_latency_hist::mean 73.340909 -system.ruby.IFETCH.miss_latency_hist::gmean 65.579350 -system.ruby.IFETCH.miss_latency_hist::stdev 35.479403 -system.ruby.IFETCH.miss_latency_hist | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 44 +system.ruby.LD.latency_hist_seqr::bucket_size 128 +system.ruby.LD.latency_hist_seqr::max_bucket 1279 +system.ruby.LD.latency_hist_seqr::samples 54 +system.ruby.LD.latency_hist_seqr::mean 874.574074 +system.ruby.LD.latency_hist_seqr::gmean 437.265598 +system.ruby.LD.latency_hist_seqr::stdev 350.325488 +system.ruby.LD.latency_hist_seqr | 7 12.96% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 5 9.26% 22.22% | 29 53.70% 75.93% | 9 16.67% 92.59% | 4 7.41% 100.00% +system.ruby.LD.latency_hist_seqr::total 54 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 6 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 6 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_seqr::samples 48 +system.ruby.LD.miss_latency_hist_seqr::mean 983.770833 +system.ruby.LD.miss_latency_hist_seqr::gmean 935.057837 +system.ruby.LD.miss_latency_hist_seqr::stdev 169.695753 +system.ruby.LD.miss_latency_hist_seqr | 1 2.08% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 5 10.42% 12.50% | 29 60.42% 72.92% | 9 18.75% 91.67% | 4 8.33% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 48 +system.ruby.ST.latency_hist_seqr::bucket_size 256 +system.ruby.ST.latency_hist_seqr::max_bucket 2559 +system.ruby.ST.latency_hist_seqr::samples 870 +system.ruby.ST.latency_hist_seqr::mean 919.120690 +system.ruby.ST.latency_hist_seqr::gmean 509.527867 +system.ruby.ST.latency_hist_seqr::stdev 331.108106 +system.ruby.ST.latency_hist_seqr | 93 10.69% 10.69% | 6 0.69% 11.38% | 4 0.46% 11.84% | 354 40.69% 52.53% | 405 46.55% 99.08% | 8 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 870 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 84 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 84 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 +system.ruby.ST.miss_latency_hist_seqr::samples 786 +system.ruby.ST.miss_latency_hist_seqr::mean 1017.240458 +system.ruby.ST.miss_latency_hist_seqr::gmean 991.935880 +system.ruby.ST.miss_latency_hist_seqr::stdev 146.709443 +system.ruby.ST.miss_latency_hist_seqr | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 354 45.04% 47.46% | 405 51.53% 98.98% | 8 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 786 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 46 +system.ruby.IFETCH.latency_hist_seqr::mean 70.195652 +system.ruby.IFETCH.latency_hist_seqr::gmean 54.673545 +system.ruby.IFETCH.latency_hist_seqr::stdev 37.753363 +system.ruby.IFETCH.latency_hist_seqr | 4 8.70% 8.70% | 14 30.43% 39.13% | 21 45.65% 84.78% | 1 2.17% 86.96% | 4 8.70% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 46 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 44 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.340909 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 65.579350 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.479403 +system.ruby.IFETCH.miss_latency_hist_seqr | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 44 system.ruby.Directory_Controller.GETX 761 0.00% 0.00% system.ruby.Directory_Controller.GETS 83 0.00% 0.00% system.ruby.Directory_Controller.PUTX 755 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index 91457f746..47885b3ee 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -313,6 +314,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -336,6 +338,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -413,12 +416,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.ruby.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true ruby_system=system.ruby @@ -492,6 +497,7 @@ slave=system.ruby.network.master[4] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1669,6 +1675,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index f6fb164f9..583f49075 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:15:50 -gem5 started Dec 11 2015 20:16:20 -gem5 executing on zizzer, pid 47648 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token +gem5 compiled Jan 21 2016 14:12:23 +gem5 started Jan 21 2016 14:12:59 +gem5 executing on zizzer, pid 55402 +command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 22d2e6b72..851456fb6 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000050 # Nu sim_ticks 50141 # Number of ticks simulated final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 455774 # Simulator tick rate (ticks/s) -host_mem_usage 387088 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 395128 # Simulator tick rate (ticks/s) +host_mem_usage 389312 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory @@ -263,39 +263,39 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 961 -system.ruby.outstanding_req_hist::mean 15.762747 -system.ruby.outstanding_req_hist::gmean 15.654325 -system.ruby.outstanding_req_hist::stdev 1.209298 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.42% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.47% 11.13% | 854 88.87% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 961 -system.ruby.latency_hist::bucket_size 256 -system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 946 -system.ruby.latency_hist::mean 831.747357 -system.ruby.latency_hist::gmean 353.331206 -system.ruby.latency_hist::stdev 440.661399 -system.ruby.latency_hist | 208 21.99% 21.99% | 7 0.74% 22.73% | 5 0.53% 23.26% | 262 27.70% 50.95% | 409 43.23% 94.19% | 55 5.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 946 -system.ruby.hit_latency_hist::bucket_size 256 -system.ruby.hit_latency_hist::max_bucket 2559 -system.ruby.hit_latency_hist::samples 156 -system.ruby.hit_latency_hist::mean 161.115385 -system.ruby.hit_latency_hist::gmean 5.208817 -system.ruby.hit_latency_hist::stdev 361.858143 -system.ruby.hit_latency_hist | 132 84.62% 84.62% | 0 0.00% 84.62% | 0 0.00% 84.62% | 17 10.90% 95.51% | 6 3.85% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 156 -system.ruby.miss_latency_hist::bucket_size 256 -system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 790 -system.ruby.miss_latency_hist::mean 964.175949 -system.ruby.miss_latency_hist::gmean 812.519909 -system.ruby.miss_latency_hist::stdev 316.811320 -system.ruby.miss_latency_hist | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 790 -system.ruby.Directory.incomplete_times 790 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 961 +system.ruby.outstanding_req_hist_seqr::mean 15.762747 +system.ruby.outstanding_req_hist_seqr::gmean 15.654325 +system.ruby.outstanding_req_hist_seqr::stdev 1.209298 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.42% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.47% 11.13% | 854 88.87% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 961 +system.ruby.latency_hist_seqr::bucket_size 256 +system.ruby.latency_hist_seqr::max_bucket 2559 +system.ruby.latency_hist_seqr::samples 946 +system.ruby.latency_hist_seqr::mean 831.747357 +system.ruby.latency_hist_seqr::gmean 353.331206 +system.ruby.latency_hist_seqr::stdev 440.661399 +system.ruby.latency_hist_seqr | 208 21.99% 21.99% | 7 0.74% 22.73% | 5 0.53% 23.26% | 262 27.70% 50.95% | 409 43.23% 94.19% | 55 5.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 946 +system.ruby.hit_latency_hist_seqr::bucket_size 256 +system.ruby.hit_latency_hist_seqr::max_bucket 2559 +system.ruby.hit_latency_hist_seqr::samples 156 +system.ruby.hit_latency_hist_seqr::mean 161.115385 +system.ruby.hit_latency_hist_seqr::gmean 5.208817 +system.ruby.hit_latency_hist_seqr::stdev 361.858143 +system.ruby.hit_latency_hist_seqr | 132 84.62% 84.62% | 0 0.00% 84.62% | 0 0.00% 84.62% | 17 10.90% 95.51% | 6 3.85% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 156 +system.ruby.miss_latency_hist_seqr::bucket_size 256 +system.ruby.miss_latency_hist_seqr::max_bucket 2559 +system.ruby.miss_latency_hist_seqr::samples 790 +system.ruby.miss_latency_hist_seqr::mean 964.175949 +system.ruby.miss_latency_hist_seqr::gmean 812.519909 +system.ruby.miss_latency_hist_seqr::stdev 316.811320 +system.ruby.miss_latency_hist_seqr | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 790 +system.ruby.Directory.incomplete_times_seqr 790 system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 788 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses @@ -452,171 +452,171 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6344 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 51768 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 520 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 272 -system.ruby.LD.latency_hist::bucket_size 256 -system.ruby.LD.latency_hist::max_bucket 2559 -system.ruby.LD.latency_hist::samples 46 -system.ruby.LD.latency_hist::mean 817.543478 -system.ruby.LD.latency_hist::gmean 284.544942 -system.ruby.LD.latency_hist::stdev 462.655942 -system.ruby.LD.latency_hist | 11 23.91% 23.91% | 0 0.00% 23.91% | 0 0.00% 23.91% | 15 32.61% 56.52% | 16 34.78% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 46 -system.ruby.LD.hit_latency_hist::bucket_size 128 -system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 10 -system.ruby.LD.hit_latency_hist::mean 101 -system.ruby.LD.hit_latency_hist::gmean 3.750098 -system.ruby.LD.hit_latency_hist::stdev 300.217329 -system.ruby.LD.hit_latency_hist | 9 90.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 10 -system.ruby.LD.miss_latency_hist::bucket_size 256 -system.ruby.LD.miss_latency_hist::max_bucket 2559 -system.ruby.LD.miss_latency_hist::samples 36 -system.ruby.LD.miss_latency_hist::mean 1016.583333 -system.ruby.LD.miss_latency_hist::gmean 947.115995 -system.ruby.LD.miss_latency_hist::stdev 254.139824 -system.ruby.LD.miss_latency_hist | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 36 -system.ruby.ST.latency_hist::bucket_size 256 -system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 846 -system.ruby.ST.latency_hist::mean 881.170213 -system.ruby.ST.latency_hist::gmean 402.465808 -system.ruby.ST.latency_hist::stdev 407.456674 -system.ruby.ST.latency_hist | 144 17.02% 17.02% | 6 0.71% 17.73% | 5 0.59% 18.32% | 247 29.20% 47.52% | 393 46.45% 93.97% | 51 6.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 846 -system.ruby.ST.hit_latency_hist::bucket_size 256 -system.ruby.ST.hit_latency_hist::max_bucket 2559 -system.ruby.ST.hit_latency_hist::samples 138 -system.ruby.ST.hit_latency_hist::mean 173.615942 -system.ruby.ST.hit_latency_hist::gmean 5.002563 -system.ruby.ST.hit_latency_hist::stdev 375.029660 -system.ruby.ST.hit_latency_hist | 115 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 16 11.59% 94.93% | 6 4.35% 99.28% | 1 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 138 -system.ruby.ST.miss_latency_hist::bucket_size 256 -system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 708 -system.ruby.ST.miss_latency_hist::mean 1019.083333 -system.ruby.ST.miss_latency_hist::gmean 946.557722 -system.ruby.ST.miss_latency_hist::stdev 233.252272 -system.ruby.ST.miss_latency_hist | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 708 -system.ruby.IFETCH.latency_hist::bucket_size 32 -system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 54 -system.ruby.IFETCH.latency_hist::mean 69.555556 -system.ruby.IFETCH.latency_hist::gmean 55.256031 -system.ruby.IFETCH.latency_hist::stdev 50.686855 -system.ruby.IFETCH.latency_hist | 8 14.81% 14.81% | 15 27.78% 42.59% | 25 46.30% 88.89% | 0 0.00% 88.89% | 3 5.56% 94.44% | 0 0.00% 94.44% | 2 3.70% 98.15% | 0 0.00% 98.15% | 0 0.00% 98.15% | 1 1.85% 100.00% -system.ruby.IFETCH.latency_hist::total 54 -system.ruby.IFETCH.hit_latency_hist::bucket_size 4 -system.ruby.IFETCH.hit_latency_hist::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist::samples 8 -system.ruby.IFETCH.hit_latency_hist::mean 20.625000 -system.ruby.IFETCH.hit_latency_hist::gmean 15.768384 -system.ruby.IFETCH.hit_latency_hist::stdev 8.052285 -system.ruby.IFETCH.hit_latency_hist | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 1 12.50% 25.00% | 6 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 8 -system.ruby.IFETCH.miss_latency_hist::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 46 -system.ruby.IFETCH.miss_latency_hist::mean 78.065217 -system.ruby.IFETCH.miss_latency_hist::gmean 68.721309 -system.ruby.IFETCH.miss_latency_hist::stdev 50.161252 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 46 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 106 -system.ruby.L1Cache.hit_mach_latency_hist::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 106 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 256 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 2559 -system.ruby.L2Cache.hit_mach_latency_hist::samples 50 -system.ruby.L2Cache.hit_mach_latency_hist::mean 500.560000 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 172.276482 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 491.089092 -system.ruby.L2Cache.hit_mach_latency_hist | 26 52.00% 52.00% | 0 0.00% 52.00% | 0 0.00% 52.00% | 17 34.00% 86.00% | 6 12.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 50 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 256 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 2559 -system.ruby.Directory.miss_mach_latency_hist::samples 790 -system.ruby.Directory.miss_mach_latency_hist::mean 964.175949 -system.ruby.Directory.miss_mach_latency_hist::gmean 812.519909 -system.ruby.Directory.miss_mach_latency_hist::stdev 316.811320 -system.ruby.Directory.miss_mach_latency_hist | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 790 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 7 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 7 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 3 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 334.333333 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 81.936099 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 537.513101 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 3 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 36 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1016.583333 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 947.115995 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 254.139824 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 36 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 98 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 98 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 256 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 40 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 596.525000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 258.353536 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 485.549015 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 17 42.50% 42.50% | 0 0.00% 42.50% | 0 0.00% 42.50% | 16 40.00% 82.50% | 6 15.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 40 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 256 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29.20% 47.52% | 393 46.45% 93.97% | 51 6.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 846 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 256 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 2559 +system.ruby.ST.hit_latency_hist_seqr::samples 138 +system.ruby.ST.hit_latency_hist_seqr::mean 173.615942 +system.ruby.ST.hit_latency_hist_seqr::gmean 5.002563 +system.ruby.ST.hit_latency_hist_seqr::stdev 375.029660 +system.ruby.ST.hit_latency_hist_seqr | 115 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 16 11.59% 94.93% | 6 4.35% 99.28% | 1 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 138 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 +system.ruby.ST.miss_latency_hist_seqr::samples 708 +system.ruby.ST.miss_latency_hist_seqr::mean 1019.083333 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+system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 106 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 106 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 256 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 2559 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| 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 790 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 7 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 7 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 3 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 334.333333 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 81.936099 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 537.513101 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 3 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1016.583333 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 947.115995 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 254.139824 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 98 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 98 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 256 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 2559 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 40 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 596.525000 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 258.353536 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 485.549015 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 17 42.50% 42.50% | 0 0.00% 42.50% | 0 0.00% 42.50% | 16 40.00% 82.50% | 6 15.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 40 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 708 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1019.083333 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 946.557722 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 233.252272 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 708 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::stdev nan +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 1 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 7 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.428571 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.382968 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.511858 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 7 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.065217 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 68.721309 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 50.161252 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46 system.ruby.Directory_Controller.GETX 710 0.00% 0.00% system.ruby.Directory_Controller.GETS 85 0.00% 0.00% system.ruby.Directory_Controller.Lockdown 17 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index c18dbade3..39a3b4a9b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -230,6 +231,7 @@ master=system.ruby.network.slave[3] type=RubyCache children=replacement_policy assoc=4 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -329,6 +331,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -352,6 +355,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -375,6 +379,7 @@ size=256 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -436,12 +441,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.ruby.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true ruby_system=system.ruby @@ -1153,6 +1160,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 0e5bf2d7e..cb4dc5a7d 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:00:36 -gem5 started Dec 11 2015 20:01:07 -gem5 executing on zizzer, pid 31713 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer +gem5 compiled Jan 21 2016 13:56:08 +gem5 started Jan 21 2016 13:56:42 +gem5 executing on zizzer, pid 39357 +command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 7065b4fe2..016399c56 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu sim_ticks 29561 # Number of ticks simulated final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 249798 # Simulator tick rate (ticks/s) -host_mem_usage 387096 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 198957 # Simulator tick rate (ticks/s) +host_mem_usage 389156 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory @@ -262,39 +262,39 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1027 -system.ruby.outstanding_req_hist::mean 15.566699 -system.ruby.outstanding_req_hist::gmean 15.456992 -system.ruby.outstanding_req_hist::stdev 1.265135 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.49% | 3 0.29% 0.78% | 3 0.29% 1.07% | 6 0.58% 1.66% | 3 0.29% 1.95% | 271 26.39% 28.33% | 736 71.67% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1027 -system.ruby.latency_hist::bucket_size 128 -system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 1012 -system.ruby.latency_hist::mean 452.030632 -system.ruby.latency_hist::gmean 221.913062 -system.ruby.latency_hist::stdev 245.259624 -system.ruby.latency_hist | 227 22.43% 22.43% | 13 1.28% 23.72% | 6 0.59% 24.31% | 123 12.15% 36.46% | 525 51.88% 88.34% | 73 7.21% 95.55% | 35 3.46% 99.01% | 10 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 1012 -system.ruby.hit_latency_hist::bucket_size 64 -system.ruby.hit_latency_hist::max_bucket 639 -system.ruby.hit_latency_hist::samples 140 -system.ruby.hit_latency_hist::mean 75.100000 -system.ruby.hit_latency_hist::gmean 3.808266 -system.ruby.hit_latency_hist::stdev 173.693574 -system.ruby.hit_latency_hist | 117 83.57% 83.57% | 3 2.14% 85.71% | 1 0.71% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 4 2.86% 89.29% | 5 3.57% 92.86% | 8 5.71% 98.57% | 2 1.43% 100.00% -system.ruby.hit_latency_hist::total 140 -system.ruby.miss_latency_hist::bucket_size 128 -system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 872 -system.ruby.miss_latency_hist::mean 512.547018 -system.ruby.miss_latency_hist::gmean 426.213857 -system.ruby.miss_latency_hist::stdev 196.222062 -system.ruby.miss_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 872 -system.ruby.Directory.incomplete_times 872 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 1027 +system.ruby.outstanding_req_hist_seqr::mean 15.566699 +system.ruby.outstanding_req_hist_seqr::gmean 15.456992 +system.ruby.outstanding_req_hist_seqr::stdev 1.265135 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.49% | 3 0.29% 0.78% | 3 0.29% 1.07% | 6 0.58% 1.66% | 3 0.29% 1.95% | 271 26.39% 28.33% | 736 71.67% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1027 +system.ruby.latency_hist_seqr::bucket_size 128 +system.ruby.latency_hist_seqr::max_bucket 1279 +system.ruby.latency_hist_seqr::samples 1012 +system.ruby.latency_hist_seqr::mean 452.030632 +system.ruby.latency_hist_seqr::gmean 221.913062 +system.ruby.latency_hist_seqr::stdev 245.259624 +system.ruby.latency_hist_seqr | 227 22.43% 22.43% | 13 1.28% 23.72% | 6 0.59% 24.31% | 123 12.15% 36.46% | 525 51.88% 88.34% | 73 7.21% 95.55% | 35 3.46% 99.01% | 10 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 1012 +system.ruby.hit_latency_hist_seqr::bucket_size 64 +system.ruby.hit_latency_hist_seqr::max_bucket 639 +system.ruby.hit_latency_hist_seqr::samples 140 +system.ruby.hit_latency_hist_seqr::mean 75.100000 +system.ruby.hit_latency_hist_seqr::gmean 3.808266 +system.ruby.hit_latency_hist_seqr::stdev 173.693574 +system.ruby.hit_latency_hist_seqr | 117 83.57% 83.57% | 3 2.14% 85.71% | 1 0.71% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 4 2.86% 89.29% | 5 3.57% 92.86% | 8 5.71% 98.57% | 2 1.43% 100.00% +system.ruby.hit_latency_hist_seqr::total 140 +system.ruby.miss_latency_hist_seqr::bucket_size 128 +system.ruby.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.miss_latency_hist_seqr::samples 872 +system.ruby.miss_latency_hist_seqr::mean 512.547018 +system.ruby.miss_latency_hist_seqr::gmean 426.213857 +system.ruby.miss_latency_hist_seqr::stdev 196.222062 +system.ruby.miss_latency_hist_seqr | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 872 +system.ruby.Directory.incomplete_times_seqr 872 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -415,185 +415,185 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56952 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6952 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6968 -system.ruby.LD.latency_hist::bucket_size 128 -system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 43 -system.ruby.LD.latency_hist::mean 511.511628 -system.ruby.LD.latency_hist::gmean 293.373548 -system.ruby.LD.latency_hist::stdev 216.139767 -system.ruby.LD.latency_hist | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 7 16.28% 30.23% | 23 53.49% 83.72% | 5 11.63% 95.35% | 1 2.33% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 43 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 4 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 4 -system.ruby.LD.miss_latency_hist::bucket_size 128 -system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 39 -system.ruby.LD.miss_latency_hist::mean 563.871795 -system.ruby.LD.miss_latency_hist::gmean 525.399638 -system.ruby.LD.miss_latency_hist::stdev 146.240462 -system.ruby.LD.miss_latency_hist | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 39 -system.ruby.ST.latency_hist::bucket_size 128 -system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 910 -system.ruby.ST.latency_hist::mean 473.924176 -system.ruby.ST.latency_hist::gmean 243.035413 -system.ruby.ST.latency_hist::stdev 232.681347 -system.ruby.ST.latency_hist | 166 18.24% 18.24% | 11 1.21% 19.45% | 6 0.66% 20.11% | 116 12.75% 32.86% | 500 54.95% 87.80% | 68 7.47% 95.27% | 34 3.74% 99.01% | 9 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 910 -system.ruby.ST.hit_latency_hist::bucket_size 64 -system.ruby.ST.hit_latency_hist::max_bucket 639 -system.ruby.ST.hit_latency_hist::samples 126 -system.ruby.ST.hit_latency_hist::mean 74.587302 -system.ruby.ST.hit_latency_hist::gmean 3.636852 -system.ruby.ST.hit_latency_hist::stdev 172.646982 -system.ruby.ST.hit_latency_hist | 105 83.33% 83.33% | 3 2.38% 85.71% | 1 0.79% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 4 3.17% 89.68% | 5 3.97% 93.65% | 6 4.76% 98.41% | 2 1.59% 100.00% -system.ruby.ST.hit_latency_hist::total 126 -system.ruby.ST.miss_latency_hist::bucket_size 128 -system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 784 -system.ruby.ST.miss_latency_hist::mean 538.103316 -system.ruby.ST.miss_latency_hist::gmean 477.489826 -system.ruby.ST.miss_latency_hist::stdev 168.250948 -system.ruby.ST.miss_latency_hist | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 784 -system.ruby.IFETCH.latency_hist::bucket_size 16 -system.ruby.IFETCH.latency_hist::max_bucket 159 -system.ruby.IFETCH.latency_hist::samples 57 -system.ruby.IFETCH.latency_hist::mean 55 -system.ruby.IFETCH.latency_hist::gmean 40.845512 -system.ruby.IFETCH.latency_hist::stdev 30.808162 -system.ruby.IFETCH.latency_hist | 8 14.04% 14.04% | 6 10.53% 24.56% | 1 1.75% 26.32% | 27 47.37% 73.68% | 9 15.79% 89.47% | 3 5.26% 94.74% | 1 1.75% 96.49% | 0 0.00% 96.49% | 0 0.00% 96.49% | 2 3.51% 100.00% -system.ruby.IFETCH.latency_hist::total 57 -system.ruby.IFETCH.hit_latency_hist::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist::samples 8 -system.ruby.IFETCH.hit_latency_hist::mean 7.250000 -system.ruby.IFETCH.hit_latency_hist::gmean 4.475797 -system.ruby.IFETCH.hit_latency_hist::stdev 5.175492 -system.ruby.IFETCH.hit_latency_hist | 3 37.50% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 5 62.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 8 -system.ruby.IFETCH.miss_latency_hist::bucket_size 16 -system.ruby.IFETCH.miss_latency_hist::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist::samples 49 -system.ruby.IFETCH.miss_latency_hist::mean 62.795918 -system.ruby.IFETCH.miss_latency_hist::gmean 58.603527 -system.ruby.IFETCH.miss_latency_hist::stdev 25.717196 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 49 -system.ruby.FLUSH.latency_hist::bucket_size 64 -system.ruby.FLUSH.latency_hist::max_bucket 639 -system.ruby.FLUSH.latency_hist::samples 2 -system.ruby.FLUSH.latency_hist::mean 527 -system.ruby.FLUSH.latency_hist::gmean 526.885187 -system.ruby.FLUSH.latency_hist::stdev 15.556349 -system.ruby.FLUSH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.latency_hist::total 2 -system.ruby.FLUSH.hit_latency_hist::bucket_size 64 -system.ruby.FLUSH.hit_latency_hist::max_bucket 639 -system.ruby.FLUSH.hit_latency_hist::samples 2 -system.ruby.FLUSH.hit_latency_hist::mean 527 -system.ruby.FLUSH.hit_latency_hist::gmean 526.885187 -system.ruby.FLUSH.hit_latency_hist::stdev 15.556349 -system.ruby.FLUSH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.hit_latency_hist::total 2 -system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 64 -system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 639 -system.ruby.L1Cache.hit_mach_latency_hist::samples 101 -system.ruby.L1Cache.hit_mach_latency_hist::mean 11.415842 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1.132128 -system.ruby.L1Cache.hit_mach_latency_hist::stdev 73.663867 -system.ruby.L1Cache.hit_mach_latency_hist | 99 98.02% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 2 1.98% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 101 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 64 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 639 -system.ruby.L2Cache.hit_mach_latency_hist::samples 39 -system.ruby.L2Cache.hit_mach_latency_hist::mean 240.025641 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 88.122529 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 239.543259 -system.ruby.L2Cache.hit_mach_latency_hist | 18 46.15% 46.15% | 3 7.69% 53.85% | 1 2.56% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 4 10.26% 66.67% | 5 12.82% 79.49% | 6 15.38% 94.87% | 2 5.13% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 39 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 128 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist::samples 872 -system.ruby.Directory.miss_mach_latency_hist::mean 512.547018 -system.ruby.Directory.miss_mach_latency_hist::gmean 426.213857 -system.ruby.Directory.miss_mach_latency_hist::stdev 196.222062 -system.ruby.Directory.miss_mach_latency_hist | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 872 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 39 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 563.871795 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 525.399638 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 146.240462 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 39 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 92 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 92 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 639 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 34 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 273.705882 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 119.669415 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 238.660724 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 13 38.24% 38.24% | 3 8.82% 47.06% | 1 2.94% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 11.76% 61.76% | 5 14.71% 76.47% | 6 17.65% 94.12% | 2 5.88% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 34 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 784 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 538.103316 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 477.489826 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 168.250948 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 784 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 3 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 3 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 5 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 5 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 62.795918 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.603527 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 25.717196 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 64 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 639 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 2 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 527 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 526.885187 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 15.556349 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 2 +system.ruby.LD.latency_hist_seqr::bucket_size 128 +system.ruby.LD.latency_hist_seqr::max_bucket 1279 +system.ruby.LD.latency_hist_seqr::samples 43 +system.ruby.LD.latency_hist_seqr::mean 511.511628 +system.ruby.LD.latency_hist_seqr::gmean 293.373548 +system.ruby.LD.latency_hist_seqr::stdev 216.139767 +system.ruby.LD.latency_hist_seqr | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 7 16.28% 30.23% | 23 53.49% 83.72% | 5 11.63% 95.35% | 1 2.33% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 43 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 4 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 4 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_seqr::samples 39 +system.ruby.LD.miss_latency_hist_seqr::mean 563.871795 +system.ruby.LD.miss_latency_hist_seqr::gmean 525.399638 +system.ruby.LD.miss_latency_hist_seqr::stdev 146.240462 +system.ruby.LD.miss_latency_hist_seqr | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 39 +system.ruby.ST.latency_hist_seqr::bucket_size 128 +system.ruby.ST.latency_hist_seqr::max_bucket 1279 +system.ruby.ST.latency_hist_seqr::samples 910 +system.ruby.ST.latency_hist_seqr::mean 473.924176 +system.ruby.ST.latency_hist_seqr::gmean 243.035413 +system.ruby.ST.latency_hist_seqr::stdev 232.681347 +system.ruby.ST.latency_hist_seqr | 166 18.24% 18.24% | 11 1.21% 19.45% | 6 0.66% 20.11% | 116 12.75% 32.86% | 500 54.95% 87.80% | 68 7.47% 95.27% | 34 3.74% 99.01% | 9 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 910 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 +system.ruby.ST.hit_latency_hist_seqr::samples 126 +system.ruby.ST.hit_latency_hist_seqr::mean 74.587302 +system.ruby.ST.hit_latency_hist_seqr::gmean 3.636852 +system.ruby.ST.hit_latency_hist_seqr::stdev 172.646982 +system.ruby.ST.hit_latency_hist_seqr | 105 83.33% 83.33% | 3 2.38% 85.71% | 1 0.79% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 4 3.17% 89.68% | 5 3.97% 93.65% | 6 4.76% 98.41% | 2 1.59% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 126 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.miss_latency_hist_seqr::samples 784 +system.ruby.ST.miss_latency_hist_seqr::mean 538.103316 +system.ruby.ST.miss_latency_hist_seqr::gmean 477.489826 +system.ruby.ST.miss_latency_hist_seqr::stdev 168.250948 +system.ruby.ST.miss_latency_hist_seqr | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 784 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 16 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 159 +system.ruby.IFETCH.latency_hist_seqr::samples 57 +system.ruby.IFETCH.latency_hist_seqr::mean 55 +system.ruby.IFETCH.latency_hist_seqr::gmean 40.845512 +system.ruby.IFETCH.latency_hist_seqr::stdev 30.808162 +system.ruby.IFETCH.latency_hist_seqr | 8 14.04% 14.04% | 6 10.53% 24.56% | 1 1.75% 26.32% | 27 47.37% 73.68% | 9 15.79% 89.47% | 3 5.26% 94.74% | 1 1.75% 96.49% | 0 0.00% 96.49% | 0 0.00% 96.49% | 2 3.51% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 57 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 8 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 7.250000 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 4.475797 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 5.175492 +system.ruby.IFETCH.hit_latency_hist_seqr | 3 37.50% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 5 62.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 8 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 16 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 159 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 49 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.795918 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.603527 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.717196 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 49 +system.ruby.FLUSH.latency_hist_seqr::bucket_size 64 +system.ruby.FLUSH.latency_hist_seqr::max_bucket 639 +system.ruby.FLUSH.latency_hist_seqr::samples 2 +system.ruby.FLUSH.latency_hist_seqr::mean 527 +system.ruby.FLUSH.latency_hist_seqr::gmean 526.885187 +system.ruby.FLUSH.latency_hist_seqr::stdev 15.556349 +system.ruby.FLUSH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.latency_hist_seqr::total 2 +system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size 64 +system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket 639 +system.ruby.FLUSH.hit_latency_hist_seqr::samples 2 +system.ruby.FLUSH.hit_latency_hist_seqr::mean 527 +system.ruby.FLUSH.hit_latency_hist_seqr::gmean 526.885187 +system.ruby.FLUSH.hit_latency_hist_seqr::stdev 15.556349 +system.ruby.FLUSH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.hit_latency_hist_seqr::total 2 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 64 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 639 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 101 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 11.415842 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1.132128 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev 73.663867 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 99 98.02% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 2 1.98% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 101 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 64 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 639 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 39 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 240.025641 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 88.122529 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 239.543259 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 18 46.15% 46.15% | 3 7.69% 53.85% | 1 2.56% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 4 10.26% 66.67% | 5 12.82% 79.49% | 6 15.38% 94.87% | 2 5.13% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 39 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 872 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 512.547018 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 426.213857 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 196.222062 +system.ruby.Directory.miss_mach_latency_hist_seqr | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 872 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 4 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 4 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 39 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 563.871795 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 525.399638 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 146.240462 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 39 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 92 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 92 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 34 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 273.705882 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 119.669415 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 238.660724 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 13 38.24% 38.24% | 3 8.82% 47.06% | 1 2.94% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 11.76% 61.76% | 5 14.71% 76.47% | 6 17.65% 94.12% | 2 5.88% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 34 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 784 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 538.103316 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 477.489826 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 168.250948 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 784 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 3 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 3 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 5 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 5 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 49 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.795918 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.603527 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.717196 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 49 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean 527 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 526.885187 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev 15.556349 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::total 2 system.ruby.Directory_Controller.GETX 785 0.00% 0.00% system.ruby.Directory_Controller.GETS 90 0.00% 0.00% system.ruby.Directory_Controller.PUT 1118 0.00% 0.00% diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini index b74242b8f..736270382 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -271,6 +272,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -332,12 +334,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.ruby.clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true ruby_system=system.ruby @@ -936,6 +940,7 @@ randomization=false type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 80d0304fa..e720ac2ac 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:29 -gem5 executing on zizzer, pid 26182 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:27 +gem5 executing on zizzer, pid 34085 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 9784c36a4..122a8ae41 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu sim_ticks 37741 # Number of ticks simulated final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 420656 # Simulator tick rate (ticks/s) -host_mem_usage 384732 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 330031 # Simulator tick rate (ticks/s) +host_mem_usage 387076 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory @@ -267,39 +267,39 @@ system.ruby.delayHist::mean 0.196532 # de system.ruby.delayHist::stdev 1.062331 # delay histogram for all message system.ruby.delayHist | 1839 96.64% 96.64% | 0 0.00% 96.64% | 2 0.11% 96.74% | 0 0.00% 96.74% | 1 0.05% 96.79% | 0 0.00% 96.79% | 61 3.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 1903 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 2 -system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1005 -system.ruby.outstanding_req_hist::mean 15.609950 -system.ruby.outstanding_req_hist::gmean 15.502410 -system.ruby.outstanding_req_hist::stdev 1.236521 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.09% | 3 0.30% 1.39% | 4 0.40% 1.79% | 233 23.18% 24.98% | 754 75.02% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1005 -system.ruby.latency_hist::bucket_size 128 -system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 992 -system.ruby.latency_hist::mean 594.351815 -system.ruby.latency_hist::gmean 584.578373 -system.ruby.latency_hist::stdev 96.099439 -system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.91% 1.11% | 6 0.60% 1.71% | 111 11.19% 12.90% | 654 65.93% 78.83% | 154 15.52% 94.35% | 49 4.94% 99.29% | 7 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 992 -system.ruby.hit_latency_hist::bucket_size 128 -system.ruby.hit_latency_hist::max_bucket 1279 -system.ruby.hit_latency_hist::samples 39 -system.ruby.hit_latency_hist::mean 492.692308 -system.ruby.hit_latency_hist::gmean 488.844837 -system.ruby.hit_latency_hist::stdev 62.931522 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.56% 2.56% | 22 56.41% 58.97% | 15 38.46% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 39 -system.ruby.miss_latency_hist::bucket_size 128 -system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 953 -system.ruby.miss_latency_hist::mean 598.512067 -system.ruby.miss_latency_hist::gmean 588.872583 -system.ruby.miss_latency_hist::stdev 94.945507 -system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 953 -system.ruby.Directory.incomplete_times 953 +system.ruby.outstanding_req_hist_seqr::bucket_size 2 +system.ruby.outstanding_req_hist_seqr::max_bucket 19 +system.ruby.outstanding_req_hist_seqr::samples 1005 +system.ruby.outstanding_req_hist_seqr::mean 15.609950 +system.ruby.outstanding_req_hist_seqr::gmean 15.502410 +system.ruby.outstanding_req_hist_seqr::stdev 1.236521 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.09% | 3 0.30% 1.39% | 4 0.40% 1.79% | 233 23.18% 24.98% | 754 75.02% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1005 +system.ruby.latency_hist_seqr::bucket_size 128 +system.ruby.latency_hist_seqr::max_bucket 1279 +system.ruby.latency_hist_seqr::samples 992 +system.ruby.latency_hist_seqr::mean 594.351815 +system.ruby.latency_hist_seqr::gmean 584.578373 +system.ruby.latency_hist_seqr::stdev 96.099439 +system.ruby.latency_hist_seqr | 2 0.20% 0.20% | 9 0.91% 1.11% | 6 0.60% 1.71% | 111 11.19% 12.90% | 654 65.93% 78.83% | 154 15.52% 94.35% | 49 4.94% 99.29% | 7 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 992 +system.ruby.hit_latency_hist_seqr::bucket_size 128 +system.ruby.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.hit_latency_hist_seqr::samples 39 +system.ruby.hit_latency_hist_seqr::mean 492.692308 +system.ruby.hit_latency_hist_seqr::gmean 488.844837 +system.ruby.hit_latency_hist_seqr::stdev 62.931522 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.56% 2.56% | 22 56.41% 58.97% | 15 38.46% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 39 +system.ruby.miss_latency_hist_seqr::bucket_size 128 +system.ruby.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.miss_latency_hist_seqr::samples 953 +system.ruby.miss_latency_hist_seqr::mean 598.512067 +system.ruby.miss_latency_hist_seqr::gmean 588.872583 +system.ruby.miss_latency_hist_seqr::stdev 94.945507 +system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 953 +system.ruby.Directory.incomplete_times_seqr 953 system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses @@ -385,102 +385,102 @@ system.ruby.delayVCHist.vnet_2::mean 0.393684 # de system.ruby.delayVCHist.vnet_2::stdev 1.477888 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 886 93.26% 93.26% | 0 0.00% 93.26% | 2 0.21% 93.47% | 0 0.00% 93.47% | 1 0.11% 93.58% | 0 0.00% 93.58% | 61 6.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 950 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 128 -system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 50 -system.ruby.LD.latency_hist::mean 620.660000 -system.ruby.LD.latency_hist::gmean 616.355454 -system.ruby.LD.latency_hist::stdev 75.297399 -system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 50 -system.ruby.LD.miss_latency_hist::bucket_size 128 -system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 50 -system.ruby.LD.miss_latency_hist::mean 620.660000 -system.ruby.LD.miss_latency_hist::gmean 616.355454 -system.ruby.LD.miss_latency_hist::stdev 75.297399 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 50 -system.ruby.ST.latency_hist::bucket_size 128 -system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 892 -system.ruby.ST.latency_hist::mean 591.263453 -system.ruby.ST.latency_hist::gmean 581.152835 -system.ruby.ST.latency_hist::stdev 96.524225 -system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.01% 1.23% | 6 0.67% 1.91% | 103 11.55% 13.45% | 591 66.26% 79.71% | 135 15.13% 94.84% | 39 4.37% 99.22% | 7 0.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 892 -system.ruby.ST.hit_latency_hist::bucket_size 128 -system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 38 -system.ruby.ST.hit_latency_hist::mean 491.526316 -system.ruby.ST.hit_latency_hist::gmean 487.637688 -system.ruby.ST.hit_latency_hist::stdev 63.347918 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 22 57.89% 60.53% | 14 36.84% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 38 -system.ruby.ST.miss_latency_hist::bucket_size 128 -system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 854 -system.ruby.ST.miss_latency_hist::mean 595.701405 -system.ruby.ST.miss_latency_hist::gmean 585.707367 -system.ruby.ST.miss_latency_hist::stdev 95.367967 -system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 854 -system.ruby.IFETCH.latency_hist::bucket_size 128 -system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 50 -system.ruby.IFETCH.latency_hist::mean 623.140000 -system.ruby.IFETCH.latency_hist::gmean 615.727796 -system.ruby.IFETCH.latency_hist::stdev 99.820044 -system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.00% 10.00% | 30 60.00% 70.00% | 9 18.00% 88.00% | 6 12.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 50 -system.ruby.IFETCH.hit_latency_hist::bucket_size 64 -system.ruby.IFETCH.hit_latency_hist::max_bucket 639 -system.ruby.IFETCH.hit_latency_hist::samples 1 -system.ruby.IFETCH.hit_latency_hist::mean 537 -system.ruby.IFETCH.hit_latency_hist::gmean 537.000000 -system.ruby.IFETCH.hit_latency_hist::stdev nan -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 1 -system.ruby.IFETCH.miss_latency_hist::bucket_size 128 -system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 49 -system.ruby.IFETCH.miss_latency_hist::mean 624.897959 -system.ruby.IFETCH.miss_latency_hist::gmean 617.449297 -system.ruby.IFETCH.miss_latency_hist::stdev 100.069402 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 49 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 128 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist::samples 953 -system.ruby.Directory.miss_mach_latency_hist::mean 598.512067 -system.ruby.Directory.miss_mach_latency_hist::gmean 588.872583 -system.ruby.Directory.miss_mach_latency_hist::stdev 94.945507 -system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 953 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 50 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 620.660000 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 616.355454 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 75.297399 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 50 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 854 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 595.701405 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 585.707367 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 95.367967 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 854 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 624.897959 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 617.449297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 100.069402 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49 +system.ruby.LD.latency_hist_seqr::bucket_size 128 +system.ruby.LD.latency_hist_seqr::max_bucket 1279 +system.ruby.LD.latency_hist_seqr::samples 50 +system.ruby.LD.latency_hist_seqr::mean 620.660000 +system.ruby.LD.latency_hist_seqr::gmean 616.355454 +system.ruby.LD.latency_hist_seqr::stdev 75.297399 +system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 50 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_seqr::samples 50 +system.ruby.LD.miss_latency_hist_seqr::mean 620.660000 +system.ruby.LD.miss_latency_hist_seqr::gmean 616.355454 +system.ruby.LD.miss_latency_hist_seqr::stdev 75.297399 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 50 +system.ruby.ST.latency_hist_seqr::bucket_size 128 +system.ruby.ST.latency_hist_seqr::max_bucket 1279 +system.ruby.ST.latency_hist_seqr::samples 892 +system.ruby.ST.latency_hist_seqr::mean 591.263453 +system.ruby.ST.latency_hist_seqr::gmean 581.152835 +system.ruby.ST.latency_hist_seqr::stdev 96.524225 +system.ruby.ST.latency_hist_seqr | 2 0.22% 0.22% | 9 1.01% 1.23% | 6 0.67% 1.91% | 103 11.55% 13.45% | 591 66.26% 79.71% | 135 15.13% 94.84% | 39 4.37% 99.22% | 7 0.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 892 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.hit_latency_hist_seqr::samples 38 +system.ruby.ST.hit_latency_hist_seqr::mean 491.526316 +system.ruby.ST.hit_latency_hist_seqr::gmean 487.637688 +system.ruby.ST.hit_latency_hist_seqr::stdev 63.347918 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 22 57.89% 60.53% | 14 36.84% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 38 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.miss_latency_hist_seqr::samples 854 +system.ruby.ST.miss_latency_hist_seqr::mean 595.701405 +system.ruby.ST.miss_latency_hist_seqr::gmean 585.707367 +system.ruby.ST.miss_latency_hist_seqr::stdev 95.367967 +system.ruby.ST.miss_latency_hist_seqr | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 854 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 128 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279 +system.ruby.IFETCH.latency_hist_seqr::samples 50 +system.ruby.IFETCH.latency_hist_seqr::mean 623.140000 +system.ruby.IFETCH.latency_hist_seqr::gmean 615.727796 +system.ruby.IFETCH.latency_hist_seqr::stdev 99.820044 +system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.00% 10.00% | 30 60.00% 70.00% | 9 18.00% 88.00% | 6 12.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 50 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 537 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 537.000000 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 49 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 624.897959 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 617.449297 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 100.069402 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 49 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 953 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 598.512067 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 588.872583 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 94.945507 +system.ruby.Directory.miss_mach_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 953 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 50 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 620.660000 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 616.355454 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 75.297399 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 50 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 854 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 595.701405 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 585.707367 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 95.367967 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 854 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 49 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 624.897959 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 617.449297 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 100.069402 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 49 system.ruby.Directory_Controller.GETX 953 0.00% 0.00% system.ruby.Directory_Controller.PUTX 950 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 953 0.00% 0.00% diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini index 1c3eb8444..7ca6b51f7 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout index f6358b402..cf720d597 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:23:08 -gem5 started Dec 11 2015 20:23:21 -gem5 executing on zizzer, pid 55322 -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl +gem5 compiled Jan 21 2016 14:20:17 +gem5 started Jan 21 2016 14:20:32 +gem5 executing on zizzer, pid 63117 +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 438149089..14d004205 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 4683886556 # Simulator tick rate (ticks/s) -host_mem_usage 202144 # Number of bytes of host memory used -host_seconds 21.35 # Real time elapsed on the host +host_tick_rate 4618007467 # Simulator tick rate (ticks/s) +host_mem_usage 202228 # Number of bytes of host memory used +host_seconds 21.65 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini index 0936865ed..08be6a107 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index dabb33d8a..38c82e1af 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:23:08 -gem5 started Dec 11 2015 20:23:21 -gem5 executing on zizzer, pid 55316 -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /z/atgutier/gem5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem +gem5 compiled Jan 21 2016 14:20:17 +gem5 started Jan 21 2016 14:20:32 +gem5 executing on zizzer, pid 63119 +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index 6a7ed28d3..710d324a6 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 15208030858 # Simulator tick rate (ticks/s) -host_mem_usage 204576 # Number of bytes of host memory used -host_seconds 6.58 # Real time elapsed on the host +host_tick_rate 15880275218 # Simulator tick rate (ticks/s) +host_mem_usage 204660 # Number of bytes of host memory used +host_seconds 6.30 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 965103cd9..831912ec7 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 49415ecf9..96d4044c7 100755 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:27 -gem5 executing on zizzer, pid 26136 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:03 +gem5 executing on zizzer, pid 34012 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 688d00d9f..46baca50d 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 999914 # Simulator instruction rate (inst/s) -host_op_rate 999914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 499957255 # Simulator tick rate (ticks/s) -host_mem_usage 224596 # Number of bytes of host memory used -host_seconds 91.91 # Real time elapsed on the host +host_inst_rate 1065115 # Simulator instruction rate (inst/s) +host_op_rate 1065115 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 532557762 # Simulator tick rate (ticks/s) +host_mem_usage 224960 # Number of bytes of host memory used +host_seconds 86.28 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 7b2d13d42..1e2092c81 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 21e2ba030..fc1844e03 100755 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 19:54:02 -gem5 started Dec 11 2015 19:54:29 -gem5 executing on zizzer, pid 26184 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing +gem5 compiled Jan 21 2016 13:49:21 +gem5 started Jan 21 2016 13:50:00 +gem5 executing on zizzer, pid 33964 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 6ab7e4d25..da47b432f 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118763 # Nu sim_ticks 118762761500 # Number of ticks simulated final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 510960 # Simulator instruction rate (inst/s) -host_op_rate 510960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 660293850 # Simulator tick rate (ticks/s) -host_mem_usage 234860 # Number of bytes of host memory used -host_seconds 179.86 # Real time elapsed on the host +host_inst_rate 546473 # Simulator instruction rate (inst/s) +host_op_rate 546472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 706184987 # Simulator tick rate (ticks/s) +host_mem_usage 235092 # Number of bytes of host memory used +host_seconds 168.18 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 74c17abe1..a38cc9763 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout index 51c0d90e7..a3aed918d 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:10 -gem5 executing on zizzer, pid 11547 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:39 +gem5 executing on zizzer, pid 20766 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index df22b2153..177b96346 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 676246 # Simulator instruction rate (inst/s) -host_op_rate 712872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 390858173 # Simulator tick rate (ticks/s) -host_mem_usage 241720 # Number of bytes of host memory used -host_seconds 254.82 # Real time elapsed on the host +host_inst_rate 695621 # Simulator instruction rate (inst/s) +host_op_rate 733297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 402056906 # Simulator tick rate (ticks/s) +host_mem_usage 242228 # Number of bytes of host memory used +host_seconds 247.72 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 9f4a8940a..f94d22eff 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout index 54bf73b2a..0a9d1a43d 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:46:46 -gem5 started Dec 11 2015 20:47:11 -gem5 executing on zizzer, pid 11563 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing +gem5 compiled Jan 21 2016 14:45:42 +gem5 started Jan 21 2016 14:46:22 +gem5 executing on zizzer, pid 20735 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6ded2a08d..d7fd446da 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497825 # Simulator instruction rate (inst/s) -host_op_rate 524833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 666878578 # Simulator tick rate (ticks/s) -host_mem_usage 251744 # Number of bytes of host memory used -host_seconds 345.19 # Real time elapsed on the host +host_inst_rate 435347 # Simulator instruction rate (inst/s) +host_op_rate 458966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583184688 # Simulator tick rate (ticks/s) +host_mem_usage 252480 # Number of bytes of host memory used +host_seconds 394.73 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index a8b481426..4e8cfbb92 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 10a467e72..51e17a4c6 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:42 -gem5 executing on zizzer, pid 902 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:26 +gem5 executing on zizzer, pid 8722 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 9e7313938..cdb442c20 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1006317 # Simulator instruction rate (inst/s) -host_op_rate 1006319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 503162156 # Simulator tick rate (ticks/s) -host_mem_usage 224668 # Number of bytes of host memory used -host_seconds 192.23 # Real time elapsed on the host +host_inst_rate 966666 # Simulator instruction rate (inst/s) +host_op_rate 966667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 483336155 # Simulator tick rate (ticks/s) +host_mem_usage 225024 # Number of bytes of host memory used +host_seconds 200.12 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index 3df38f24a..250899e0a 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout index 56d6700a6..d9abfd9b9 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:33:09 -gem5 started Dec 11 2015 20:33:37 -gem5 executing on zizzer, pid 875 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing +gem5 compiled Jan 21 2016 14:30:54 +gem5 started Jan 21 2016 14:31:24 +gem5 executing on zizzer, pid 8707 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 32a80dbb1..9e9ac48d5 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270600 # Nu sim_ticks 270599529500 # Number of ticks simulated final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523713 # Simulator instruction rate (inst/s) -host_op_rate 523713 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 732594560 # Simulator tick rate (ticks/s) -host_mem_usage 234928 # Number of bytes of host memory used -host_seconds 369.37 # Real time elapsed on the host +host_inst_rate 568132 # Simulator instruction rate (inst/s) +host_op_rate 568133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 794730164 # Simulator tick rate (ticks/s) +host_mem_usage 235264 # Number of bytes of host memory used +host_seconds 340.49 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 28b619736..ce2e451b7 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout index 8bffb815b..5842ab9bc 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:47 -gem5 executing on zizzer, pid 10151 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:53 +gem5 executing on zizzer, pid 17904 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 308403145..5a46e9bad 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 611209 # Simulator instruction rate (inst/s) -host_op_rate 1024442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 608071542 # Simulator tick rate (ticks/s) -host_mem_usage 268844 # Number of bytes of host memory used -host_seconds 216.08 # Real time elapsed on the host +host_inst_rate 550181 # Simulator instruction rate (inst/s) +host_op_rate 922154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 547357033 # Simulator tick rate (ticks/s) +host_mem_usage 269224 # Number of bytes of host memory used +host_seconds 240.05 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 619fe58cb..3014dab83 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout index a40514988..985e23889 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2015 20:42:59 -gem5 started Dec 11 2015 20:43:46 -gem5 executing on zizzer, pid 10130 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /z/atgutier/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing +gem5 compiled Jan 21 2016 14:41:03 +gem5 started Jan 21 2016 14:41:53 +gem5 executing on zizzer, pid 17898 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index db06e6b3c..01cb3bdc8 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250987 # Nu sim_ticks 250987138500 # Number of ticks simulated final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309334 # Simulator instruction rate (inst/s) -host_op_rate 518472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 587856087 # Simulator tick rate (ticks/s) -host_mem_usage 279244 # Number of bytes of host memory used -host_seconds 426.95 # Real time elapsed on the host +host_inst_rate 290260 # Simulator instruction rate (inst/s) +host_op_rate 486501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 551606975 # Simulator tick rate (ticks/s) +host_mem_usage 279340 # Number of bytes of host memory used +host_seconds 455.01 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts |