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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-03-30 15:05:58 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-03-30 15:05:58 -0500 |
| commit | 13608a9b85a60982a9fa0ebee38a1d15c0ea5fc5 (patch) | |
| tree | 4780f627d171ca785dd4efe4b15e78b89a1d62cb | |
| parent | cda8f99a5664a79f94b9ce84a4c6f456cf0ea976 (diff) | |
| download | gem5-13608a9b85a60982a9fa0ebee38a1d15c0ea5fc5.tar.xz | |
Rework the way the prefetcher is used. Now we copy the request from the prefetch queue and into the mq when issued
objects/BaseCache.mpy:
Add some parameters for prefetcher
--HG--
extra : convert_revision : 1a2e6d2ce5359fab0a4d5d4639a701131101d68c
| -rw-r--r-- | objects/BaseCache.mpy | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 98a422e30..314a4efda 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -36,3 +36,7 @@ simobj BaseCache(BaseMem): two_queue = Param.Bool(False, "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") + use_prefetcher = Param.Bool(False, + "wheter you are using the hardware prefetcher") + prefetcher_size = Param.Int(100, + "Number of entries in the harware prefetch queue") |