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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-27 18:30:58 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-27 18:30:58 -0700 |
| commit | 13b1f7231c8a30fd0a7c7a5b0df6ba4c75430943 (patch) | |
| tree | 6377f5c33e86dd3a3f3754bde721a39bc7c07a81 | |
| parent | 703d10705ce4e5db0b388853ab8699e3c9d49835 (diff) | |
| download | gem5-13b1f7231c8a30fd0a7c7a5b0df6ba4c75430943.tar.xz | |
Address Translation: Make the Generic TLB only compile in SE mode.
--HG--
extra : convert_revision : 7eb9a78480174f754f51f75983ee5a1b31280bd3
| -rw-r--r-- | src/sim/SConscript | 2 | ||||
| -rw-r--r-- | src/sim/tlb.hh | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript index 1753b33c0..b0af4c795 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -48,12 +48,12 @@ Source('simulate.cc') Source('startup.cc') Source('stat_control.cc') Source('system.cc') -Source('tlb.cc') if env['FULL_SYSTEM']: Source('arguments.cc') Source('pseudo_inst.cc') else: + Source('tlb.cc') SimObject('Process.py') Source('process.cc') diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index b54eb501f..c4c171015 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -67,7 +67,7 @@ class GenericTLB : public GenericTLBBase if(doSizeCheck && !isPowerOf2(size)) panic("Invalid request size!\n"); if (doAlignmentCheck && ((size - 1) & paddr)) - return Fault(new GenericAlignmentFault(paddr)); + return new GenericAlignmentFault(paddr); return NoFault; } |