diff options
| author | Kevin Lim <ktlim@umich.edu> | 2005-02-04 18:25:49 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-02-04 18:25:49 -0500 |
| commit | 1e7a744c09d0bde70e0f83179fdf4d6059585e4b (patch) | |
| tree | 9bbc7713c4bb79abb3f76b07547d8822f0557caa | |
| parent | c389c2e327cc3ee1c988855b05505660c6670172 (diff) | |
| parent | b78d7c2f16dac11ed468de45a088a362605c6493 (diff) | |
| download | gem5-1e7a744c09d0bde70e0f83179fdf4d6059585e4b.tar.xz | |
Hand merge
--HG--
extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
77 files changed, 779 insertions, 410 deletions
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc index 67bb0ab3b..ba4b1d07e 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/alpha_linux_process.cc @@ -26,24 +26,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include <dirent.h> #include <errno.h> -#include <unistd.h> #include <fcntl.h> // for host open() flags -#include <sys/types.h> -#include <sys/stat.h> #include <string.h> // for memset() -#include <dirent.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> -#include "sim/host.hh" #include "cpu/base_cpu.hh" -#include "mem/functional_mem/functional_memory.hh" -#include "sim/process.hh" #include "cpu/exec_context.hh" +#include "mem/functional_mem/functional_memory.hh" #include "sim/fake_syscall.hh" +#include "sim/host.hh" +#include "sim/process.hh" #include "sim/sim_events.hh" -#include "sim/syscall_emul.hh" #include "arch/alpha/alpha_common_syscall_emul.hh" +#include "sim/syscall_emul.hh" #include "sim/universe.hh" // for curTick & ticksPerSecond #include "arch/alpha/alpha_linux_process.hh" diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index fbd4cfe60..e7d0d68ce 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -790,48 +790,14 @@ output header {{ protected: /// Constructor MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr<AlphaISA> _eaCompPtr, - StaticInstPtr<AlphaISA> _memAccPtr) + StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, + StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; - - - /** - * Base class for "fake" effective-address computation - * instructions returnded by eaCompInst(). - */ - class EACompBase : public AlphaStaticInst - { - public: - /// Constructor - EACompBase(MachInst machInst) - : AlphaStaticInst("(eacomp)", machInst, IntAluOp) - { - } - - %(BasicExecDeclare)s - }; - - /** - * Base class for "fake" memory-access instructions returnded by - * memAccInst(). - */ - class MemAccBase : public AlphaStaticInst - { - public: - /// Constructor - MemAccBase(MachInst machInst, OpClass __opClass) - : AlphaStaticInst("(memacc)", machInst, __opClass) - { - } - - %(BasicExecDeclare)s - }; - }}; @@ -850,21 +816,6 @@ output decoder {{ } }}; -output exec {{ - Fault - EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute eacomp"); - } - - Fault - MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute memacc"); - } -}}; - - def format LoadAddress(code) {{ iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) header_output = BasicDeclare.subst(iop) @@ -885,21 +836,25 @@ def template LoadStoreDeclare {{ /** * "Fake" effective address computation class for "%(mnemonic)s". */ - class EAComp : public EACompBase + class EAComp : public %(base_class)s { public: /// Constructor EAComp(MachInst machInst); + + %(BasicExecDeclare)s }; /** * "Fake" memory access instruction class for "%(mnemonic)s". */ - class MemAcc : public MemAccBase + class MemAcc : public %(base_class)s { public: /// Constructor MemAcc(MachInst machInst); + + %(BasicExecDeclare)s }; public: @@ -912,14 +867,17 @@ def template LoadStoreDeclare {{ }}; def template LoadStoreConstructor {{ + /** TODO: change op_class to AddrGenOp or something (requires + * creating new member of OpClass enum in op_class.hh, updating + * config files, etc.). */ inline %(class_name)s::EAComp::EAComp(MachInst machInst) - : EACompBase(machInst) + : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) { %(ea_constructor)s; } inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) - : MemAccBase(machInst, %(op_class)s) + : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) { %(memacc_constructor)s; } @@ -932,6 +890,64 @@ def template LoadStoreConstructor {{ } }}; + +def template EACompExecute {{ + Fault + %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if (fault == No_Fault) { + %(op_wb)s; + xc->setEA(EA); + } + + return fault; + } +}}; + +def template MemAccExecute {{ + Fault + %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_nonmem_rd)s; + EA = xc->getEA(); + + if (fault == No_Fault) { + %(op_mem_rd)s; + %(code)s; + } + + if (fault == No_Fault) { + %(op_mem_wb)s; + } + + if (fault == No_Fault) { + %(postacc_code)s; + } + + if (fault == No_Fault) { + %(op_nonmem_wb)s; + } + + return fault; + } +}}; + + def template LoadStoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) @@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', # Would be nice to autogenerate this list, but oh well. valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE'] - inst_flags = [] - mem_flags = [] - for f in flags: - if f in valid_mem_flags: - mem_flags.append(f) - else: - inst_flags.append(f) + mem_flags = [f for f in flags if f in valid_mem_flags] + inst_flags = [f for f in flags if f not in valid_mem_flags] + + # add hook to get effective addresses into execution trace output. + ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' + # generate code block objects ea_cblk = CodeBlock(ea_code) memacc_cblk = CodeBlock(memacc_code) postacc_cblk = CodeBlock(postacc_code) + # Some CPU models execute the memory operation as an atomic unit, + # while others want to separate them into an effective address + # computation and a memory access operation. As a result, we need + # to generate three StaticInst objects. Note that the latter two + # are nested inside the larger "atomic" one. + + # generate InstObjParams for EAComp object + ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags) + + # generate InstObjParams for MemAcc object + memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags) + # in the split execution model, the MemAcc portion is responsible + # for the post-access code. + memacc_iop.postacc_code = postacc_cblk.code + + # generate InstObjParams for unified execution cblk = CodeBlock(ea_code + memacc_code + postacc_code) iop = InstObjParams(name, Name, base_class, cblk, inst_flags) @@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', iop.memacc_code = memacc_cblk.code iop.postacc_code = postacc_cblk.code - mem_flags = string.join(mem_flags, '|') - if mem_flags != '': - iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';' + if mem_flags: + s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + iop.constructor += s + memacc_iop.constructor += s # (header_output, decoder_output, decode_block, exec_output) return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop), - decode_template.subst(iop), exec_template.subst(iop)) + decode_template.subst(iop), + EACompExecute.subst(ea_iop) + + MemAccExecute.subst(memacc_iop) + + exec_template.subst(iop)) }}; @@ -1460,8 +1495,8 @@ output header {{ /// Constructor HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr<AlphaISA> _eaCompPtr, - StaticInstPtr<AlphaISA> _memAccPtr); + StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, + StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr); std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc index 95c85b45a..22d65638b 100644 --- a/arch/alpha/pseudo_inst.cc +++ b/arch/alpha/pseudo_inst.cc @@ -206,7 +206,7 @@ namespace AlphaPseudo void checkParams(); }; - Context context("PseudoInsts"); + Context context("pseudo_inst"); Param<bool> __quiesce(&context, "quiesce", "enable quiesce instructions", diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh index cd4bc547b..e955c67cf 100644 --- a/arch/alpha/vptr.hh +++ b/arch/alpha/vptr.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __VPTR_HH__ -#define __VPTR_HH__ +#ifndef __ARCH_ALPHA_VPTR_HH__ +#define __ARCH_ALPHA_VPTR_HH__ #include "arch/alpha/vtophys.hh" @@ -69,14 +69,15 @@ class VPtr const VPtr<T> &operator+=(int offset) { ptr += offset; - assert((ptr & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T) + < AlphaISA::PageBytes); return *this; } const VPtr<T> &operator=(Addr p) { - assert((p & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes); ptr = p; return *this; @@ -110,4 +111,4 @@ class VPtr } }; -#endif // __VPTR_HH__ +#endif // __ARCH_ALPHA_VPTR_HH__ diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 7228f99b6..8187cf188 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1213,10 +1213,12 @@ class MemOperandTraits(OperandTraits): def makeWrite(self, op_desc): (size, type, is_signed) = operandSizeMap[op_desc.eff_ext] eff_type = 'uint%d_t' % size - return 'fault = xc->write((%s&)%s, EA, %s_flags,' \ - ' &%s_write_result);\n' \ + wb = 'fault = xc->write((%s&)%s, EA, %s_flags, &%s_write_result);\n' \ % (eff_type, op_desc.munged_name, op_desc.base_name, op_desc.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + op_desc.munged_name + return wb class NPCOperandTraits(OperandTraits): def makeConstructor(self, op_desc): diff --git a/base/random.hh b/base/random.hh index 0bfed100c..fe93a98a6 100644 --- a/base/random.hh +++ b/base/random.hh @@ -37,61 +37,61 @@ double getDouble(); template <typename T> struct Random; -struct Random<int8_t> +template<> struct Random<int8_t> { static int8_t get() { return getLong() & (int8_t)-1; } }; -struct Random<uint8_t> +template<> struct Random<uint8_t> { static uint8_t get() { return getLong() & (uint8_t)-1; } }; -struct Random<int16_t> +template<> struct Random<int16_t> { static int16_t get() { return getLong() & (int16_t)-1; } }; -struct Random<uint16_t> +template<> struct Random<uint16_t> { static uint16_t get() { return getLong() & (uint16_t)-1; } }; -struct Random<int32_t> +template<> struct Random<int32_t> { static int32_t get() { return (int32_t)getLong(); } }; -struct Random<uint32_t> +template<> struct Random<uint32_t> { static uint32_t get() { return (uint32_t)getLong(); } }; -struct Random<int64_t> +template<> struct Random<int64_t> { static int64_t get() { return (int64_t)getLong() << 32 || (uint64_t)getLong(); } }; -struct Random<uint64_t> +template<> struct Random<uint64_t> { static uint64_t get() { return (uint64_t)getLong() << 32 || (uint64_t)getLong(); } }; -struct Random<float> +template<> struct Random<float> { static float get() { return getDouble(); } }; -struct Random<double> +template<> struct Random<double> { static double get() { return getDouble(); } diff --git a/base/range.hh b/base/range.hh index 9289792ea..57b6e6a77 100644 --- a/base/range.hh +++ b/base/range.hh @@ -30,6 +30,7 @@ #define __BASE_RANGE_HH__ #include <cassert> +#include <iostream> #include <string> /** diff --git a/base/res_list.hh b/base/res_list.hh index 7080a3ba7..5dc798fed 100644 --- a/base/res_list.hh +++ b/base/res_list.hh @@ -352,7 +352,7 @@ res_list<T>::insert_after(iterator prev, T *d) iterator p; if (!allocate_storage) - panic("Can't copy data... not allocating storage"); + this->panic("Can't copy data... not allocating storage"); p = insert_after(prev); if (p.notnull()) diff --git a/base/statistics.hh b/base/statistics.hh index a0be64ce5..9ec26eb4d 100644 --- a/base/statistics.hh +++ b/base/statistics.hh @@ -407,7 +407,7 @@ class Wrap : public Child public: Wrap() { - this->map(new Data<Child>(*this)); + map(new Data<Child>(*this)); } /** @@ -417,10 +417,10 @@ class Wrap : public Child */ Parent &name(const std::string &_name) { - Data<Child> *data = statData(); + Data<Child> *data = this->statData(); data->name = _name; - setPrint(); - return self(); + this->setPrint(); + return this->self(); } /** @@ -431,8 +431,8 @@ class Wrap : public Child */ Parent &desc(const std::string &_desc) { - statData()->desc = _desc; - return self(); + this->statData()->desc = _desc; + return this->self(); } /** @@ -442,8 +442,8 @@ class Wrap : public Child */ Parent &precision(int _precision) { - statData()->precision = _precision; - return self(); + this->statData()->precision = _precision; + return this->self(); } /** @@ -453,8 +453,8 @@ class Wrap : public Child */ Parent &flags(StatFlags _flags) { - statData()->flags |= _flags; - return self(); + this->statData()->flags |= _flags; + return this->self(); } /** @@ -466,8 +466,8 @@ class Wrap : public Child template <class Stat> Parent &prereq(const Stat &prereq) { - statData()->prereq = prereq.statData(); - return self(); + this->statData()->prereq = prereq.statData(); + return this->self(); } }; @@ -487,11 +487,11 @@ class WrapVec : public Wrap<Parent, Child, Data> */ Parent &subname(int index, const std::string &name) { - std::vector<std::string> &subn = statData()->subnames; + std::vector<std::string> &subn = this->statData()->subnames; if (subn.size() <= index) subn.resize(index + 1); subn[index] = name; - return self(); + return this->self(); } /** @@ -503,12 +503,12 @@ class WrapVec : public Wrap<Parent, Child, Data> */ Parent &subdesc(int index, const std::string &desc) { - std::vector<std::string> &subd = statData()->subdescs; + std::vector<std::string> &subd = this->statData()->subdescs; if (subd.size() <= index) subd.resize(index + 1); subd[index] = desc; - return self(); + return this->self(); } }; @@ -523,19 +523,19 @@ class WrapVec2d : public WrapVec<Parent, Child, Data> */ Parent &ysubnames(const char **names) { - Data<Child> *data = statData(); - data->y_subnames.resize(y); - for (int i = 0; i < y; ++i) + Data<Child> *data = this->statData(); + data->y_subnames.resize(this->y); + for (int i = 0; i < this->y; ++i) data->y_subnames[i] = names[i]; - return self(); + return this->self(); } Parent &ysubname(int index, const std::string subname) { - Data<Child> *data = statData(); - assert(index < y); - data->y_subnames.resize(y); + Data<Child> *data = this->statData(); + assert(index < this->y); + data->y_subnames.resize(this->y); data->y_subnames[index] = subname.c_str(); - return self(); + return this->self(); } }; @@ -711,7 +711,7 @@ class ScalarBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::Bin<Storage> bin_t; + typedef typename Bin::template Bin<Storage> bin_t; protected: /** The bin of this stat. */ @@ -914,7 +914,7 @@ class VectorBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::VectorBin<Storage> bin_t; + typedef typename Bin::template VectorBin<Storage> bin_t; protected: /** The bin of this stat. */ @@ -1022,7 +1022,7 @@ class ScalarProxy /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::VectorBin<Storage> bin_t; + typedef typename Bin::template VectorBin<Storage> bin_t; private: /** Pointer to the bin in the parent VectorBase. */ @@ -1155,7 +1155,7 @@ class ScalarProxy const StatData *statData() const { return getStatData(stat); } std::string str() const { - return csprintf("%s[%d]", statData()->name, index); + return csprintf("%s[%d]", this->statData()->name, index); } }; @@ -1176,7 +1176,7 @@ class Vector2dBase : public DataAccess { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin<Storage> bin_t; + typedef typename Bin::template VectorBin<Storage> bin_t; protected: size_t x; @@ -1204,7 +1204,7 @@ class Vector2dBase : public DataAccess data->cvec[i] = this->data(i)->value(params); } - std::string ysubname(int i) const { return (*y_subnames)[i]; } + std::string ysubname(int i) const { return (*this->y_subnames)[i]; } friend class VectorProxy<Storage, Bin>; VectorProxy<Storage, Bin> operator[](int index); @@ -1225,7 +1225,7 @@ class VectorProxy { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin<Storage> bin_t; + typedef typename Bin::template VectorBin<Storage> bin_t; private: bin_t *bin; @@ -1622,7 +1622,7 @@ class DistBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::Bin<Storage> bin_t; + typedef typename Bin::template Bin<Storage> bin_t; protected: /** The bin of this stat. */ @@ -1698,7 +1698,7 @@ class VectorDistBase : public DataAccess { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin<Storage> bin_t; + typedef typename Bin::template VectorBin<Storage> bin_t; protected: bin_t bin; @@ -1749,7 +1749,7 @@ class DistProxy { public: typedef typename Storage::Params params_t; - typedef typename Bin::Bin<Storage> bin_t; + typedef typename Bin::template Bin<Storage> bin_t; typedef VectorDistBase<Storage, Bin> base_t; private: @@ -2206,7 +2206,7 @@ class Scalar Scalar() { - setInit(); + this->setInit(); } /** @@ -2258,7 +2258,7 @@ class Average Average() { - setInit(); + this->setInit(); } /** @@ -2290,8 +2290,8 @@ class Vector * @return A reference to this stat. */ Vector &init(size_t size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2314,8 +2314,8 @@ class AverageVector * @return A reference to this stat. */ AverageVector &init(size_t size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2333,10 +2333,10 @@ class Vector2d { public: Vector2d &init(size_t _x, size_t _y) { - statData()->x = x = _x; - statData()->y = y = _y; - bin.init(x * y, params); - setInit(); + this->statData()->x = this->x = _x; + this->statData()->y = this->y = _y; + this->bin.init(this->x * this->y, this->params); + this->setInit(); return *this; } @@ -2367,12 +2367,12 @@ class Distribution * @return A reference to this distribution. */ Distribution &init(Counter min, Counter max, Counter bkt) { - params.min = min; - params.max = max; - params.bucket_size = bkt; - params.size = (int)rint((max - min) / bkt + 1.0); - bin.init(params); - setInit(); + this->params.min = min; + this->params.max = max; + this->params.bucket_size = bkt; + this->params.size = (int)rint((max - min) / bkt + 1.0); + this->bin.init(this->params); + this->setInit(); return *this; } @@ -2399,8 +2399,8 @@ class StandardDeviation * Construct and initialize this distribution. */ StandardDeviation() { - bin.init(params); - setInit(); + this->bin.init(this->params); + this->setInit(); } }; @@ -2426,8 +2426,8 @@ class AverageDeviation */ AverageDeviation() { - bin.init(params); - setInit(); + this->bin.init(this->params); + this->setInit(); } }; @@ -2457,12 +2457,12 @@ class VectorDistribution * @return A reference to this distribution. */ VectorDistribution &init(int size, Counter min, Counter max, Counter bkt) { - params.min = min; - params.max = max; - params.bucket_size = bkt; - params.size = (int)rint((max - min) / bkt + 1.0); - bin.init(size, params); - setInit(); + this->params.min = min; + this->params.max = max; + this->params.bucket_size = bkt; + this->params.size = (int)rint((max - min) / bkt + 1.0); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2491,8 +2491,8 @@ class VectorStandardDeviation * @return A reference to this distribution. */ VectorStandardDeviation &init(int size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2521,8 +2521,8 @@ class VectorAverageDeviation * @return A reference to this distribution. */ VectorAverageDeviation &init(int size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } diff --git a/base/stats/events.cc b/base/stats/events.cc index e5efceabe..d716fa4d3 100644 --- a/base/stats/events.cc +++ b/base/stats/events.cc @@ -134,7 +134,7 @@ InsertEvent::insert(const string &stat) first = false; size += sprintf(query + size, "(%u,%u,%llu)", - event, run, curTick); + event, run, (unsigned long long)curTick); } void diff --git a/base/trace.cc b/base/trace.cc index 1c07e408f..c9d4a0f78 100644 --- a/base/trace.cc +++ b/base/trace.cc @@ -71,7 +71,7 @@ Log::init(int _size) size = _size; - buffer = new (Record *)[size]; + buffer = new Record *[size]; for (int i = 0; i < size; ++i) { buffer[i] = NULL; diff --git a/base/trace.hh b/base/trace.hh index 5e05d6e5e..054b14546 100644 --- a/base/trace.hh +++ b/base/trace.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __TRACE_HH__ -#define __TRACE_HH__ +#ifndef __BASE_TRACE_HH__ +#define __BASE_TRACE_HH__ #include <vector> @@ -228,4 +228,4 @@ do { \ #endif // TRACING_ON -#endif // __TRACE_HH__ +#endif // __BASE_TRACE_HH__ diff --git a/base/traceflags.py b/base/traceflags.py index 1f69e5e88..d1eb4478a 100644 --- a/base/traceflags.py +++ b/base/traceflags.py @@ -154,6 +154,7 @@ compoundFlagMap = { 'ScsiAll' : [ 'ScsiDisk', 'ScsiCtrl', 'ScsiNone' ], 'DiskImageAll' : [ 'DiskImage', 'DiskImageRead', 'DiskImageWrite' ], 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], + 'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ], 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LDSTQ', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU'] } diff --git a/configs/boot/devtime.rcS b/configs/boot/devtime.rcS new file mode 100644 index 000000000..91fddc20d --- /dev/null +++ b/configs/boot/devtime.rcS @@ -0,0 +1,8 @@ +insmod /modules/devtime.ko dataAddr=0x9000004 count=100 +rmmod devtime +insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 +rmmod devtime +insmod /modules/devtime.ko memTest=1 count=100 +rmmod devtime +m5 exit + diff --git a/configs/boot/nat-netperf-maerts-client.rcS b/configs/boot/nat-netperf-maerts-client.rcS index fa3e174e7..ab9fd8c4e 100644 --- a/configs/boot/nat-netperf-maerts-client.rcS +++ b/configs/boot/nat-netperf-maerts-client.rcS @@ -11,6 +11,7 @@ route add default gw 10.0.0.1 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-netperf-server.rcS b/configs/boot/nat-netperf-server.rcS index c0646b61c..5b094b790 100644 --- a/configs/boot/nat-netperf-server.rcS +++ b/configs/boot/nat-netperf-server.rcS @@ -9,6 +9,7 @@ ifconfig eth0 $SERVER txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-netperf-stream-client.rcS b/configs/boot/nat-netperf-stream-client.rcS index f0f3a23ce..d0213c265 100644 --- a/configs/boot/nat-netperf-stream-client.rcS +++ b/configs/boot/nat-netperf-stream-client.rcS @@ -8,6 +8,7 @@ ifconfig eth0 $CLIENT txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-spec-surge-client.rcS b/configs/boot/nat-spec-surge-client.rcS index 2c0b46607..a3bc512db 100644 --- a/configs/boot/nat-spec-surge-client.rcS +++ b/configs/boot/nat-spec-surge-client.rcS @@ -20,6 +20,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem diff --git a/configs/boot/nat-spec-surge-server.rcS b/configs/boot/nat-spec-surge-server.rcS index ed0e96a44..9b5674e63 100755 --- a/configs/boot/nat-spec-surge-server.rcS +++ b/configs/boot/nat-spec-surge-server.rcS @@ -23,6 +23,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem diff --git a/configs/boot/natbox-netperf.rcS b/configs/boot/natbox-netperf.rcS index d665670fe..5ec08c1a2 100644 --- a/configs/boot/natbox-netperf.rcS +++ b/configs/boot/natbox-netperf.rcS @@ -10,6 +10,8 @@ ifconfig eth1 $INTIF txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid + echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/natbox-spec-surge.rcS b/configs/boot/natbox-spec-surge.rcS index ed74b71bd..d612424d2 100644 --- a/configs/boot/natbox-spec-surge.rcS +++ b/configs/boot/natbox-spec-surge.rcS @@ -10,6 +10,7 @@ ifconfig eth1 $INTIF txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 2275f12e3..19261e97b 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -86,7 +86,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, maxThreadsPerCPU = number_of_threads; // allocate per-thread instruction-based event queues - comInstEventQueue = new (EventQueue *)[number_of_threads]; + comInstEventQueue = new EventQueue *[number_of_threads]; for (int i = 0; i < number_of_threads; ++i) comInstEventQueue[i] = new EventQueue("instruction-based event queue"); @@ -111,7 +111,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, } // allocate per-thread load-based event queues - comLoadEventQueue = new (EventQueue *)[number_of_threads]; + comLoadEventQueue = new EventQueue *[number_of_threads]; for (int i = 0; i < number_of_threads; ++i) comLoadEventQueue[i] = new EventQueue("load-based event queue"); diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index d48f93663..f292b25a5 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -74,6 +74,7 @@ using namespace std; + SimpleCPU::TickEvent::TickEvent(SimpleCPU *c) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) { diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 341a0da23..a81d6365b 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -26,15 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __SIMPLE_CPU_HH__ -#define __SIMPLE_CPU_HH__ +#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ +#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ -#include "cpu/base_cpu.hh" -#include "sim/eventq.hh" -#include "cpu/pc_event.hh" #include "base/statistics.hh" +#include "cpu/base_cpu.hh" #include "cpu/exec_context.hh" +#include "cpu/pc_event.hh" #include "cpu/static_inst.hh" +#include "sim/eventq.hh" // forward declarations #ifdef FULL_SYSTEM @@ -102,12 +102,6 @@ class SimpleCPU : public BaseCPU private: Trace::InstRecord *traceData; - template<typename T> - void trace_data(T data) { - if (traceData) { - traceData->setData(data); - } - }; public: // @@ -249,6 +243,11 @@ class SimpleCPU : public BaseCPU template <class T> Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + // These functions are only used in CPU models that split + // effective address computation from the actual memory access. + void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } + Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } + void prefetch(Addr addr, unsigned flags) { // need to do this... @@ -346,4 +345,4 @@ class SimpleCPU : public BaseCPU ExecContext *xcBase() { return xc; } }; -#endif // __SIMPLE_CPU_HH__ +#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc index 4cb45a818..7069d89ec 100644 --- a/cpu/static_inst.cc +++ b/cpu/static_inst.cc @@ -85,4 +85,4 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) // force instantiation of template function(s) above -template StaticInst<AlphaISA>; +template class StaticInst<AlphaISA>; diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index c47fa32db..b5022af5b 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -441,7 +441,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > /// Convert to pointer to StaticInstBase class. operator const StaticInstBasePtr() { - return get(); + return this->get(); } }; diff --git a/dev/etherlink.hh b/dev/etherlink.hh index e998a006f..d5cd7d7c8 100644 --- a/dev/etherlink.hh +++ b/dev/etherlink.hh @@ -30,13 +30,13 @@ * Device module for modelling a fixed bandwidth full duplex ethernet link */ -#ifndef __ETHERLINK_HH__ -#define __ETHERLINK_HH__ +#ifndef __DEV_ETHERLINK_HH__ +#define __DEV_ETHERLINK_HH__ -#include "sim/host.hh" -#include "sim/eventq.hh" #include "dev/etherint.hh" #include "dev/etherpkt.hh" +#include "sim/eventq.hh" +#include "sim/host.hh" #include "sim/sim_object.hh" class EtherDump; @@ -71,7 +71,7 @@ class EtherLink : public SimObject PacketPtr packet; void txDone(); typedef EventWrapper<Link, &Link::txDone> DoneEvent; - friend class DoneEvent; + friend void DoneEvent::process(); DoneEvent doneEvent; friend class LinkDelayEvent; diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index aa47436f7..db1474d1c 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -244,7 +244,6 @@ NSGigE::regStats() .precision(0) ; - txBandwidth .name(name() + ".txBandwidth") .desc("Transmit Bandwidth (bits/s)") @@ -259,6 +258,34 @@ NSGigE::regStats() .prereq(rxBytes) ; + totBandwidth + .name(name() + ".totBandwidth") + .desc("Total Bandwidth (bits/s)") + .precision(0) + .prereq(totBytes) + ; + + totPackets + .name(name() + ".totPackets") + .desc("Total Packets") + .precision(0) + .prereq(totBytes) + ; + + totBytes + .name(name() + ".totBytes") + .desc("Total Bytes") + .precision(0) + .prereq(totBytes) + ; + + totPacketRate + .name(name() + ".totPPS") + .desc("Total Tranmission Rate (packets/s)") + .precision(0) + .prereq(totBytes) + ; + txPacketRate .name(name() + ".txPPS") .desc("Packet Tranmission Rate (packets/s)") @@ -449,6 +476,10 @@ NSGigE::regStats() txBandwidth = txBytes * Stats::constant(8) / simSeconds; rxBandwidth = rxBytes * Stats::constant(8) / simSeconds; + totBandwidth = txBandwidth + rxBandwidth; + totBytes = txBytes + rxBytes; + totPackets = txPackets + rxPackets; + txPacketRate = txPackets / simSeconds; rxPacketRate = rxPackets / simSeconds; } @@ -2352,6 +2383,7 @@ NSGigE::serialize(ostream &os) bool txPacketExists = txPacket; SERIALIZE_SCALAR(txPacketExists); if (txPacketExists) { + txPacket->length = txPacketBufPtr - txPacket->data; txPacket->serialize("txPacket", os); uint32_t txPktBufPtr = (uint32_t) (txPacketBufPtr - txPacket->data); SERIALIZE_SCALAR(txPktBufPtr); diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index bc7a87373..58060edac 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -261,12 +261,12 @@ class NSGigE : public PciDev void rxKick(); Tick rxKickTick; typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); void txKick(); Tick txKickTick; typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); /** * Retransmit event @@ -279,7 +279,7 @@ class NSGigE : public PciDev txKick(); } typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent; - friend class TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; @@ -313,7 +313,7 @@ class NSGigE : public PciDev void cpuIntrClear(); typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; NSGigEInt *interface; @@ -379,6 +379,10 @@ class NSGigE : public PciDev Stats::Scalar<> descDmaWrites; Stats::Scalar<> descDmaRdBytes; Stats::Scalar<> descDmaWrBytes; + Stats::Formula totBandwidth; + Stats::Formula totPackets; + Stats::Formula totBytes; + Stats::Formula totPacketRate; Stats::Formula txBandwidth; Stats::Formula rxBandwidth; Stats::Formula txPacketRate; diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 4b947b560..14f183e28 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -78,10 +78,6 @@ class PciConfigData : public SimObject */ class PciDev : public DmaDevice { - protected: - struct Params; - Params *_params; - public: struct Params { @@ -110,6 +106,11 @@ class PciDev : public DmaDevice /** The function number */ uint32_t functionNum; }; + + protected: + Params *_params; + + public: const Params *params() const { return _params; } protected: diff --git a/dev/pktfifo.cc b/dev/pktfifo.cc index ae82123cf..dcb1c4c03 100644 --- a/dev/pktfifo.cc +++ b/dev/pktfifo.cc @@ -54,13 +54,12 @@ PacketFifo::unserialize(const string &base, Checkpoint *cp, const string §ion) { paramIn(cp, section, base + ".size", _size); - paramIn(cp, section, base + ".maxsize", _maxsize); +// paramIn(cp, section, base + ".maxsize", _maxsize); paramIn(cp, section, base + ".reserved", _reserved); int fifosize; paramIn(cp, section, base + ".packets", fifosize); fifo.clear(); - fifo.resize(fifosize); for (int i = 0; i < fifosize; ++i) { PacketPtr p = new PacketData(16384); diff --git a/dev/rtcreg.h b/dev/rtcreg.h new file mode 100644 index 000000000..8e1f51bfa --- /dev/null +++ b/dev/rtcreg.h @@ -0,0 +1,44 @@ + +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define RTC_SEC 0x00 +#define RTC_SEC_ALRM 0x01 +#define RTC_MIN 0x02 +#define RTC_MIN_ALRM 0x03 +#define RTC_HR 0x04 +#define RTC_HR_ALRM 0x05 +#define RTC_DOW 0x06 +#define RTC_DOM 0x07 +#define RTC_MON 0x08 +#define RTC_YEAR 0x09 +#define RTC_CNTRL_REGA 0x0A +#define RTC_CNTRL_REGB 0x0B +#define RTC_CNTRL_REGC 0x0C +#define RTC_CNTRL_REGD 0x0D + diff --git a/dev/simconsole.cc b/dev/simconsole.cc index d8d890e15..48e5d0201 100644 --- a/dev/simconsole.cc +++ b/dev/simconsole.cc @@ -315,7 +315,7 @@ CREATE_SIM_OBJECT(SimConsole) { string filename; - if (!output.isValid()) { + if (filename.empty()) { filename = getInstanceName(); } else if (append_name) { filename = (string)output + "." + getInstanceName(); diff --git a/dev/sinic.cc b/dev/sinic.cc index 56782b589..fa4cd570f 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -191,6 +191,34 @@ Device::regStats() .prereq(rxBytes) ; + totBandwidth + .name(name() + ".totBandwidth") + .desc("Total Bandwidth (bits/s)") + .precision(0) + .prereq(totBytes) + ; + + totPackets + .name(name() + ".totPackets") + .desc("Total Packets") + .precision(0) + .prereq(totBytes) + ; + + totBytes + .name(name() + ".totBytes") + .desc("Total Bytes") + .precision(0) + .prereq(totBytes) + ; + + totPacketRate + .name(name() + ".totPPS") + .desc("Total Tranmission Rate (packets/s)") + .precision(0) + .prereq(totBytes) + ; + txBytes .name(name() + ".txBytes") .desc("Bytes Transmitted") @@ -258,6 +286,9 @@ Device::regStats() txBandwidth = txBytes * Stats::constant(8) / simSeconds; rxBandwidth = rxBytes * Stats::constant(8) / simSeconds; + totBandwidth = txBandwidth + rxBandwidth; + totBytes = txBytes + rxBytes; + totPackets = txPackets + rxPackets; txPacketRate = txPackets / simSeconds; rxPacketRate = rxPackets / simSeconds; } diff --git a/dev/sinic.hh b/dev/sinic.hh index ef515ffad..9b8920f3b 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -59,7 +59,7 @@ class Base : public PciDev void cpuIntrClear(); typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; Interface *interface; @@ -155,12 +155,12 @@ class Device : public Base void rxKick(); Tick rxKickTick; typedef EventWrapper<Device, &Device::rxKick> RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); void txKick(); Tick txKickTick; typedef EventWrapper<Device, &Device::txKick> TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); /** * Retransmit event @@ -173,7 +173,7 @@ class Device : public Base txKick(); } typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent; - friend class TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; @@ -262,6 +262,10 @@ class Device : public Base Stats::Scalar<> txBytes; Stats::Formula txBandwidth; + Stats::Formula totBandwidth; + Stats::Formula totPackets; + Stats::Formula totBytes; + Stats::Formula totPacketRate; Stats::Scalar<> txPackets; Stats::Formula txPacketRate; Stats::Scalar<> txIpPackets; diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 823d1f118..6bf4d8b57 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -173,6 +173,13 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) break; case sizeof(uint32_t): + if (regnum == TSDEV_CC_DRIR) { + warn("accessing DRIR with 32 bit read, " + "hopefully your just reading this for timing"); + *(uint64_t*)data = drir; + } else + panic("invalid access size(?) for tsunami register!\n"); + return No_Fault; case sizeof(uint16_t): case sizeof(uint8_t): default: diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index a223c95c7..94a951d2c 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ #include "sim/builder.hh" #include "dev/tsunami_cchip.hh" #include "dev/tsunamireg.h" +#include "dev/rtcreg.h" #include "mem/functional_mem/memory_control.hh" using namespace std; @@ -217,36 +218,36 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) return No_Fault; case TSDEV_RTC_DATA: switch(RTCAddress) { - case RTC_CONTROL_REGISTERA: + case RTC_CNTRL_REGA: *(uint8_t*)data = uip << 7 | 0x26; uip = !uip; return No_Fault; - case RTC_CONTROL_REGISTERB: + case RTC_CNTRL_REGB: // DM and 24/12 and UIE *(uint8_t*)data = 0x46; return No_Fault; - case RTC_CONTROL_REGISTERC: + case RTC_CNTRL_REGC: // If we want to support RTC user access in linux // This won't work, but for now it's fine *(uint8_t*)data = 0x00; return No_Fault; - case RTC_CONTROL_REGISTERD: + case RTC_CNTRL_REGD: panic("RTC Control Register D not implemented"); - case RTC_SECOND: + case RTC_SEC: *(uint8_t *)data = tm.tm_sec; return No_Fault; - case RTC_MINUTE: + case RTC_MIN: *(uint8_t *)data = tm.tm_min; return No_Fault; - case RTC_HOUR: + case RTC_HR: *(uint8_t *)data = tm.tm_hour; return No_Fault; - case RTC_DAY_OF_WEEK: + case RTC_DOW: *(uint8_t *)data = tm.tm_wday; return No_Fault; - case RTC_DAY_OF_MONTH: + case RTC_DOM: *(uint8_t *)data = tm.tm_mday; - case RTC_MONTH: + case RTC_MON: *(uint8_t *)data = tm.tm_mon + 1; return No_Fault; case RTC_YEAR: diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 3304082a5..290f21a5b 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -122,23 +122,6 @@ #define TSDEV_RTC_ADDR 0x70 #define TSDEV_RTC_DATA 0x71 -// RTC defines -#define RTC_SECOND 0 // second of minute [0..59] -#define RTC_SECOND_ALARM 1 // seconds to alarm -#define RTC_MINUTE 2 // minute of hour [0..59] -#define RTC_MINUTE_ALARM 3 // minutes to alarm -#define RTC_HOUR 4 // hour of day [0..23] -#define RTC_HOUR_ALARM 5 // hours to alarm -#define RTC_DAY_OF_WEEK 6 // day of week [1..7] -#define RTC_DAY_OF_MONTH 7 // day of month [1..31] -#define RTC_MONTH 8 // month of year [1..12] -#define RTC_YEAR 9 // year [00..99] -#define RTC_CONTROL_REGISTERA 10 // control register A -#define RTC_CONTROL_REGISTERB 11 // control register B -#define RTC_CONTROL_REGISTERC 12 // control register C -#define RTC_CONTROL_REGISTERD 13 // control register D -#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 - #define PCHIP_PCI0_MEMORY ULL(0x00000000000) #define PCHIP_PCI0_IO ULL(0x001FC000000) #define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) diff --git a/kern/linux/linux_syscalls.hh b/kern/linux/linux_syscalls.hh index dee7c5fcd..44a038def 100644 --- a/kern/linux/linux_syscalls.hh +++ b/kern/linux/linux_syscalls.hh @@ -26,14 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __LINUX_SYSCALLS_HH__ -#define __LINUX_SYSCALLS_HH__ +#ifndef __KERN_LINUX_LINUX_SYSCALLS_HH__ +#define __KERN_LINUX_LINUX_SYSCALLS_HH__ #include "kern/linux/linux.hh" template <class OS> class SystemCalls; +template <> class SystemCalls<Linux> { public: @@ -322,4 +323,4 @@ class SystemCalls<Linux> }; -#endif // __LINUX_SYSCALLS_HH__ +#endif // __KERN_LINUX_LINUX_SYSCALLS_HH__ diff --git a/kern/tru64/tru64_syscalls.hh b/kern/tru64/tru64_syscalls.hh index 7ddc699b1..44e5de250 100644 --- a/kern/tru64/tru64_syscalls.hh +++ b/kern/tru64/tru64_syscalls.hh @@ -26,14 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __TRU64_SYSCALLS_HH__ -#define __TRU64_SYSCALLS_HH__ +#ifndef __KERN_TRU64_TRU64_SYSCALLS_HH__ +#define __KERN_TRU64_TRU64_SYSCALLS_HH__ #include "kern/tru64/tru64.hh" template <class OS> class SystemCalls; +template <> class SystemCalls<Tru64> { public: @@ -355,4 +356,4 @@ class SystemCalls<Tru64> } }; -#endif // __TRU64_SYSCALLS_HH__ +#endif // __KERN_TRU64_TRU64_SYSCALLS_HH__ diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy index bcb47bf8b..79918a01e 100644 --- a/objects/AlphaConsole.mpy +++ b/objects/AlphaConsole.mpy @@ -1,8 +1,9 @@ from Device import PioDevice simobj AlphaConsole(PioDevice): + type = 'AlphaConsole' cpu = Param.BaseCPU(Super, "Processor") disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPU's") + num_cpus = Param.Int(1, "Number of CPUs") sim_console = Param.SimConsole(Super, "The Simulator Console") system = Param.BaseSystem(Super, "system object") diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy index 571b98374..8e7cd62cc 100644 --- a/objects/AlphaTLB.mpy +++ b/objects/AlphaTLB.mpy @@ -1,9 +1,12 @@ simobj AlphaTLB(SimObject): + type = 'AlphaTLB' abstract = True size = Param.Int("TLB size") simobj AlphaDTB(AlphaTLB): + type = 'AlphaDTB' size = 64 simobj AlphaITB(AlphaTLB): + type = 'AlphaITB' size = 48 diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy index 5c56b8036..35a12e0bf 100644 --- a/objects/BadDevice.mpy +++ b/objects/BadDevice.mpy @@ -1,4 +1,5 @@ from Device import PioDevice simobj BadDevice(PioDevice): + type = 'BadDevice' devicename = Param.String("Name of device to error on") diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy index 2aca9120d..f6e6ff96c 100644 --- a/objects/BaseCPU.mpy +++ b/objects/BaseCPU.mpy @@ -1,4 +1,5 @@ simobj BaseCPU(SimObject): + type = 'BaseCPU' abstract = True icache = Param.BaseMem(NULL, "L1 instruction cache object") dcache = Param.BaseMem(NULL, "L1 data cache object") @@ -18,7 +19,7 @@ simobj BaseCPU(SimObject): max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") - defer_registration = Param.Bool(false, + defer_registration = Param.Bool(False, "defer registration with system (for sampling)") def check(self): diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 67ca3c04e..98a422e30 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -1,30 +1,38 @@ from BaseMem import BaseMem simobj BaseCache(BaseMem): - adaptive_compression = Param.Bool(false, + type = 'BaseCache' + adaptive_compression = Param.Bool(False, "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - compressed_bus = Param.Bool(false, + compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Int(0, "Latency in cycles of compression algorithm") - do_copy = Param.Bool(false, "perform fast copies in the cache") + do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") in_bus = Param.Bus(NULL, "incoming bus object") + lifo = Param.Bool(False, + "whether this NIC partition should use LIFO repl. policy") max_miss_count = Param.Counter(0, "number of misses to handle before calling exit") mshrs = Param.Int("number of MSHRs (max outstanding requests)") out_bus = Param.Bus("outgoing bus object") - prioritizeRequests = Param.Bool(false, + prioritizeRequests = Param.Bool(False, "always service demand misses first") protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") repl = Param.Repl(NULL, "replacement policy") size = Param.Int("capacity in bytes") - store_compressed = Param.Bool(false, + split = Param.Bool(False, "whether or not this cache is split") + split_size = Param.Int(0, + "How many ways of the cache belong to CPU/LRU partition") + store_compressed = Param.Bool(False, "Store compressed data in the cache") subblock_size = Param.Int(0, "Size of subblock in IIC used for compression") tgts_per_mshr = Param.Int("max number of accesses per MSHR") trace_addr = Param.Addr(0, "address to trace") + two_queue = Param.Bool(False, + "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy index 2a8b98338..1cbdf4e99 100644 --- a/objects/BaseSystem.mpy +++ b/objects/BaseSystem.mpy @@ -1,4 +1,5 @@ simobj BaseSystem(SimObject): + type = 'BaseSystem' abstract = True memctrl = Param.MemoryController(Super, "memory controller") physmem = Param.PhysicalMemory(Super, "phsyical memory") @@ -10,5 +11,5 @@ simobj BaseSystem(SimObject): boot_osflags = Param.String("a", "boot flags to pass to the kernel") system_type = Param.UInt64("Type of system we are emulating") system_rev = Param.UInt64("Revision of system we are emulating") - bin = Param.Bool(false, "is this system binned") + bin = Param.Bool(False, "is this system binned") binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/objects/Bus.mpy b/objects/Bus.mpy index 9e112bfe6..025d69785 100644 --- a/objects/Bus.mpy +++ b/objects/Bus.mpy @@ -1,5 +1,6 @@ from BaseHier import BaseHier simobj Bus(BaseHier): + type = 'Bus' clock_ratio = Param.Int("ratio of CPU to bus frequency") width = Param.Int("bus width in bytes") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy index a2518bf39..ae041b638 100644 --- a/objects/CoherenceProtocol.mpy +++ b/objects/CoherenceProtocol.mpy @@ -1,5 +1,6 @@ Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi') simobj CoherenceProtocol(SimObject): - do_upgrades = Param.Bool(true, "use upgrade transactions?") + type = 'CoherenceProtocol' + do_upgrades = Param.Bool(True, "use upgrade transactions?") protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/Device.mpy b/objects/Device.mpy index babc8aa9d..47f8db1cb 100644 --- a/objects/Device.mpy +++ b/objects/Device.mpy @@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory # initialization phase at which point all SimObject pointers will be # valid. simobj FooPioDevice(FunctionalMemory): - abstract = True type = 'PioDevice' + abstract = True addr = Param.Addr("Device Address") mmu = Param.MemoryController(Super, "Memory Controller") io_bus = Param.Bus(NULL, "The IO Bus to attach to") pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") simobj FooDmaDevice(FooPioDevice): - abstract = True type = 'DmaDevice' + abstract = True simobj PioDevice(FooPioDevice): + type = 'PioDevice' abstract = True platform = Param.Platform(Super, "Platform") simobj DmaDevice(PioDevice): + type = 'DmaDevice' abstract = True diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy index bea2e56a8..80ef7b072 100644 --- a/objects/DiskImage.mpy +++ b/objects/DiskImage.mpy @@ -1,12 +1,14 @@ simobj DiskImage(SimObject): + type = 'DiskImage' abstract = True image_file = Param.String("disk image file") - read_only = Param.Bool(false, "read only image") + read_only = Param.Bool(False, "read only image") simobj RawDiskImage(DiskImage): - pass + type = 'RawDiskImage' simobj CowDiskImage(DiskImage): + type = 'CowDiskImage' child = Param.DiskImage("child image") table_size = Param.Int(65536, "initial table size") image_file = '' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy index 64eab00a3..088df4b93 100644 --- a/objects/Ethernet.mpy +++ b/objects/Ethernet.mpy @@ -2,10 +2,12 @@ from Device import DmaDevice from Pci import PciDevice simobj EtherInt(SimObject): + type = 'EtherInt' abstract = True peer = Param.EtherInt(NULL, "peer interface") simobj EtherLink(SimObject): + type = 'EtherLink' int1 = Param.EtherInt("interface 1") int2 = Param.EtherInt("interface 2") delay = Param.Tick(0, "transmit delay of packets in us") @@ -13,31 +15,35 @@ simobj EtherLink(SimObject): dump = Param.EtherDump(NULL, "dump object") simobj EtherBus(SimObject): - loopback = Param.Bool(true, + type = 'EtherBus' + loopback = Param.Bool(True, "send packet back to the interface from which it came") dump = Param.EtherDump(NULL, "dump object") speed = Param.UInt64(100000000, "bus speed in bits per second") simobj EtherTap(EtherInt): + type = 'EtherTap' bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") port = Param.UInt16(3500, "tap port") simobj EtherDump(SimObject): + type = 'EtherDump' file = Param.String("dump file") simobj EtherDev(DmaDevice): + type = 'EtherDev' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - dma_data_free = Param.Bool(false, "DMA of Data is free") - dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") dma_read_delay = Param.Tick(0, "fixed delay for dma reads") dma_read_factor = Param.Tick(0, "multiplier for dma reads") dma_write_delay = Param.Tick(0, "fixed delay for dma writes") dma_write_factor = Param.Tick(0, "multiplier for dma writes") - rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Tick(1000, "Receive Delay") tx_delay = Param.Tick(1000, "Transmit Delay") @@ -47,17 +53,18 @@ simobj EtherDev(DmaDevice): tlaser = Param.Turbolaser(Super, "Turbolaser") simobj NSGigE(PciDevice): + type = 'NSGigE' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - dma_data_free = Param.Bool(false, "DMA of Data is free") - dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") dma_read_delay = Param.Tick(0, "fixed delay for dma reads") dma_read_factor = Param.Tick(0, "multiplier for dma reads") dma_write_delay = Param.Tick(0, "fixed delay for dma writes") dma_write_factor = Param.Tick(0, "multiplier for dma writes") - rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Tick(1000, "Receive Delay") tx_delay = Param.Tick(1000, "Transmit Delay") @@ -69,9 +76,11 @@ simobj NSGigE(PciDevice): physmem = Param.PhysicalMemory(Super, "Physical Memory") simobj EtherDevInt(EtherInt): + type = 'EtherDevInt' device = Param.EtherDev("Ethernet device of this interface") simobj NSGigEInt(EtherInt): + type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") diff --git a/objects/Ide.mpy b/objects/Ide.mpy index 816b33c8c..c4aa2aca0 100644 --- a/objects/Ide.mpy +++ b/objects/Ide.mpy @@ -3,10 +3,12 @@ from Pci import PciDevice IdeID = Enum('master', 'slave') simobj IdeDisk(SimObject): + type = 'IdeDisk' delay = Param.Tick(1, "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") physmem = Param.PhysicalMemory(Super, "Physical memory") simobj IdeController(PciDevice): + type = 'IdeController' disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy index 7c97746ff..1ef5a17ee 100644 --- a/objects/IntrControl.mpy +++ b/objects/IntrControl.mpy @@ -1,2 +1,3 @@ simobj IntrControl(SimObject): + type = 'IntrControl' cpu = Param.BaseCPU(Super, "the cpu") diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy index 49319e163..1ec33a30c 100644 --- a/objects/MemTest.mpy +++ b/objects/MemTest.mpy @@ -1,4 +1,5 @@ simobj MemTest(SimObject): + type = 'MemTest' cache = Param.BaseCache("L1 cache") check_mem = Param.FunctionalMemory("check memory") main_mem = Param.FunctionalMemory("hierarchical memory") diff --git a/objects/Pci.mpy b/objects/Pci.mpy index d6917b020..caa3c52ff 100644 --- a/objects/Pci.mpy +++ b/objects/Pci.mpy @@ -1,7 +1,8 @@ from Device import FooPioDevice, DmaDevice simobj PciConfigData(FooPioDevice): - addr = 0xffffffffffffffff + type = 'PciConfigData' + addr = 0xffffffffffffffffL VendorID = Param.UInt16("Vendor ID") DeviceID = Param.UInt16("Device ID") Command = Param.UInt16(0, "Command") @@ -38,13 +39,14 @@ simobj PciConfigData(FooPioDevice): MinimumGrant = Param.UInt8(0x00, "Minimum Grant") simobj PciConfigAll(FooPioDevice): - pass + type = 'PciConfigAll' simobj PciDevice(DmaDevice): + type = 'PciDevice' abstract = True pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") pci_func = Param.Int("PCI function code") configdata = Param.PciConfigData(Super, "PCI Config data") configspace = Param.PciConfigAll(Super, "PCI Configspace") - addr = 0xffffffffffffffff + addr = 0xffffffffffffffffL diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy index 9644c503a..d1e4ad4b4 100644 --- a/objects/PhysicalMemory.mpy +++ b/objects/PhysicalMemory.mpy @@ -1,6 +1,7 @@ from FunctionalMemory import FunctionalMemory simobj PhysicalMemory(FunctionalMemory): + type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/objects/Platform.mpy b/objects/Platform.mpy index 870026259..d0510eaf8 100644 --- a/objects/Platform.mpy +++ b/objects/Platform.mpy @@ -1,4 +1,5 @@ simobj Platform(SimObject): + type = 'Platform' abstract = True interrupt_frequency = Param.Tick(1200, "frequency of interrupts") intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/objects/Process.mpy b/objects/Process.mpy index 4f5c4a674..6a91c09c2 100644 --- a/objects/Process.mpy +++ b/objects/Process.mpy @@ -1,12 +1,15 @@ simobj Process(SimObject): + type = 'Process' abstract = True output = Param.String('cout', 'filename for stdout/stderr') simobj LiveProcess(Process): + type = 'LiveProcess' cmd = VectorParam.String("command line (executable plus arguments)") env = VectorParam.String('', "environment settings") input = Param.String('cin', "filename for stdin") simobj EioProcess(Process): + type = 'EioProcess' chkpt = Param.String('', "EIO checkpoint file name (optional)") file = Param.String("EIO trace file name") diff --git a/objects/Repl.mpy b/objects/Repl.mpy index 87e7bfb7d..fff5a2a02 100644 --- a/objects/Repl.mpy +++ b/objects/Repl.mpy @@ -1,7 +1,9 @@ simobj Repl(SimObject): + type = 'Repl' abstract = True simobj GenRepl(Repl): + type = 'GenRepl' fresh_res = Param.Int("associativity") num_pools = Param.Int("capacity in bytes") pool_res = Param.Int("block size in bytes") diff --git a/objects/Root.mpy b/objects/Root.mpy index 2649d59fa..b21396e36 100644 --- a/objects/Root.mpy +++ b/objects/Root.mpy @@ -1,9 +1,11 @@ from HierParams import HierParams simobj Root(SimObject): + type = 'Root' frequency = Param.Tick(200000000, "tick frequency") output_dir = Param.String('.', "directory to output data to") output_file = Param.String('cout', "file to dump simulator output to") config_output_file = Param.String('m5config.out', "file to dump simulator config to") full_system = Param.Bool("Full system simulation?") - hier = HierParams(do_data = false, do_events = true) + hier = HierParams(do_data = False, do_events = True) + checkpoint = Param.String('', "Checkpoint file") diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy index 0676738f9..ab88db8c6 100644 --- a/objects/SimConsole.mpy +++ b/objects/SimConsole.mpy @@ -1,9 +1,11 @@ simobj ConsoleListener(SimObject): + type = 'ConsoleListener' port = Param.UInt16(3456, "listen port") simobj SimConsole(SimObject): - append_name = Param.Bool(true, "append name() to filename") + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") intr_control = Param.IntrControl(Super, "interrupt controller") listener = Param.ConsoleListener("console listener") number = Param.Int(0, "console number") - output = Param.String("", "file to dump output to") + output = Param.String('', "file to dump output to") diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy index 46bbdb8fd..c4dd5435b 100644 --- a/objects/SimpleDisk.mpy +++ b/objects/SimpleDisk.mpy @@ -1,3 +1,4 @@ simobj SimpleDisk(SimObject): + type = 'SimpleDisk' disk = Param.DiskImage("Disk Image") physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy index 6f9555d49..cfe23977e 100644 --- a/objects/Tsunami.mpy +++ b/objects/Tsunami.mpy @@ -2,20 +2,24 @@ from Device import FooPioDevice from Platform import Platform simobj Tsunami(Platform): + type = 'Tsunami' pciconfig = Param.PciConfigAll("PCI configuration") system = Param.BaseSystem(Super, "system") interrupt_frequency = Param.Int(1024, "frequency of interrupts") simobj TsunamiCChip(FooPioDevice): + type = 'TsunamiCChip' tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiFake(FooPioDevice): - pass + type = 'TsunamiFake' simobj TsunamiIO(FooPioDevice): + type = 'TsunamiIO' time = Param.UInt64(1136073600, "System time to use (0 for actual time, default is 1/1/06)") tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiPChip(FooPioDevice): + type = 'TsunamiPChip' tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/objects/Uart.mpy b/objects/Uart.mpy index a54e19dcd..76ee8805f 100644 --- a/objects/Uart.mpy +++ b/objects/Uart.mpy @@ -1,5 +1,6 @@ from Device import PioDevice simobj Uart(PioDevice): + type = 'Uart' console = Param.SimConsole(Super, "The console") size = Param.Addr(0x8, "Device size") diff --git a/sim/eventq.hh b/sim/eventq.hh index 304e4b16a..d62e7df10 100644 --- a/sim/eventq.hh +++ b/sim/eventq.hh @@ -30,8 +30,8 @@ * EventQueue interfaces */ -#ifndef __EVENTQ_HH__ -#define __EVENTQ_HH__ +#ifndef __SIM_EVENTQ_HH__ +#define __SIM_EVENTQ_HH__ #include <assert.h> @@ -43,11 +43,24 @@ #include "sim/host.hh" // for Tick #include "base/fast_alloc.hh" -#include "sim/serialize.hh" #include "base/trace.hh" +#include "sim/serialize.hh" class EventQueue; // forward declaration +////////////////////// +// +// Main Event Queue +// +// Events on this queue are processed at the *beginning* of each +// cycle, before the pipeline simulation is performed. +// +// defined in eventq.cc +// +////////////////////// +extern EventQueue mainEventQueue; + + /* * An item on an event queue. The action caused by a given * event is specified by deriving a subclass and overriding the @@ -228,7 +241,7 @@ DelayFunction(Tick when, T *object) public: DelayEvent(Tick when, T *o) : Event(&mainEventQueue), object(o) - { setFlags(AutoDestroy); schedule(when); } + { setFlags(this->AutoDestroy); schedule(when); } void process() { (object->*F)(); } const char *description() { return "delay"; } }; @@ -386,16 +399,5 @@ EventQueue::reschedule(Event *event) } -////////////////////// -// -// Main Event Queue -// -// Events on this queue are processed at the *beginning* of each -// cycle, before the pipeline simulation is performed. -// -// defined in eventq.cc -// -////////////////////// -extern EventQueue mainEventQueue; -#endif // __EVENTQ_HH__ +#endif // __SIM_EVENTQ_HH__ diff --git a/sim/param.cc b/sim/param.cc index d666463c9..d16578a2d 100644 --- a/sim/param.cc +++ b/sim/param.cc @@ -493,11 +493,11 @@ EnumVectorParam<Map>::showType(ostream &os) const showEnumType(os, map, num_values); } -template EnumParam<const char *>; -template EnumVectorParam<const char *>; +template class EnumParam<const char *>; +template class EnumVectorParam<const char *>; -template EnumParam<EnumParamMap>; -template EnumVectorParam<EnumParamMap>; +template class EnumParam<EnumParamMap>; +template class EnumVectorParam<EnumParamMap>; //////////////////////////////////////////////////////////////////////// // diff --git a/sim/param.hh b/sim/param.hh index ac57afa31..f4b9d3450 100644 --- a/sim/param.hh +++ b/sim/param.hh @@ -26,9 +26,10 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PARAM_HH__ -#define __PARAM_HH__ +#ifndef __SIM_PARAM_HH__ +#define __SIM_PARAM_HH__ +#include <iostream> #include <list> #include <string> #include <vector> @@ -524,7 +525,7 @@ class MappedEnumParam : public EnumParam<EnumParamMap> { if (!isValid()) die("not found"); - return (ENUM)value[n]; + return (ENUM)value[this->n]; } }; @@ -782,4 +783,4 @@ SimObjectVectorParam<OBJ_CLASS *>::showType(std::ostream &os) const \ template <class T> bool parseParam(const std::string &str, T &data); template <class T> void showParam(std::ostream &os, const T &data); -#endif // _PARAM_HH +#endif // _SIM_PARAM_HH_ diff --git a/sim/pyconfig/SConscript b/sim/pyconfig/SConscript index 127b0efae..5708ac9a8 100644 --- a/sim/pyconfig/SConscript +++ b/sim/pyconfig/SConscript @@ -28,14 +28,15 @@ import os, os.path, re -def WriteEmbeddedPyFile(target, source, path, name, ext): +def WriteEmbeddedPyFile(target, source, path, name, ext, filename): if isinstance(source, str): source = file(source, 'r') if isinstance(target, str): target = file(target, 'w') - print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`) + print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \ + (`path`, `name`, `ext`, `filename`) for line in source: line = line @@ -105,7 +106,7 @@ def MakeEmbeddedPyFile(target, source, env): name,ext = pyfile.split('.') if name == '__init__': node['.hasinit'] = True - node[pyfile] = (src,name,ext) + node[pyfile] = (src,name,ext,src) done = False while not done: @@ -136,12 +137,12 @@ def MakeEmbeddedPyFile(target, source, env): raise NameError, 'package directory missing __init__.py' populate(entry, path + [ name ]) else: - pyfile,name,ext = entry - files.append((pyfile, path, name, ext)) + pyfile,name,ext,filename = entry + files.append((pyfile, path, name, ext, filename)) populate(tree) - for pyfile, path, name, ext in files: - WriteEmbeddedPyFile(target, pyfile, path, name, ext) + for pyfile, path, name, ext, filename in files: + WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename) CFileCounter = 0 def MakePythonCFile(target, source, env): diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 4e2a377b0..4e3a4103c 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -26,14 +26,14 @@ from __future__ import generators import os, re, sys, types +noDot = False +try: + import pydot +except: + noDot = True env = {} env.update(os.environ) -def defined(key): - return env.has_key(key) - -def define(key, value = True): - env[key] = value def panic(*args, **kwargs): sys.exit(*args, **kwargs) @@ -59,9 +59,6 @@ class Singleton(type): cls._instance = super(Singleton, cls).__call__(*args, **kwargs) return cls._instance -if os.environ.has_key('FULL_SYSTEM'): - FULL_SYSTEM = True - ##################################################################### # # M5 Python Configuration Utility @@ -209,6 +206,17 @@ def isSimObjSequence(value): return True +def isParamContext(value): + try: + return issubclass(value, ParamContext) + except: + return False + + +class_decorator = '_M5M5_SIMOBJECT_' +expr_decorator = '_M5M5_EXPRESSION_' +dot_decorator = '_M5M5_DOT_' + # The metaclass for ConfigNode (and thus for everything that derives # from ConfigNode, including SimObject). This class controls how new # classes that derive from ConfigNode are instantiated, and provides @@ -218,7 +226,6 @@ def isSimObjSequence(value): class MetaConfigNode(type): keywords = { 'abstract' : types.BooleanType, 'check' : types.FunctionType, - '_init' : types.FunctionType, 'type' : (types.NoneType, types.StringType) } # __new__ is called before __init__, and is where the statements @@ -234,6 +241,11 @@ class MetaConfigNode(type): '_disable' : {} } for key,val in dict.items(): + del dict[key] + + if key.startswith(expr_decorator): + key = key[len(expr_decorator):] + if mcls.keywords.has_key(key): if not isinstance(val, mcls.keywords[key]): raise TypeError, \ @@ -243,11 +255,9 @@ class MetaConfigNode(type): if isinstance(val, types.FunctionType): val = classmethod(val) priv[key] = val - del dict[key] elif key.startswith('_'): priv[key] = val - del dict[key] elif not isNullPointer(val) and isConfigNode(val): dict[key] = val() @@ -255,19 +265,22 @@ class MetaConfigNode(type): elif isSimObjSequence(val): dict[key] = [ v() for v in val ] + else: + dict[key] = val + # If your parent has a value in it that's a config node, clone it. for base in bases: if not isConfigNode(base): continue - for name,value in base._values.iteritems(): - if dict.has_key(name): + for key,value in base._values.iteritems(): + if dict.has_key(key): continue if isConfigNode(value): - priv['_values'][name] = value() + priv['_values'][key] = value() elif isSimObjSequence(value): - priv['_values'][name] = [ val() for val in value ] + priv['_values'][key] = [ val() for val in value ] # entries left in dict will get passed to __init__, where we'll # deal with them as params. @@ -281,12 +294,12 @@ class MetaConfigNode(type): cls._bases = [c for c in cls.__mro__ if isConfigNode(c)] # initialize attributes with values from class definition - for pname,value in dict.iteritems(): - setattr(cls, pname, value) - - if hasattr(cls, '_init'): - cls._init() - del cls._init + for key,value in dict.iteritems(): + key = key.split(dot_decorator) + c = cls + for item in key[:-1]: + c = getattr(c, item) + setattr(c, key[-1], value) def _isvalue(cls, name): for c in cls._bases: @@ -378,7 +391,6 @@ class MetaConfigNode(type): raise AttributeError, \ "object '%s' has no attribute '%s'" % (cls.__name__, cls) - # Set attribute (called on foo.attr = value when foo is an # instance of class cls). def __setattr__(cls, attr, value): @@ -435,7 +447,7 @@ class MetaConfigNode(type): # Print instance info to .ini file. def instantiate(cls, name, parent = None): - instance = Node(name, cls, cls.type, parent) + instance = Node(name, cls, cls.type, parent, isParamContext(cls)) if hasattr(cls, 'check'): cls.check() @@ -456,7 +468,11 @@ class MetaConfigNode(type): if cls._getdisable(pname): continue - value = cls._getvalue(pname) + try: + value = cls._getvalue(pname) + except: + print 'Error getting %s' % pname + raise if isConfigNode(value): value = instance.child_objects[value] @@ -533,6 +549,9 @@ class ConfigNode(object): # v = param.convert(value) # object.__setattr__(self, attr, v) +class ParamContext(ConfigNode): + pass + # SimObject is a minimal extension of ConfigNode, implementing a # hierarchy node that corresponds to an M5 SimObject. It prints out a # "type=" line to indicate its SimObject class, prints out the @@ -569,7 +588,7 @@ class NodeParam(object): class Node(object): all = {} - def __init__(self, name, realtype, type, parent): + def __init__(self, name, realtype, type, parent, paramcontext): self.name = name self.realtype = realtype self.type = type @@ -580,6 +599,7 @@ class Node(object): self.top_child_names = {} self.params = [] self.param_names = {} + self.paramcontext = paramcontext path = [ self.name ] node = self.parent @@ -642,7 +662,7 @@ class Node(object): % (self.name, ptype, value._path) found, done = obj.find(ptype, value._path) if isinstance(found, Proxy): - done = false + done = False obj = obj.parent return found @@ -678,7 +698,8 @@ class Node(object): # instantiate children in same order they were added for # backward compatibility (else we can end up with cpu1 # before cpu0). - print 'children =', ' '.join([ c.name for c in self.children]) + children = [ c.name for c in self.children if not c.paramcontext] + print 'children =', ' '.join(children) for param in self.params: try: @@ -699,6 +720,48 @@ class Node(object): for c in self.children: c.display() + # print type and parameter values to .ini file + def outputDot(self, dot): + + + label = "{%s|" % self.path + if isSimObject(self.realtype): + label += '%s|' % self.type + + if self.children: + # instantiate children in same order they were added for + # backward compatibility (else we can end up with cpu1 + # before cpu0). + for c in self.children: + dot.add_edge(pydot.Edge(self.path,c.path, style="bold")) + + simobjs = [] + for param in self.params: + try: + if param.value is None: + raise AttributeError, 'Parameter with no value' + + value = param.convert(param.value) + string = param.string(value) + except: + print 'exception in %s:%s' % (self.name, param.name) + raise + ptype = eval(param.ptype) + if isConfigNode(ptype) and string != "Null": + simobjs.append(string) + else: + label += '%s = %s\\n' % (param.name, string) + + for so in simobjs: + label += "|<%s> %s" % (so, so) + dot.add_edge(pydot.Edge("%s:%s" % (self.path, so), so, tailport="w")) + label += '}' + dot.add_node(pydot.Node(self.path,shape="Mrecord",label=label)) + + # recursively dump out children + for c in self.children: + c.outputDot(dot) + def _string(cls, value): if not isinstance(value, Node): raise AttributeError, 'expecting %s got %s' % (Node, value) @@ -1196,12 +1259,9 @@ class Enum(type): # "Constants"... handy aliases for various values. # -# For compatibility with C++ bool constants. -false = False -true = True - # Some memory range specifications use this as a default upper bound. MAX_ADDR = Addr._max +MaxTick = Tick._max # For power-of-two sizing, e.g. 64*K gives an integer value 65536. K = 1024 @@ -1234,6 +1294,15 @@ def instantiate(root): instance = root.instantiate('root') instance.fixup() instance.display() + if not noDot: + dot = pydot.Dot() + instance.outputDot(dot) + dot.orientation = "portrait" + dot.size = "8.5,11" + dot.ranksep="equally" + dot.rank="samerank" + dot.write("config.dot") + dot.write_ps("config.ps") from objects import * diff --git a/sim/serialize.cc b/sim/serialize.cc index 2a5e3d398..3a073f68d 100644 --- a/sim/serialize.cc +++ b/sim/serialize.cc @@ -29,6 +29,7 @@ #include <sys/time.h> #include <sys/types.h> #include <sys/stat.h> +#include <errno.h> #include <fstream> #include <list> diff --git a/sim/startup.cc b/sim/startup.cc index ebb4c0bc0..7cc0ac8fb 100644 --- a/sim/startup.cc +++ b/sim/startup.cc @@ -29,20 +29,32 @@ #include <list> #include "base/misc.hh" -#include "sim/startup.hh" #include "sim/debug.hh" +#include "sim/startup.hh" typedef std::list<StartupCallback *> startupq_t; -startupq_t &startupq() { static startupq_t queue; return queue; } -StartupCallback::StartupCallback() { startupq().push_back(this); } -StartupCallback::~StartupCallback() { startupq().remove(this); } + +startupq_t *startupq = NULL; + +StartupCallback::StartupCallback() +{ + if (startupq == NULL) + startupq = new startupq_t; + startupq->push_back(this); +} + +StartupCallback::~StartupCallback() +{ + startupq->remove(this); +} + void StartupCallback::startup() { } void SimStartup() { - startupq_t::iterator i = startupq().begin(); - startupq_t::iterator end = startupq().end(); + startupq_t::iterator i = startupq->begin(); + startupq_t::iterator end = startupq->end(); while (i != end) { (*i)->startup(); diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh index 77d104449..768bc3700 100644 --- a/sim/syscall_emul.hh +++ b/sim/syscall_emul.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __SYSCALL_EMUL_HH__ -#define __SYSCALL_EMUL_HH__ +#ifndef __SIM_SYSCALL_EMUL_HH__ +#define __SIM_SYSCALL_EMUL_HH__ /// /// @file syscall_emul.hh @@ -35,14 +35,16 @@ /// This file defines objects used to emulate syscalls from the target /// application on the host machine. +#include <errno.h> #include <string> #include "base/intmath.hh" // for RoundUp -#include "targetarch/isa_traits.hh" // for Addr #include "mem/functional_mem/functional_memory.hh" +#include "targetarch/isa_traits.hh" // for Addr -class Process; -class ExecContext; +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "sim/process.hh" /// /// System call descriptor. @@ -197,6 +199,36 @@ int unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc); /// Target rename() handler. int renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc); +/// This struct is used to build an target-OS-dependent table that +/// maps the target's open() flags to the host open() flags. +struct OpenFlagTransTable { + int tgtFlag; //!< Target system flag value. + int hostFlag; //!< Corresponding host system flag value. +}; + + + +/// A readable name for 1,000,000, for converting microseconds to seconds. +const int one_million = 1000000; + +/// Approximate seconds since the epoch (1/1/1970). About a billion, +/// by my reckoning. We want to keep this a constant (not use the +/// real-world time) to keep simulations repeatable. +const unsigned seconds_since_epoch = 1000000000; + +/// Helper function to convert current elapsed time to seconds and +/// microseconds. +template <class T1, class T2> +void +getElapsedTime(T1 &sec, T2 &usec) +{ + int cycles_per_usec = ticksPerSecond / one_million; + + int elapsed_usecs = curTick / cycles_per_usec; + sec = elapsed_usecs / one_million; + usec = elapsed_usecs % one_million; +} + ////////////////////////////////////////////////////////////////////// // // The following emulation functions are generic, but need to be @@ -238,14 +270,6 @@ ioctlFunc(SyscallDesc *desc, int callnum, Process *process, } } -/// This struct is used to build an target-OS-dependent table that -/// maps the target's open() flags to the host open() flags. -struct OpenFlagTransTable { - int tgtFlag; //!< Target system flag value. - int hostFlag; //!< Corresponding host system flag value. -}; - - /// Target open() handler. template <class OS> int @@ -260,7 +284,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, if (path == "/dev/sysdev0") { // This is a memory-mapped high-resolution timer device on Alpha. // We don't support it, so just punt. - DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << endl; + DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << std::endl; return -ENOENT; } @@ -278,7 +302,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, // any target flags left? if (tgtFlags != 0) - cerr << "Syscall: open: cannot decode flags: " << tgtFlags << endl; + std::cerr << "Syscall: open: cannot decode flags: " << tgtFlags << std::endl; #ifdef __CYGWIN32__ hostFlags |= O_BINARY; @@ -414,7 +438,7 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, break; default: - cerr << "getrlimitFunc: unimplemented resource " << resource << endl; + std::cerr << "getrlimitFunc: unimplemented resource " << resource << std::endl; abort(); break; } @@ -423,28 +447,6 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, return 0; } -/// A readable name for 1,000,000, for converting microseconds to seconds. -const int one_million = 1000000; - -/// Approximate seconds since the epoch (1/1/1970). About a billion, -/// by my reckoning. We want to keep this a constant (not use the -/// real-world time) to keep simulations repeatable. -const unsigned seconds_since_epoch = 1000000000; - -/// Helper function to convert current elapsed time to seconds and -/// microseconds. -template <class T1, class T2> -void -getElapsedTime(T1 &sec, T2 &usec) -{ - int cycles_per_usec = ticksPerSecond / one_million; - - int elapsed_usecs = curTick / cycles_per_usec; - sec = elapsed_usecs / one_million; - usec = elapsed_usecs % one_million; -} - - /// Target gettimeofday() handler. template <class OS> int @@ -476,7 +478,7 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process, // plow ahead DCOUT(SyscallWarnings) << "Warning: getrusage() only supports RUSAGE_SELF." - << " Parameter " << who << " ignored." << endl; + << " Parameter " << who << " ignored." << std::endl; } getElapsedTime(rup->ru_utime.tv_sec, rup->ru_utime.tv_usec); @@ -502,6 +504,4 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process, return 0; } - - -#endif // __SYSCALL_EMUL_HH__ +#endif // __SIM_SYSCALL_EMUL_HH__ diff --git a/sim/universe.cc b/sim/universe.cc index 69563650d..115f6f790 100644 --- a/sim/universe.cc +++ b/sim/universe.cc @@ -28,6 +28,7 @@ #include <sys/types.h> #include <sys/stat.h> +#include <errno.h> #include <cstring> #include <fstream> @@ -142,7 +143,8 @@ CREATE_SIM_OBJECT(Root) __ticksPerNS = freq / 1.0e9; __ticksPerPS = freq / 1.0e12; - if (output_dir.isValid()) { + outputDirectory = output_dir; + if (!outputDirectory.empty()) { outputDirectory = output_dir; // guarantee that directory ends with a '/' @@ -158,9 +160,10 @@ CREATE_SIM_OBJECT(Root) } outputStream = makeOutputStream(output_file); - configStream = config_output_file.isValid() - ? makeOutputStream(config_output_file) - : outputStream; + configStream = outputStream; + string cof = config_output_file; + if (!cof.empty()) + configStream = makeOutputStream(cof); return root; } diff --git a/test/genini.py b/test/genini.py index e96d7069c..db1a7a5b0 100644 --- a/test/genini.py +++ b/test/genini.py @@ -31,7 +31,7 @@ sys.path.append('..') sys.path.append('../configs/kernel') sys.path.append('../sim/pyconfig') -from importer import mpy_exec, AddToPath +from importer import mpy_exec, mpy_execfile, AddToPath from m5config import * try: @@ -51,7 +51,7 @@ except getopt.GetoptError: for arg in args: AddToPath(os.path.dirname(arg)) - mpy_exec(file(arg, 'r'), globals()) + mpy_execfile(arg) if globals().has_key('root') and isinstance(root, type) \ and issubclass(root, Root): diff --git a/util/stats/info.py b/util/stats/info.py index d11619765..01d7bdb0f 100644 --- a/util/stats/info.py +++ b/util/stats/info.py @@ -3,6 +3,8 @@ import operator, re, types source = None display_run = 0 +global globalTicks +globalTicks = None def issequence(t): return isinstance(t, types.TupleType) or isinstance(t, types.ListType) @@ -130,6 +132,7 @@ def cmp(a, b): return 1 class Statistic(object): + def __init__(self, data): self.__dict__.update(data.__dict__) if not self.__dict__.has_key('value'): @@ -138,9 +141,25 @@ class Statistic(object): self.__dict__['bins'] = None if not self.__dict__.has_key('ticks'): self.__dict__['ticks'] = None + if 'vc' not in self.__dict__: + self.vc = {} def __getattribute__(self, attr): + if attr == 'ticks': + if self.__dict__['ticks'] != globalTicks: + self.__dict__['value'] = None + self.__dict__['ticks'] = globalTicks + return self.__dict__['ticks'] if attr == 'value': + if self.__dict__['ticks'] != globalTicks: + if self.__dict__['ticks'] != None and \ + len(self.__dict__['ticks']) == 1: + self.vc[self.__dict__['ticks'][0]] = self.__dict__['value'] + self.__dict__['ticks'] = globalTicks + if len(globalTicks) == 1 and self.vc.has_key(globalTicks[0]): + self.__dict__['value'] = self.vc[globalTicks[0]] + else: + self.__dict__['value'] = None if self.__dict__['value'] == None: self.__dict__['value'] = self.getValue() return self.__dict__['value'] @@ -152,11 +171,12 @@ class Statistic(object): if attr == 'bins': if value is not None: value = source.getBin(value) - elif attr == 'ticks' and type(value) is str: - value = [ int(x) for x in value.split() ] + #elif attr == 'ticks' and type(value) is str: + # value = [ int(x) for x in value.split() ] self.__dict__[attr] = value self.__dict__['value'] = None + self.vc = {} else: super(Statistic, self).__setattr__(attr, value) @@ -287,7 +307,7 @@ class Scalar(Statistic,FormulaStat): class Vector(Statistic,FormulaStat): def getValue(self): - return source.data(self, self.bins); + return source.data(self, self.bins, self.ticks); def display(self): import display @@ -304,7 +324,7 @@ class Vector(Statistic,FormulaStat): def __eq__(self, other): if issequence(self.value) != issequence(other.value): - return false + return False if issequence(self.value): if len(self.value) != len(other.value): diff --git a/util/stats/stats.py b/util/stats/stats.py index 62819c397..c9b7ab2ac 100755 --- a/util/stats/stats.py +++ b/util/stats/stats.py @@ -2,10 +2,23 @@ from __future__ import division import re, sys, math + def usage(): print '''\ Usage: %s [-E] [-F] [-d <db> ] [-g <get> ] [-h <host>] [-p] - [-s <system>] [-r <runs> ] [-u <username>] <command> [command args] + [-s <system>] [-r <runs> ] [-T <samples>] [-u <username>] + <command> [command args] + + commands extra parameters description + ----------- ------------------ --------------------------------------- + bins [regex] List bins (only matching regex) + formula <formula> Evaluated formula specified + formulas [regex] List formulas (only matching regex) + runs none List all runs in database + samples none List samples present in database + stability <pairnum> <stats> Calculated statistical info about stats + stat <regex> Show stat data (only matching regex) + stats [regex] List all stats (only matching regex) ''' % sys.argv[0] sys.exit(1) @@ -250,55 +263,85 @@ def commands(options, command, args): return if command == 'stability': - stats = info.source.getStat(args[0]) - info.source.get = "avg" + if len(args) < 2: + raise CommandException + + try: + merge = int(args[0]) + except ValueError: + usage() + stats = info.source.getStat(args[1]) + info.source.get = "sum" + #loop through all the stats selected for stat in stats: print "%s:" % stat.name - print "%-30s %12s %12s %4s %5s %5s %5s" % \ - ("run name", "average", "stdev", ">10%", ">1SDV", ">2SDV", "SAMP") - print "%-30s %12s %12s %4s %5s %5s %5s" % \ - ("------------------------------", "------------", - "------------", "----", "-----", "-----", "-----") + print "%-20s %12s %12s %4s %5s %5s %5s %10s" % \ + ("run name", "average", "stdev", ">10%", ">1SDV", ">2SDV", "SAMP", "CV") + print "%-20s %12s %12s %4s %5s %5s %5s %10s" % \ + ("--------------------", "------------", + "------------", "----", "-----", "-----", "-----", "----------") #loop through all the selected runs for run in runs: info.display_run = run.run; runTicks = info.source.retTicks([ run ]) #throw away the first one, it's 0 runTicks.pop(0) - stat.ticks = runTicks - avg = float(stat) + info.globalTicks = runTicks + avg = 0 stdev = 0 numoutsideavg = 0 numoutside1std = 0 numoutside2std = 0 - + pairRunTicks = [] + if float(stat) == 1e300*1e300: + continue + for t in range(0, len(runTicks)-(merge-1), merge): + tempPair = [] + for p in range(0,merge): + tempPair.append(runTicks[t+p]) + pairRunTicks.append(tempPair) #loop through all the various ticks for each run - for tick in runTicks: - stat.ticks = str(tick) + for tick in pairRunTicks: + info.globalTicks = tick + avg += float(stat) + avg /= len(pairRunTicks) + for tick in pairRunTicks: + info.globalTicks = tick val = float(stat) - if (val < (avg * .9)) or (val > (avg * 1.1)): - numoutsideavg += 1 stdev += pow((val-avg),2) - - stdev = math.sqrt(stdev / len(runTicks)) - for tick in runTicks: - stat.ticks = str(tick) + stdev = math.sqrt(stdev / len(pairRunTicks)) + for tick in pairRunTicks: + info.globalTicks = tick val = float(stat) + if (val < (avg * .9)) or (val > (avg * 1.1)): + numoutsideavg += 1 if (val < (avg - stdev)) or (val > (avg + stdev)): numoutside1std += 1 if (val < (avg - (2*stdev))) or (val > (avg + (2*stdev))): numoutside2std += 1 - - print "%-30s %12s %12s %4s %5s %5s %5s" % \ - (run.name, "%.1f" % avg, "%.1f" % stdev, - "%d" % numoutsideavg, "%d" % numoutside1std, - "%d" % numoutside2std, "%d" % len(runTicks)) + if avg > 1000: + print "%-20s %12s %12s %4s %5s %5s %5s %10s" % \ + (run.name, "%.1f" % avg, "%.1f" % stdev, + "%d" % numoutsideavg, "%d" % numoutside1std, + "%d" % numoutside2std, "%d" % len(pairRunTicks), + "%.3f" % (stdev/avg*100)) + elif avg > 100: + print "%-20s %12s %12s %4s %5s %5s %5s %10s" % \ + (run.name, "%.1f" % avg, "%.1f" % stdev, + "%d" % numoutsideavg, "%d" % numoutside1std, + "%d" % numoutside2std, "%d" % len(pairRunTicks), + "%.5f" % (stdev/avg*100)) + else: + print "%-20s %12s %12s %4s %5s %5s %5s %10s" % \ + (run.name, "%.5f" % avg, "%.5f" % stdev, + "%d" % numoutsideavg, "%d" % numoutside1std, + "%d" % numoutside2std, "%d" % len(pairRunTicks), + "%.7f" % (stdev/avg*100)) return - if command == 'stats': if len(args) == 0: info.source.listStats() @@ -320,7 +363,7 @@ def commands(options, command, args): else: if options.ticks: print 'only displaying sample %s' % options.ticks - stat.ticks = options.ticks + info.globalTicks = [ int(x) for x in options.ticks.split() ] if options.binned: print 'kernel ticks' diff --git a/util/tracediff b/util/tracediff index a95ce8b82..402abbe55 100755 --- a/util/tracediff +++ b/util/tracediff @@ -1,5 +1,5 @@ #! /usr/bin/env perl -# Copyright (c) 2003-2004 The Regents of The University of Michigan +# Copyright (c) 2003-2005 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ $simargs = '"' . join('" "', @ARGV) . '"'; # Redirect config output to cout so that gets diffed too (in case # that's the source of the problem). -$simargs += " --Universe:config_output_file=cout"; +$simargs .= " --root:config_output_file=cout"; $cmd1 = "$sim1 $simargs --stats:text_file=tracediff-$$-1.stats 2>&1 |"; $cmd2 = "$sim2 $simargs --stats:text_file=tracediff-$$-2.stats 2>&1 |"; |