diff options
| author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-05 18:10:30 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-05 18:10:30 -0500 |
| commit | 2435918ac28b1401fcd7bb1114e62a7a6f2310a9 (patch) | |
| tree | 9eb76ae223fd6fabfa6f8faa6f661b247ad0cc41 | |
| parent | 46b56bb7b6ac2a5f069aa1f79279f46d0395eb15 (diff) | |
| download | gem5-2435918ac28b1401fcd7bb1114e62a7a6f2310a9.tar.xz | |
new mp eio test
10 files changed, 2493 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript index 762262dfa..3e0eed941 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -223,7 +223,8 @@ if env['FULL_SYSTEM']: 't1000-simple-timing'] else: - configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest'] + configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest', + 'simple-atomic-mp', 'simple-timing-mp'] cwd = os.getcwd() os.chdir(str(Dir('.').srcdir)) diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini new file mode 100644 index 000000000..78394da28 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -0,0 +1,526 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=1 +defer_registration=false +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=2 +defer_registration=false +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=3 +defer_registration=false +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt new file mode 100644 index 000000000..5a19ce746 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt @@ -0,0 +1,627 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1660926 # Simulator instruction rate (inst/s) +host_seconds 1.20 # Real time elapsed on the host +host_tick_rate 207598549 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2000004 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180793 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180775 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124435 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56340 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499556 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500032 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500019 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 182222 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180140 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180793 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180775 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124435 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56350 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56340 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499556 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500032 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 500019 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.num_insts 500001 # Number of instructions executed +system.cpu1.num_refs 182222 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499556 # number of overall hits +system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500032 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500019 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180140 # number of overall hits +system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180793 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180775 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124443 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124435 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56350 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56340 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499556 # number of overall hits +system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500032 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500019 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.num_insts 500001 # Number of instructions executed +system.cpu3.num_refs 182222 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr new file mode 100644 index 000000000..e0d5d4d73 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr @@ -0,0 +1,13 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout new file mode 100644 index 000000000..b79194a00 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 17:12:56 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 17:19:26 +M5 executing on dhcp128036150089.central.yale.edu +command line: build/ALPHA_SE/m5.fast -d simple-atomic wrapper.py +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini new file mode 100644 index 000000000..0077a0004 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -0,0 +1,514 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=1 +defer_registration=false +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu1.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dtb] +type=AlphaDTB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.itb] +type=AlphaITB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu1.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=2 +defer_registration=false +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu2.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.port[6] + +[system.cpu2.dtb] +type=AlphaDTB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.port[5] + +[system.cpu2.itb] +type=AlphaITB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu2.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache itb tracer workload +clock=500 +cpu_id=3 +defer_registration=false +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu3.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.port[8] + +[system.cpu3.dtb] +type=AlphaDTB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=1000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.port[7] + +[system.cpu3.itb] +type=AlphaITB +size=48 + +[system.cpu3.tracer] +type=ExeTracer + +[system.cpu3.workload] +type=EioProcess +chkpt= +errout=cerr +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +input=None +max_stack_size=67108864 +output=cout +system=system + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +cpu_side_filter_ranges= +hash_delay=1 +latency=10000 +max_miss_count=0 +mem_side_filter_ranges= +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.mem_side system.physmem.port[0] + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt new file mode 100644 index 000000000..d00f39e87 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt @@ -0,0 +1,717 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 803390 # Simulator instruction rate (inst/s) +host_seconds 2.49 # Real time elapsed on the host +host_tick_rate 296594923 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1999941 # Number of instructions simulated +sim_seconds 0.000738 # Number of seconds simulated +sim_ticks 738387000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180136 # number of overall hits +system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 635 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.accesses 180789 # DTB accesses +system.cpu0.dtb.acv 0 # DTB access violations +system.cpu0.dtb.hits 180771 # DTB hits +system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.read_accesses 124440 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124432 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56349 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56339 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499537 # number of overall hits +system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use +system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.accesses 500013 # ITB accesses +system.cpu0.itb.acv 0 # ITB acv +system.cpu0.itb.hits 500000 # ITB hits +system.cpu0.itb.misses 13 # ITB misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 1476774 # number of cpu cycles simulated +system.cpu0.num_insts 499981 # Number of instructions executed +system.cpu0.num_refs 182218 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180133 # number of overall hits +system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 635 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.accesses 180786 # DTB accesses +system.cpu1.dtb.acv 0 # DTB access violations +system.cpu1.dtb.hits 180768 # DTB hits +system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.read_accesses 124437 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124429 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56349 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56339 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499531 # number of overall hits +system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use +system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.accesses 500007 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 499994 # ITB hits +system.cpu1.itb.misses 13 # ITB misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 1476774 # number of cpu cycles simulated +system.cpu1.num_insts 499975 # Number of instructions executed +system.cpu1.num_refs 182214 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180140 # number of overall hits +system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 635 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.accesses 180793 # DTB accesses +system.cpu2.dtb.acv 0 # DTB access violations +system.cpu2.dtb.hits 180775 # DTB hits +system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499557 # number of overall hits +system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.accesses 500033 # ITB accesses +system.cpu2.itb.acv 0 # ITB acv +system.cpu2.itb.hits 500020 # ITB hits +system.cpu2.itb.misses 13 # ITB misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 1476774 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180137 # number of overall hits +system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 635 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.accesses 180790 # DTB accesses +system.cpu3.dtb.acv 0 # DTB access violations +system.cpu3.dtb.hits 180772 # DTB hits +system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.read_accesses 124441 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124433 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56349 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56339 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499540 # number of overall hits +system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use +system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.accesses 500016 # ITB accesses +system.cpu3.itb.acv 0 # ITB acv +system.cpu3.itb.hits 500003 # ITB hits +system.cpu3.itb.misses 13 # ITB misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 1476774 # number of cpu cycles simulated +system.cpu3.num_insts 499984 # Number of instructions executed +system.cpu3.num_refs 182219 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses +system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses +system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_miss_latency 178284000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses +system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2300 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use +system.l2c.total_refs 276 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr new file mode 100644 index 000000000..e0d5d4d73 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr @@ -0,0 +1,13 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +warn: be nice to actually delete the event here + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout new file mode 100644 index 000000000..2976be712 --- /dev/null +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout @@ -0,0 +1,24 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 5 2008 17:12:56 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 17:26:45 +M5 executing on dhcp128036150089.central.yale.edu +command line: build/ALPHA_SE/m5.fast -d output wrapper.py +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +main dictionary has 1245 entries +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +49508 bytes wasted +>>>>Exiting @ tick 738387000 because a thread reached the max instruction count diff --git a/tests/quick/30.eio-mp/test.py b/tests/quick/30.eio-mp/test.py new file mode 100644 index 000000000..3dbb7614a --- /dev/null +++ b/tests/quick/30.eio-mp/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) + +for i in xrange(nb_cores): + root.system.cpu[i].workload = process() + root.system.cpu[i].max_insts_any_thread = 500000 |