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authorChander Sudanthi <chander.sudanthi@arm.com>2013-10-31 13:41:13 -0500
committerChander Sudanthi <chander.sudanthi@arm.com>2013-10-31 13:41:13 -0500
commit3e6da89419e5d53dc8a0df446473a4f28808bc46 (patch)
tree12f3418eda6eb4255e9c9b06fabf240f134a1ca2
parentd17529b046d832f889a0fdb506c3b8d1aed5cccb (diff)
downloadgem5-3e6da89419e5d53dc8a0df446473a4f28808bc46.tar.xz
ARM: add support for TEEHBR access
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier in arch/arm/kernel/thumbee.c. The Linux kernel code just seems to be saving and restoring the register. This patch adds support for the TEEHBR cp14 register. Note, this may be a special case when restoring from an image that was run on a system that supports ThumbEE.
-rw-r--r--src/arch/arm/miscregs.cc23
-rw-r--r--src/arch/arm/miscregs.hh2
-rw-r--r--src/sim/serialize.hh2
-rwxr-xr-xutil/cpt_upgrader.py13
4 files changed, 39 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index a8abbf692..3a64b557a 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -63,9 +63,32 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
return NUM_MISCREGS;
}
default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ case 1:
+ switch (opc1) {
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (opc2) {
+ case 0:
+ return MISCREG_TEEHBR;
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ default:
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
crn, opc1, crm, opc2);
return NUM_MISCREGS;
+ }
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
}
default:
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 02c03a7fc..13234ddf5 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -121,6 +121,7 @@ namespace ArmISA
MISCREG_DBGDEVID2,
MISCREG_DBGDEVID1,
MISCREG_DBGDEVID,
+ MISCREG_TEEHBR,
// CP15 registers
MISCREG_CP15_START,
@@ -288,6 +289,7 @@ namespace ArmISA
"DBGDEVID2",
"DBGDEVID1",
"DBGDEVID",
+ "TEEHBR",
"sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 46d3fe82c..1e9566519 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -57,7 +57,7 @@ class SimObject;
* SimObject shouldn't cause the version number to increase, only changes to
* existing objects such as serializing/unserializing more state, changing sizes
* of serialized arrays, etc. */
-static const uint64_t gem5CheckpointVersion = 0x0000000000000007;
+static const uint64_t gem5CheckpointVersion = 0x0000000000000008;
template <class T>
void paramOut(std::ostream &os, const std::string &name, const T &param);
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index b5b54c1f2..e6ee7d562 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -217,6 +217,18 @@ def from_6(cpt):
if cpt.has_option(sec, "curSector"):
cpt.set(sec, "dmaAborted", "false")
+# Version 8 of the checkpoint adds an ARM MISCREG
+def from_7(cpt):
+ if cpt.get('root','isa') == 'arm':
+ for sec in cpt.sections():
+ import re
+ # Search for all ISA sections
+ if re.search('.*sys.*\.cpu.*\.isa', sec):
+ mr = cpt.get(sec, 'miscRegs').split()
+ # Add dummy value for MISCREG_TEEHBR
+ mr.insert(51,0);
+ cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+
migrations = []
migrations.append(from_0)
@@ -226,6 +238,7 @@ migrations.append(from_3)
migrations.append(from_4)
migrations.append(from_5)
migrations.append(from_6)
+migrations.append(from_7)
verbose_print = False