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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-01-31 15:03:04 -0500 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-01-31 15:03:04 -0500 |
commit | 4c40848dcc4ac02072d18520da9190f4afe33282 (patch) | |
tree | a64bf34c31873d0fdc79d2237ebbcc37994cd8f9 | |
parent | 0d74f273136627a02a5d70b4dc67b59507c3d559 (diff) | |
download | gem5-4c40848dcc4ac02072d18520da9190f4afe33282.tar.xz |
Remove non-needed functions, fix return values of completion handler.
--HG--
extra : convert_revision : 7c0cb6b13ba68650d54cdc35779517e8c4b5e3ff
-rw-r--r-- | cpu/simple/cpu.hh | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ac4e1cf22..8573a5258 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -80,10 +80,10 @@ class SimpleCPU : public BaseCPU protected: virtual bool recvTiming(Packet &pkt) - { return cpu->processCacheCompletion(pkt); } + { cpu->processCacheCompletion(pkt); return true; } virtual Tick recvAtomic(Packet &pkt) - { return cpu->processCacheCompletion(pkt); } + { cpu->processCacheCompletion(pkt); return CurTick; } virtual void recvFunctional(Packet &pkt) { cpu->processCacheCompletion(pkt); } @@ -96,10 +96,6 @@ class SimpleCPU : public BaseCPU CpuPort icache_port; CpuPort dcache_port; - bool recvTiming(Packet &pkt); - Tick recvAtomic(Packet &pkt); - void recvFunctional(Packet &pkt); - public: // main simulation loop (one cycle) void tick(); |