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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | 504ac6518bea90d614c2d2394fa3881f8557d798 (patch) | |
| tree | a7feb3b7b589dfe5819b557013ca1b58d490236a | |
| parent | 2c94bf7f30d3e9febe30485cf7182b650f48f4d5 (diff) | |
| download | gem5-504ac6518bea90d614c2d2394fa3881f8557d798.tar.xz | |
ARM: Decode the clz instruction.
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 7 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 16 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 2 |
4 files changed, 16 insertions, 11 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index fe8e1ed2e..ca74a2c1e 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -67,12 +67,7 @@ format DataOp { 1: decode OPCODE_7 { 0x0: decode MISC_OPCODE { 0x0: ArmMsrMrs::armMsrMrs(); - 0x1: decode OPCODE { - 0x9: ArmBx::armBx(); - 0xb: PredOp::clz({{ - Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); - }}); - } + 0x1: ArmBxClz::armBxClz(); 0x2: decode OPCODE { 0x9: WarnUnimpl::bxj(); } diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 999126081..07f39b129 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -71,10 +71,20 @@ def format ArmBlBlxImm() {{ ''' }}; -def format ArmBx() {{ +def format ArmBxClz() {{ decode_block = ''' - return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), - (ConditionCode)(uint32_t)machInst.condCode); + { + const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); + const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + if (OPCODE == 0x9) { + return new BxReg(machInst, rm, + (ConditionCode)(uint32_t)machInst.condCode); + } else if (OPCODE == 0xb) { + return new Clz(machInst, rd, rm); + } else { + return new Unknown(machInst); + } + } ''' }}; diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 9dca0e8a3..03f94075c 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -803,7 +803,7 @@ def format Thumb32DataProcReg() {{ break; case 0x3: if (op2 == 0) { - return new WarnUnimplemented("clz", machInst); + return new Clz(machInst, rd, rm); } } } diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index c673372bb..d7fa310b7 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -177,7 +177,7 @@ let {{ clzCode = ''' Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); ''' - clzIop = InstObjParams("clz", "ClzInst", "RevOp", + clzIop = InstObjParams("clz", "Clz", "RevOp", { "code": clzCode, "predicate_test": predicateTest }, []) header_output += RevOpDeclare.subst(clzIop) |