inorder-unified-tlb: use unified TLB instead of old TLB model

8 files changed, 28 insertions, 20 deletions

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index e431e7570..cbd3657f7 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -36,6 +36,7 @@
 #include "arch/alpha/intregfile.hh"
 #include "arch/alpha/miscregfile.hh"
 #include "arch/alpha/types.hh"
+#include "arch/alpha/mt.hh"
 #include "sim/faults.hh"
 
 #include <string>
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 83e94e74d..c5f06c3b2 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1264,17 +1264,17 @@ InOrderCPU::write(DynInstPtr inst)
     return mem_res->doDataAccess(inst);
 }
 
-TheISA::ITB*
+TheISA::TLB*
 InOrderCPU::getITBPtr()
 {
     TLBUnit *itb_res = dynamic_cast<TLBUnit*>(resPool->getResource(itbIdx));
-    return dynamic_cast<TheISA::ITB*>(itb_res->tlb());
+    return itb_res->tlb();
 }
 
 
-TheISA::DTB*
+TheISA::TLB*
 InOrderCPU::getDTBPtr()
 {
     TLBUnit *dtb_res = dynamic_cast<TLBUnit*>(resPool->getResource(dtbIdx));
-    return dynamic_cast<TheISA::DTB*>(dtb_res->tlb());
+    return dtb_res->tlb();
 }
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 7c1ad8264..fda2e4366 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -266,8 +266,8 @@ class InOrderCPU : public BaseCPU
     /** Communication structure that sits in between pipeline stages */
     StageQueue *stageQueue[ThePipeline::NumStages-1];
 
-    TheISA::ITB *getITBPtr();
-    TheISA::DTB *getDTBPtr();
+    TheISA::TLB *getITBPtr();
+    TheISA::TLB *getDTBPtr();
 
   public:
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 143d10783..042a6485a 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -419,11 +419,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
 
     /** Print Resource Schedule */
+    /** @NOTE: DEBUG ONLY */
     void printSched()
     {
-        using namespace ThePipeline;
-
-        ResSchedule tempSched;
+        ThePipeline::ResSchedule tempSched;
         std::cerr << "\tInst. Res. Schedule: ";
         while (!resSched.empty()) {
             std::cerr << '\t' << resSched.top()->stageNum << "-"
@@ -835,7 +834,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
     FloatReg readFloatRegOperand(const StaticInst *si, int idx,
                           int width = TheISA::SingleWidth);
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+    TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
                                   int width = TheISA::SingleWidth);
     MiscReg readMiscReg(int misc_reg);
     MiscReg readMiscRegNoEffect(int misc_reg);
@@ -878,7 +877,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
                      int width = TheISA::SingleWidth);
-    void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val,
+    void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
                          int width = TheISA::SingleWidth);
     void setMiscReg(int misc_reg, const MiscReg &val);
     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc
index 1c17b0d3f..150115138 100644
--- a/src/cpu/inorder/pipeline_traits.cc
+++ b/src/cpu/inorder/pipeline_traits.cc
@@ -101,7 +101,7 @@ bool createBackEndSchedule(DynInstPtr &inst)
     } else if ( inst->isMemRef() ) {
         if ( inst->isLoad() ) {
             E->needs(AGEN, AGENUnit::GenerateAddr);
-            E->needs(DTLB, TLBUnit::DataLookup);
+            E->needs(DTLB, TLBUnit::DataReadLookup);
             E->needs(DCache, CacheUnit::InitiateReadData);
         }
     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
@@ -122,7 +122,7 @@ bool createBackEndSchedule(DynInstPtr &inst)
     } else if ( inst->isStore() ) {
         M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
         M->needs(AGEN, AGENUnit::GenerateAddr);
-        M->needs(DTLB, TLBUnit::DataLookup);
+        M->needs(DTLB, TLBUnit::DataWriteLookup);
         M->needs(DCache, CacheUnit::InitiateWriteData);
     }
 
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 1b5d07450..6fe0bcf76 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -451,10 +451,12 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
 
 
     // Get resource request info
-    // @todo: SMT needs to figure out where to get thread # from.
-    unsigned tid = 0;
     unsigned stage_num = cache_req->getStageNum();
     DynInstPtr inst = cache_req->inst;
+    unsigned tid;
+
+
+    tid = cache_req->inst->readTid();
 
     if (!cache_req->isSquashed()) {
         if (inst->resSched.top()->cmd == CompleteFetch) {
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index fbc6bc195..dbf799661 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -118,7 +118,7 @@ TLBUnit::execute(int slot_idx)
         {
             tlb_req->fault =
                 _tlb->translateAtomic(tlb_req->memReq,
-                        cpu->thread[tid]->getTC(), false, true);
+                                      cpu->thread[tid]->getTC(), TheISA::TLB::Execute);
 
             if (tlb_req->fault != NoFault) {
                 DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
@@ -142,14 +142,19 @@ TLBUnit::execute(int slot_idx)
         }
         break;
 
-      case DataLookup:
+      case DataReadLookup:
+      case DataWriteLookup:
         {
             DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
                     tid, seq_num, tlb_req->memReq->getVaddr());
 
+
+            TheISA::TLB::Mode tlb_mode = (tlb_req->cmd == DataReadLookup) ?
+                TheISA::TLB::Read : TheISA::TLB::Write;
+
             tlb_req->fault =
                 _tlb->translateAtomic(tlb_req->memReq,
-                        cpu->thread[tid]->getTC());
+                                      cpu->thread[tid]->getTC(), tlb_mode);
 
             if (tlb_req->fault != NoFault) {
                 DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index b53f251fc..b0cdac2a2 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -47,7 +47,8 @@ class TLBUnit : public InstBuffer {
 
     enum TLBCommand {
         FetchLookup,
-        DataLookup
+        DataReadLookup,
+        DataWriteLookup
     };
 
   public:
@@ -103,7 +104,7 @@ class TLBUnitRequest : public ResourceRequest {
 
         if (_cmd == TLBUnit::FetchLookup) {
             aligned_addr = inst->getMemAddr();
-            req_size = sizeof(MachInst);
+            req_size = sizeof(TheISA::MachInst);
             flags = 0;
         } else {
             aligned_addr = inst->getMemAddr();;