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| author | Kevin Lim <ktlim@umich.edu> | 2006-08-02 12:07:44 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-08-02 12:07:44 -0400 |
| commit | 5ec58c4bdc2ffa8c650a784efc5a342a3ad36810 (patch) | |
| tree | 6b52712921ab3856b7dda3545241b9bbe4685431 | |
| parent | 5be592f870d1d59cffe9a5d1eebac66b225ff8ef (diff) | |
| download | gem5-5ec58c4bdc2ffa8c650a784efc5a342a3ad36810.tar.xz | |
Fix up some ISA related stuff.
arch/alpha/isa/decoder.isa:
Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.
--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae
| -rw-r--r-- | arch/alpha/isa/decoder.isa | 6 | ||||
| -rw-r--r-- | arch/alpha/isa/mem.isa | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index b3744a43d..71b9131aa 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -694,7 +694,7 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(); - }}, IsNonSpeculative); + }}, IsNonSpeculative, IsSerializeAfter); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); // Write uniq reg with value from ABI arg register (r16) @@ -768,10 +768,10 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative, IsQuiesce); 0x03: quiesceCycles({{ AlphaPseudo::quiesceCycles(xc->xcBase(), R16); - }}, IsNonSpeculative, IsQuiesce); + }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 0x04: quiesceTime({{ R0 = AlphaPseudo::quiesceTime(xc->xcBase()); - }}, IsNonSpeculative); + }}, IsNonSpeculative, IsUnverifiable); 0x10: ivlb({{ AlphaPseudo::ivlb(xc->xcBase()); }}, No_OpClass, IsNonSpeculative); diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa index 3c8b4f755..5d29c18bc 100644 --- a/arch/alpha/isa/mem.isa +++ b/arch/alpha/isa/mem.isa @@ -500,7 +500,7 @@ def template MiscInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - panic("Misc instruction does not support split access method!"); + warn("Misc instruction does not support split access method!"); return NoFault; } }}; @@ -511,7 +511,7 @@ def template MiscCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - panic("Misc instruction does not support split access method!"); + warn("Misc instruction does not support split access method!"); return NoFault; } |