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authorKevin Lim <ktlim@umich.edu>2004-05-28 14:42:59 -0400
committerKevin Lim <ktlim@umich.edu>2004-05-28 14:42:59 -0400
commit6964ecd1cf14f294a300e91bc5b65042d03952d4 (patch)
tree294cda7746b1fc636a00c2a377d41a95e67a62a3
parent67b5f6afc10a87a5942d24ad503f3e6b9358580c (diff)
downloadgem5-6964ecd1cf14f294a300e91bc5b65042d03952d4.tar.xz
Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc: Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future. arch/isa_parser.py: Added in FastCPU model. --HG-- extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
-rw-r--r--arch/alpha/ev5.cc6
-rwxr-xr-xarch/isa_parser.py3
2 files changed, 7 insertions, 2 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e88f6d0a3..ecf66f4f5 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -153,8 +153,10 @@ void
AlphaISA::zeroRegisters(XC *xc)
{
// Insure ISA semantics
- xc->setIntReg(ZeroReg, 0);
- xc->setFloatRegDouble(ZeroReg, 0.0);
+ // (no longer very clean due to the change in setIntReg() in the
+ // cpu model. Consider changing later.)
+ xc->xc->setIntReg(ZeroReg, 0);
+ xc->xc->setFloatRegDouble(ZeroReg, 0.0);
}
void
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 7f77241be..c808c2565 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -630,6 +630,9 @@ class CpuModel:
CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
'#include "cpu/simple_cpu/simple_cpu.hh"',
{ 'CPU_exec_context': 'SimpleCPU' })
+CpuModel('FastCPU', 'fast_cpu_exec.cc',
+ '#include "cpu/fast_cpu/fast_cpu.hh"',
+ { 'CPU_exec_context': 'FastCPU' })
CpuModel('FullCPU', 'full_cpu_exec.cc',
'#include "cpu/full_cpu/dyn_inst.hh"',
{ 'CPU_exec_context': 'DynInst' })