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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 18:34:16 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 18:34:16 -0700
commit6a923c1c79af1de9661c09afdd80ec805aff5e34 (patch)
tree417b060601e6b55373ac0fa0a6f3e5722779e992
parent09eed9ff621b6101289bde78f8cda6f360f6ef52 (diff)
downloadgem5-6a923c1c79af1de9661c09afdd80ec805aff5e34.tar.xz
X86: Implement a media square root microop.
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa45
1 files changed, 45 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 5cd7bd4f5..f61c8234f 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -529,4 +529,49 @@ let {{
}
FpDestReg.uqw = result;
'''
+
+ class Msqrt(MediaOp):
+ def __init__(self, dest, src, \
+ size = None, destSize = None, srcSize = None, ext = None):
+ super(Msqrt, self).__init__(dest, src,\
+ "InstRegIndex(0)", size, destSize, srcSize, ext)
+ code = '''
+ union floatInt
+ {
+ float f;
+ uint32_t i;
+ };
+ union doubleInt
+ {
+ double d;
+ uint64_t i;
+ };
+
+ assert(srcSize == destSize);
+ int size = srcSize;
+ int sizeBits = size * 8;
+ assert(srcSize == 4 || srcSize == 8);
+ int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size);
+ uint64_t result = FpDestReg.uqw;
+
+ for (int i = 0; i < items; i++) {
+ int hiIndex = (i + 1) * sizeBits - 1;
+ int loIndex = (i + 0) * sizeBits;
+ uint64_t argBits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
+
+ if (size == 4) {
+ floatInt fi;
+ fi.i = argBits;
+ fi.f = sqrt(fi.f);
+ argBits = fi.i;
+ } else {
+ doubleInt di;
+ di.i = argBits;
+ di.d = sqrt(di.d);
+ argBits = di.i;
+ }
+ result = insertBits(result, hiIndex, loIndex, argBits);
+ }
+ FpDestReg.uqw = result;
+ '''
}};