arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2 files changed, 58 insertions, 14 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 319cc9c09..647ecf787 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -659,16 +659,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         return readMiscRegNoEffect(MISCREG_DFAR_S);
       case MISCREG_HIFAR: // alias for secure IFAR
         return readMiscRegNoEffect(MISCREG_IFAR_S);
-      case MISCREG_HVBAR: // bottom bits reserved
-        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
-      case MISCREG_SCTLR:
-        return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
-      case MISCREG_SCTLR_EL1:
-        return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
-      case MISCREG_SCTLR_EL2:
-      case MISCREG_SCTLR_EL3:
-      case MISCREG_HSCTLR:
-        return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
 
       case MISCREG_ID_PFR0:
         // !ThumbEE | !Jazelle | Thumb | ARM
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 1eee78116..7c1a6930c 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2453,6 +2453,26 @@ ISA::initializeMiscRegMetadata()
     // is running in aarch64 (aarch32EL3 = false)
     bool aarch32EL3 = haveSecurity && !highestELIs64;
 
+    // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
+    // unsupported
+    bool SPAN = false;
+
+    // Implicit error synchronization event enable (Arm 8.2+), unsupported
+    bool IESB = false;
+
+    // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
+    // unsupported
+    bool LSMAOE = false;
+
+    // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
+    bool nTLSMD = false;
+
+    // Pointer authentication (Arm 8.3+), unsupported
+    bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
+    bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
+    bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
+    bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
+
     /**
      * Some registers alias with others, and therefore need to be translated.
      * When two mapping registers are given, they are the 32b lower and
@@ -2747,7 +2767,13 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_VMPIDR)
       .hyp().monNonSecure();
     InitReg(MISCREG_SCTLR)
-      .banked();
+      .banked()
+      // readMiscRegNoEffect() uses this metadata
+      // despite using children (below) as backing store
+      .res0(0x8d22c600)
+      .res1(0x00400800 | (SPAN   ? 0 : 0x800000)
+                       | (LSMAOE ? 0 :     0x10)
+                       | (nTLSMD ? 0 :      0x8));
     InitReg(MISCREG_SCTLR_NS)
       .bankedChild()
       .privSecure(!aarch32EL3)
@@ -2775,7 +2801,13 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_NSACR)
       .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
     InitReg(MISCREG_HSCTLR)
-      .hyp().monNonSecure();
+      .hyp().monNonSecure()
+      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
+                       | (IESB   ? 0 :   0x200000)
+                       | (EnDA   ? 0 :  0x8000000)
+                       | (EnIB   ? 0 : 0x40000000)
+                       | (EnIA   ? 0 : 0x80000000))
+      .res1(0x30c50830);
     InitReg(MISCREG_HACTLR)
       .hyp().monNonSecure();
     InitReg(MISCREG_HCR)
@@ -3175,7 +3207,8 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_ISR)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_HVBAR)
-      .hyp().monNonSecure();
+      .hyp().monNonSecure()
+      .res0(0x1f);
     InitReg(MISCREG_FCSEIDR)
       .unimplemented()
       .warnNotFail()
@@ -3537,6 +3570,14 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_VMPIDR);
     InitReg(MISCREG_SCTLR_EL1)
       .allPrivileges().exceptUserMode()
+      .res0( 0x20440 | (EnDB   ? 0 :     0x2000)
+                     | (IESB   ? 0 :   0x200000)
+                     | (EnDA   ? 0 :  0x8000000)
+                     | (EnIB   ? 0 : 0x40000000)
+                     | (EnIA   ? 0 : 0x80000000))
+      .res1(0x500800 | (SPAN   ? 0 :   0x800000)
+                     | (nTLSMD ? 0 :  0x8000000)
+                     | (LSMAOE ? 0 : 0x10000000))
       .mapsTo(MISCREG_SCTLR_NS);
     InitReg(MISCREG_ACTLR_EL1)
       .allPrivileges().exceptUserMode()
@@ -3546,6 +3587,12 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_CPACR);
     InitReg(MISCREG_SCTLR_EL2)
       .hyp().mon()
+      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
+                       | (IESB   ? 0 :   0x200000)
+                       | (EnDA   ? 0 :  0x8000000)
+                       | (EnIB   ? 0 : 0x40000000)
+                       | (EnIA   ? 0 : 0x80000000))
+      .res1(0x30c50830)
       .mapsTo(MISCREG_HSCTLR);
     InitReg(MISCREG_ACTLR_EL2)
       .hyp().mon()
@@ -3566,7 +3613,13 @@ ISA::initializeMiscRegMetadata()
       .hyp().mon()
       .mapsTo(MISCREG_HACR);
     InitReg(MISCREG_SCTLR_EL3)
-      .mon();
+      .mon()
+      .res0(0x0512c7c0 | (EnDB   ? 0 :     0x2000)
+                       | (IESB   ? 0 :   0x200000)
+                       | (EnDA   ? 0 :  0x8000000)
+                       | (EnIB   ? 0 : 0x40000000)
+                       | (EnIA   ? 0 : 0x80000000))
+      .res1(0x30c50830);
     InitReg(MISCREG_ACTLR_EL3)
       .mon();
     InitReg(MISCREG_SCR_EL3)
@@ -3892,6 +3945,7 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_VBAR_EL2)
       .hyp().mon()
+      .res0(0x7ff)
       .mapsTo(MISCREG_HVBAR);
     InitReg(MISCREG_RVBAR_EL2)
       .mon().hyp().writes(0);