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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-31 13:02:58 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-31 13:02:58 -0700 |
commit | 941675690ca77475f8f311e99f3660d0394e583c (patch) | |
tree | daa6eb2423311e30099e2bbbb3e38c52e6903ceb | |
parent | eddf6f163741d116235caeba9cec3e604907dfcf (diff) | |
download | gem5-941675690ca77475f8f311e99f3660d0394e583c.tar.xz |
X86: Get x86 to compile again after the simobject constructor change.
--HG--
extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
-rw-r--r-- | src/arch/x86/tlb.cc | 4 | ||||
-rw-r--r-- | src/arch/x86/tlb.hh | 5 | ||||
-rw-r--r-- | src/cpu/nativetrace.cc | 4 | ||||
-rw-r--r-- | src/cpu/nativetrace.hh | 2 |
4 files changed, 7 insertions, 8 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index e29ec58c2..d2db8cb0b 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -79,11 +79,11 @@ namespace X86ISA { X86ISA::ITB * X86ITBParams::create() { - return new X86ISA::ITB(name); + return new X86ISA::ITB(this); } X86ISA::DTB * X86DTBParams::create() { - return new X86ISA::DTB(name); + return new X86ISA::DTB(this); } diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 6622f5dc2..354443794 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -59,7 +59,6 @@ #define __ARCH_X86_TLB_HH__ #include <iostream> -#include <string> #include "sim/host.hh" #include "sim/tlb.hh" @@ -81,14 +80,14 @@ namespace X86ISA class ITB : public GenericTLB { public: - ITB(const std::string &name) : GenericTLB(name) + ITB(const Params *p) : GenericTLB(p) {} }; class DTB : public GenericTLB { public: - DTB(const std::string &name) : GenericTLB(name) + DTB(const Params *p) : GenericTLB(p) {} }; }; diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index fe524e245..0db61af2c 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -50,7 +50,7 @@ using namespace TheISA; namespace Trace { -NativeTrace::NativeTrace(const std::string & _name) : InstTracer(_name) +NativeTrace::NativeTrace(const Params *p) : InstTracer(p) { int port = 8000; while(!native_listener.listen(port, true)) @@ -187,5 +187,5 @@ Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall) Trace::NativeTrace * NativeTraceParams::create() { - return new Trace::NativeTrace(name); + return new Trace::NativeTrace(this); }; diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 126077581..6fd624211 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -171,7 +171,7 @@ class NativeTrace : public InstTracer bool checkR11Reg(const char * regName, uint64_t &, uint64_t &); - NativeTrace(const std::string & name); + NativeTrace(const Params *p); NativeTraceRecord * getInstRecord(Tick when, ThreadContext *tc, |