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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-01-03 12:03:06 +0000 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-01-03 12:03:06 +0000 |
commit | abe7ef95cb89c68c6385162cb801bab8b27a585b (patch) | |
tree | 3f3b52aa2328f2511e6d4cbe72cd854c21997f9d | |
parent | f835378bea588c8fe614b18f41c5792ba7044263 (diff) | |
download | gem5-abe7ef95cb89c68c6385162cb801bab8b27a585b.tar.xz |
sim: Remove redundant export_method_cxx_predecls
The headers declared in export_method_cxx_predecls are redundant since a
SimObject's main header is automatically included.
Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joe Gross <joseph.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
-rw-r--r-- | src/arch/arm/ArmSystem.py | 4 | ||||
-rw-r--r-- | src/cpu/kvm/BaseKvmCPU.py | 4 | ||||
-rw-r--r-- | src/python/m5/SimObject.py | 12 | ||||
-rw-r--r-- | src/sim/System.py | 4 |
4 files changed, 1 insertions, 23 deletions
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index ac04a56e4..9100db09a 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -99,10 +99,6 @@ class LinuxArmSystem(GenericArmSystem): cxx_header = "arch/arm/linux/system.hh" @classmethod - def export_method_cxx_predecls(cls, code): - code('#include "arch/arm/linux/system.hh"') - - @classmethod def export_methods(cls, code): code('''void dumpDmesg();''') diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py index 34ab752de..4c64f24ed 100644 --- a/src/cpu/kvm/BaseKvmCPU.py +++ b/src/cpu/kvm/BaseKvmCPU.py @@ -47,10 +47,6 @@ class BaseKvmCPU(BaseCPU): abstract = True @classmethod - def export_method_cxx_predecls(cls, code): - code('#include "cpu/kvm/base.hh"') - - @classmethod def export_methods(cls, code): code(''' void dump() const; diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index bb834fc0b..11f356204 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -498,8 +498,7 @@ class MetaSimObject(type): # suppresses inheritance by substituting in the base (null) # versions of these methods unless a different version is # explicitly supplied. - for method_name in ('export_methods', 'export_method_cxx_predecls', - 'export_method_swig_predecls'): + for method_name in ('export_methods', 'export_method_swig_predecls'): if method_name not in cls.__dict__: base_method = getattr(MetaSimObject, method_name) m = MethodType(base_method, cls, MetaSimObject) @@ -665,14 +664,6 @@ class MetaSimObject(type): pass # Generate the code needed as a prerequisite for the C++ methods - # exported via export_methods() to be compiled in the _wrap.cc - # file. Typically generates one or more #include statements. If - # any methods are exported, typically at least the C++ header - # declaring the relevant SimObject class must be included. - def export_method_cxx_predecls(cls, code): - pass - - # Generate the code needed as a prerequisite for the C++ methods # exported via export_methods() to be processed by SWIG. # Typically generates one or more %include or %import statements. # If any methods are exported, typically at least the C++ header @@ -703,7 +694,6 @@ class MetaSimObject(type): for param in params: param.cxx_predecls(code) code('#include "${{cls.cxx_header}}"') - cls.export_method_cxx_predecls(code) code('''\ /** * This is a workaround for bug in swig. Prior to gcc 4.6.1 the STL diff --git a/src/sim/System.py b/src/sim/System.py index 8ebf7a024..f97096fcc 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -44,10 +44,6 @@ class System(MemObject): system_port = MasterPort("System port") @classmethod - def export_method_cxx_predecls(cls, code): - code('#include "sim/system.hh"') - - @classmethod def export_methods(cls, code): code(''' Enums::MemoryMode getMemoryMode() const; |