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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-05-09 18:58:47 -0400
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-05-09 18:58:47 -0400
commitaf39ab297f7c666e77d29e836a4ff4c2a6d672a9 (patch)
tree519bce2e113e54ce6b2165d92fd1436e45200dd8
parentfe27f937aa833a2d25e0462fd0cac301a45df8cb (diff)
downloadgem5-af39ab297f7c666e77d29e836a4ff4c2a6d672a9.tar.xz
arm: add preliminary ISA splits for ARM arch
-rw-r--r--src/arch/arm/isa/insts/insts.isa10
-rw-r--r--src/arch/arm/isa/insts/neon.isa22
-rw-r--r--src/arch/arm/isa/insts/neon64.isa3
3 files changed, 26 insertions, 9 deletions
diff --git a/src/arch/arm/isa/insts/insts.isa b/src/arch/arm/isa/insts/insts.isa
index 2f53d895c..89c80cbaa 100644
--- a/src/arch/arm/isa/insts/insts.isa
+++ b/src/arch/arm/isa/insts/insts.isa
@@ -53,6 +53,9 @@
##include "misc.isa"
##include "misc64.isa"
+split exec;
+split decoder;
+
//Stores of a single item, AArch64
##include "str64.isa"
@@ -65,6 +68,8 @@
//Load/store multiple
##include "macromem.isa"
+split exec;
+
//Data processing instructions
##include "data.isa"
@@ -85,12 +90,15 @@
##include "fp.isa"
##include "fp64.isa"
+split exec;
+
//Neon
##include "neon.isa"
//AArch64 Neon
##include "neon64.isa"
+split decoder;
##include "neon64_mem.isa"
-//m5 Psuedo-ops
+//m5 Pseudo-ops
##include "m5ops.isa"
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index ca5c3038c..166176602 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1058,7 +1058,11 @@ output header {{
}
}};
-output exec {{
+let {{
+ header_output = ""
+ exec_output = ""
+
+ vcompares = '''
static float
vcgtFunc(float op1, float op2)
{
@@ -1082,7 +1086,8 @@ output exec {{
return 2.0;
return (op1 == op2) ? 0.0 : 1.0;
}
-
+'''
+ vcomparesL = '''
static float
vcleFunc(float op1, float op2)
{
@@ -1098,7 +1103,8 @@ output exec {{
return 2.0;
return (op1 < op2) ? 0.0 : 1.0;
}
-
+'''
+ vacomparesG = '''
static float
vacgtFunc(float op1, float op2)
{
@@ -1114,12 +1120,9 @@ output exec {{
return 2.0;
return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0;
}
-}};
-
-let {{
+'''
- header_output = ""
- exec_output = ""
+ exec_output += vcompares + vacomparesG
smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t")
unsignedTypes = smallUnsignedTypes + ("uint64_t",)
@@ -3414,6 +3417,9 @@ let {{
twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code)
twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code)
+ split('exec')
+ exec_output += vcompares + vcomparesL
+
vpaddlCode = '''
destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
'''
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index e065761f4..bbe57bdfa 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1959,6 +1959,9 @@ let {{
2, minAcrossCode)
twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4,
minAcrossCode)
+
+ split('exec')
+
# SMLAL, SMLAL2 (by element)
mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;"
threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp",