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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:33 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:33 -0400
commitb43eeaf2e22ef081e2bc73bff7a069bbf5eb5fda (patch)
treef824a20153cb0e4c55916e22989b3e0c81788952
parente2f9266dbfc7ef54f94028eeffa4e40c76ffc17a (diff)
downloadgem5-b43eeaf2e22ef081e2bc73bff7a069bbf5eb5fda.tar.xz
cpus/isa: add a != operator for pcstate
-rw-r--r--src/arch/arm/types.hh6
-rw-r--r--src/arch/generic/types.hh24
2 files changed, 30 insertions, 0 deletions
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 9e7c0ff7f..15f9f4d0a 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -433,6 +433,12 @@ namespace ArmISA
_itstate == opc._itstate && _nextItstate == opc._nextItstate;
}
+ bool
+ operator != (const PCState &opc) const
+ {
+ return !(*this == opc);
+ }
+
void
serialize(std::ostream &os)
{
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 931349ac4..050fbd56e 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -98,6 +98,12 @@ class PCStateBase
return _pc == opc._pc && _npc == opc._npc;
}
+ bool
+ operator != (const PCStateBase &opc) const
+ {
+ return !(*this == opc);
+ }
+
void
serialize(std::ostream &os)
{
@@ -235,6 +241,12 @@ class UPCState : public SimplePCState<MachInst>
_upc == opc._upc && _nupc == opc._nupc;
}
+ bool
+ operator != (const UPCState<MachInst> &opc) const
+ {
+ return !(*this == opc);
+ }
+
void
serialize(std::ostream &os)
{
@@ -310,6 +322,12 @@ class DelaySlotPCState : public SimplePCState<MachInst>
_nnpc == opc._nnpc;
}
+ bool
+ operator != (const DelaySlotPCState<MachInst> &opc) const
+ {
+ return !(*this == opc);
+ }
+
void
serialize(std::ostream &os)
{
@@ -401,6 +419,12 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
_upc == opc._upc && _nupc == opc._nupc;
}
+ bool
+ operator != (const DelaySlotUPCState<MachInst> &opc) const
+ {
+ return !(*this == opc);
+ }
+
void
serialize(std::ostream &os)
{