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authorGabe Black <gblack@eecs.umich.edu>2009-12-31 15:30:50 -0500
committerGabe Black <gblack@eecs.umich.edu>2009-12-31 15:30:50 -0500
commitcc07dcf02654267227d9de6ae0898d39d5ea5438 (patch)
tree1bec0ecf7c702aab29993e59ca0a496716b225f4
parent1261f1d8db6134d47ccf27bb9b2bbb275deb6b84 (diff)
downloadgem5-cc07dcf02654267227d9de6ae0898d39d5ea5438.tar.xz
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
-rw-r--r--src/arch/mips/isa.cc17
-rw-r--r--src/arch/mips/isa.hh9
2 files changed, 8 insertions, 18 deletions
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 3c8c9a986..1cad7e4be 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -91,12 +91,6 @@ ISA::ISA()
init();
}
-ISA::ISA(BaseCPU *_cpu)
-{
- cpu = _cpu;
- init();
-}
-
void
ISA::init()
{
@@ -173,11 +167,10 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
ISA::reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+ unsigned num_vpes, BaseCPU *cpu)
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
num_threads, num_vpes);
- cpu = _cpu;
MipsISA::CoreSpecific &cp = cpu->coreParams;
@@ -499,7 +492,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
miscRegFile[misc_reg][reg_sel] = cp0_val;
- scheduleCP0Update(1);
+ scheduleCP0Update(tc->getCpuPtr(), 1);
}
/**
@@ -528,7 +521,7 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
}
void
-ISA::scheduleCP0Update(int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
{
if (!cp0Updated) {
cp0Updated = true;
@@ -540,7 +533,7 @@ ISA::scheduleCP0Update(int delay)
}
void
-ISA::updateCPU()
+ISA::updateCPU(BaseCPU *cpu)
{
///////////////////////////////////////////////////////////////////
//
@@ -578,7 +571,7 @@ ISA::CP0Event::process()
switch (cp0EventType)
{
case UpdateCP0:
- cp0->updateCPU();
+ cp0->updateCPU(cpu);
break;
}
}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 165adff83..3f7afcdd0 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -64,18 +64,15 @@ namespace MipsISA
std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
std::vector<BankType> bankType;
- BaseCPU *cpu;
-
public:
ISA();
- ISA(BaseCPU *_cpu);
void init();
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu);
+ unsigned num_vpes, BaseCPU *cpu);
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
@@ -147,11 +144,11 @@ namespace MipsISA
};
// Schedule a CP0 Update Event
- void scheduleCP0Update(int delay = 0);
+ void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
// If any changes have been made, then check the state for changes
// and if necessary alert the CPU
- void updateCPU();
+ void updateCPU(BaseCPU *cpu);
// Keep a List of CPU Events that need to be deallocated
std::queue<CP0Event*> cp0EventRemoveList;