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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-10 15:29:32 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-10 15:29:32 -0500 |
| commit | d30e3b30afde1916537f8ebb76cbb9b1d2df6f7d (patch) | |
| tree | 1b610f8a86b127f5204887b7598bb05f76abfbf0 | |
| parent | 13a8752c11ae8e2c9fbf97c405e27b4ec2f8fd3b (diff) | |
| download | gem5-d30e3b30afde1916537f8ebb76cbb9b1d2df6f7d.tar.xz | |
Added StrandStsReg operand.
--HG--
extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index caee20b0c..2d200f568 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -123,6 +123,7 @@ def operands {{ 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), + 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), # Mem gets a large number so it's always last |