X86: Take advantage of new PCState syntax.

4 files changed, 14 insertions, 25 deletions

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index def9b7f9d..1dc32122e 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -198,8 +198,8 @@
                         }}, IsNonSpeculative);
 #endif
                         0x54: m5panic({{
-                            panic("M5 panic instruction called at pc=%#x.\n",
-                                xc->pcState().pc());
+                            panic("M5 panic instruction called at pc = %#x.\n",
+                                  RIP);
                         }}, IsNonSpeculative);
                         0x55: m5reserved1({{
                             warn("M5 reserved opcode 1 ignored.\n");
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 86ebac174..975bdce8a 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -944,12 +944,8 @@ let {{
         code = 'DoubleBits = psrc1 ^ op2;'
 
     class Wrip(WrRegOp, CondRegOp):
-        code = '''
-        X86ISA::PCState pc = PCS;
-        pc.npc(psrc1 + sop2 + CSBase);
-        PCS = pc;
-        '''
-        else_code = "PCS = PCS;"
+        code = 'NRIP = psrc1 + sop2 + CSBase;'
+        else_code = "NRIP = NRIP;"
 
     class Wruflags(WrRegOp):
         code = 'ccFlagBits = psrc1 ^ op2'
@@ -965,10 +961,7 @@ let {{
         '''
 
     class Rdip(RdRegOp):
-        code = '''
-        X86ISA::PCState pc = PCS;
-        DestReg = pc.npc() - CSBase;
-        '''
+        code = 'DestReg = NRIP - CSBase;'
 
     class Ruflags(RdRegOp):
         code = 'DestReg = ccFlagBits'
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index a3e22b0aa..1b125ec9c 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -169,23 +169,15 @@ let {{
             return super(Eret, self).getAllocator(microFlags)
 
     iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
-            {"code": '''
-             X86ISA::PCState pc = PCS;
-             pc.nupc(target);
-             PCS = pc;
-             ''',
-             "else_code": "PCS = PCS",
+            {"code": "nuIP = target;",
+             "else_code": "nuIP = nuIP;",
              "cond_test": "checkCondition(ccFlagBits, cc)"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
     decoder_output += SeqOpConstructor.subst(iop)
     iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
-            {"code": '''
-             X86ISA::PCState pc = PCS;
-             pc.nupc(target);
-             PCS = pc;
-             ''',
-             "else_code": "PCS = PCS",
+            {"code": "nuIP = target;",
+             "else_code": "nuIP = nuIP;",
              "cond_test": "true"})
     exec_output += SeqOpExecute.subst(iop)
     header_output += SeqOpDeclare.subst(iop)
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 25b73a8f2..51b9b73a6 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -97,7 +97,11 @@ def operands {{
         'FpSrcReg2':     floatReg('src2', 21),
         'FpDestReg':     floatReg('dest', 22),
         'FpData':        floatReg('data', 23),
-        'PCS':           ('PCState', 'udw', None,
+        'RIP':           ('PCState', 'uqw', 'pc',
+                          (None, None, 'IsControl'), 50),
+        'NRIP':          ('PCState', 'uqw', 'npc',
+                          (None, None, 'IsControl'), 50),
+        'nuIP':          ('PCState', 'uqw', 'nupc',
                           (None, None, 'IsControl'), 50),
         # This holds the condition code portion of the flag register. The
         # nccFlagBits version holds the rest.