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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:15:06 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:15:06 -0700 |
| commit | e174239bd8aa389fb39d8600b22dc1095a0dccf2 (patch) | |
| tree | 1bc0714eeafdcb11236f359c2d2b056314cd805b | |
| parent | 25e223c30fb97d98aa55ee21922883efa25a1ab5 (diff) | |
| download | gem5-e174239bd8aa389fb39d8600b22dc1095a0dccf2.tar.xz | |
X86: Mask the PIC at startup to avoid a glitch which causes an NMI.
| -rw-r--r-- | src/dev/x86/i8259.hh | 14 | ||||
| -rw-r--r-- | src/dev/x86/pc.cc | 7 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh index dfb56646a..a9c5baa8c 100644 --- a/src/dev/x86/i8259.hh +++ b/src/dev/x86/i8259.hh @@ -39,8 +39,6 @@ namespace X86ISA { -class I82094AA; - class I8259 : public BasicPioDevice, public IntDev { protected: @@ -94,6 +92,18 @@ class I8259 : public BasicPioDevice, public IntDev Tick read(PacketPtr pkt); Tick write(PacketPtr pkt); + void + maskAll() + { + IMR = 0xFF; + } + + void + unmaskAll() + { + IMR = 0x00; + } + void signalInterrupt(int line); void raiseInterruptPin(int number); void lowerInterruptPin(int number); diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc index d1ab4af7f..7dc1d8711 100644 --- a/src/dev/x86/pc.cc +++ b/src/dev/x86/pc.cc @@ -107,6 +107,13 @@ Pc::init() entry.vector = 0x30; ioApic.writeReg(0x30, entry.bottomDW); ioApic.writeReg(0x31, entry.topDW); + + /* + * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared + * these out and masked them before passing control to the OS. + */ + southBridge->pic1->maskAll(); + southBridge->pic2->maskAll(); } Tick |