summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorNathan Binkert <nate@binkert.org>2008-09-22 08:21:47 -0700
committerNathan Binkert <nate@binkert.org>2008-09-22 08:21:47 -0700
commitf3f4b17c5b6f594524d54176c15c23d6338c60a4 (patch)
treefde620fa39c405f999cfabc8d0984f726fab823c
parentd1bec9b0cc3761999f0c0e4dacc07ba6d91ff1a0 (diff)
downloadgem5-f3f4b17c5b6f594524d54176c15c23d6338c60a4.tar.xz
style
-rw-r--r--src/arch/alpha/utility.hh50
1 files changed, 30 insertions, 20 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index ddbf88e95..43d4908b4 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -41,7 +41,6 @@
namespace AlphaISA
{
-
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
inline bool
@@ -50,58 +49,71 @@ namespace AlphaISA
return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
}
- inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+ inline bool
+ isCallerSaveIntegerRegister(unsigned int reg)
+ {
panic("register classification not implemented");
return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
}
- inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+ inline bool
+ isCalleeSaveIntegerRegister(unsigned int reg)
+ {
panic("register classification not implemented");
return (reg >= 9 && reg <= 15);
}
- inline bool isCallerSaveFloatRegister(unsigned int reg) {
+ inline bool
+ isCallerSaveFloatRegister(unsigned int reg)
+ {
panic("register classification not implemented");
return false;
}
- inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+ inline bool
+ isCalleeSaveFloatRegister(unsigned int reg)
+ {
panic("register classification not implemented");
return false;
}
- inline Addr alignAddress(const Addr &addr,
- unsigned int nbytes) {
+ inline Addr
+ alignAddress(const Addr &addr, unsigned int nbytes)
+ {
return (addr & ~(nbytes - 1));
}
// Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr) {
+ inline Addr
+ realPCToFetchPC(const Addr &addr)
+ {
return addr;
}
- inline Addr fetchPCToRealPC(const Addr &addr) {
+ inline Addr
+ fetchPCToRealPC(const Addr &addr)
+ {
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
- inline size_t fetchInstSize() {
+ inline size_t
+ fetchInstSize()
+ {
return sizeof(MachInst);
}
- inline MachInst makeRegisterCopy(int dest, int src) {
+ inline MachInst
+ makeRegisterCopy(int dest, int src)
+ {
panic("makeRegisterCopy not implemented");
return 0;
}
// Machine operations
-
- void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
- int regnum);
-
- void restoreMachineReg(RegFile &regs, const AnyReg &reg,
- int regnum);
+ void saveMachineReg(AnyReg &savereg, const RegFile &reg_file, int regnum);
+ void restoreMachineReg(RegFile &regs, const AnyReg &reg, int regnum);
/**
* Function to insure ISA semantics about 0 registers.
@@ -112,9 +124,7 @@ namespace AlphaISA
// Alpha IPR register accessors
inline bool PcPAL(Addr addr) { return addr & 0x3; }
- inline void startupCPU(ThreadContext *tc, int cpuId) {
- tc->activate(0);
- }
+ inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
////////////////////////////////////////////////////////////////////////
//