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authorNathan Binkert <binkertn@umich.edu>2004-05-21 13:58:39 -0400
committerNathan Binkert <binkertn@umich.edu>2004-05-21 13:58:39 -0400
commitf622d74f81f6d0c451bc8437d19a38057bc0d164 (patch)
treedb725b6d157ec55ee18c584dc1b5e81b10a5043c
parentfee1e1ec0a9c1122f3c42fdef9482c64389949fc (diff)
downloadgem5-f622d74f81f6d0c451bc8437d19a38057bc0d164.tar.xz
add a few statistics events
arch/alpha/ev5.cc: Add an event for faults cpu/simple_cpu/simple_cpu.cc: add events for uncached reads/writes --HG-- extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
-rw-r--r--arch/alpha/ev5.cc17
-rw-r--r--cpu/simple_cpu/simple_cpu.cc7
2 files changed, 16 insertions, 8 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index f037a34ac..96d54c54c 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -1,15 +1,14 @@
/* $Id$ */
-#include "targetarch/alpha_memory.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
#include "cpu/exec_context.hh"
+#include "sim/debug.hh"
#include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h" // for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
#ifdef FULL_SYSTEM
@@ -102,6 +101,8 @@ AlphaISA::initIPRs(RegFile *regs)
void
ExecContext::ev5_trap(Fault fault)
{
+ Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+
assert(!misspeculating());
kernelStats.fault(fault);
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 765507345..1ade235ed 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -42,6 +42,7 @@
#include "base/pollevent.hh"
#include "base/range.hh"
#include "base/trace.hh"
+#include "base/stats/events.hh"
#include "cpu/base_cpu.hh"
#include "cpu/exec_context.hh"
#include "cpu/exetrace.hh"
@@ -402,6 +403,9 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
}
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ Stats::recordEvent("Uncached Read");
+
return fault;
}
@@ -487,6 +491,9 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (res && (fault == No_Fault))
*res = memReq->result;
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ Stats::recordEvent("Uncached Write");
+
return fault;
}