x86: Make unsuccessful CPUID instructions zero the result.

The previous implementation left the registers unmodified which is
technically correct since there is no defined behavior in that case or
a fault to raise. That would make what happened when the following code
consumed the result unpredictable because it would depend on what junk
values were left in the registers. This was originally not a problem
since the space of supported functions were tightly packed, but someone
added a new function with a gap without adjusting this behavior.

This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails.
That should be more predictable and cause less flakey failures.

Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 7 insertions, 4 deletions

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 339e5a0ab..7a4f9e198 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -756,10 +756,13 @@
                     Rcx = result.rcx;
                     Rdx = result.rdx;
                 } else {
-                    Rax = Rax;
-                    Rbx = Rbx;
-                    Rcx = Rcx;
-                    Rdx = Rdx;
+                    // It isn't defined what to do in this case. We used to
+                    // leave R[abcd]x unmodified, but setting them all to 0
+                    // seems a little safer and more predictable.
+                    Rax = 0;
+                    Rbx = 0;
+                    Rcx = 0;
+                    Rdx = 0;
                 }
                 }});
             0x3: Inst::BT(Ev,Gv);