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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-09 16:57:58 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | 05e098ff4a026aa84092b6736fe5dbadf47e3f63 (patch) | |
| tree | f0f8f0839671b6350f68514bd29891c5b3252109 | |
| parent | a71fb9ae62564b08889861496abae420a1530a6e (diff) | |
| download | gem5-05e098ff4a026aa84092b6736fe5dbadf47e3f63.tar.xz | |
arch-arm: Avoid creating an empty byteEnable vector
This behaviour will be forbidden in following patches.
Instead, create an all true vector.
JIRA: https://gem5.atlassian.net/browse/GEM5-196
Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/isa/insts/sve_mem.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa index dd3d5827c..b36c1b271 100644 --- a/src/arch/arm/isa/insts/sve_mem.isa +++ b/src/arch/arm/isa/insts/sve_mem.isa @@ -774,7 +774,7 @@ let {{ EA = XBase + ((int64_t) imm * %(memacc_size)s)''' % { 'memacc_size': 'eCount / 8' if isPred else 'eCount'} loadRdEnableCode = ''' - auto rdEn = std::vector<bool>(); + auto rdEn = std::vector<bool>(memAccessSize, true); ''' if isPred: loadMemAccCode = ''' |