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authorKevin Lim <ktlim@umich.edu>2006-03-03 15:41:57 -0500
committerKevin Lim <ktlim@umich.edu>2006-03-03 15:41:57 -0500
commit14b6cd39aadcac72e8fce47e24445037bae70309 (patch)
treeaaa17e7cb94d2b0764d9808bf7f4892e6ebe919f
parente7825aab59e03b9691d361338fba222f56446f77 (diff)
downloadgem5-14b6cd39aadcac72e8fce47e24445037bae70309.tar.xz
Remove intr_post function. No longer being used.
--HG-- extra : convert_revision : 1dc1d691244fd2edbd21d5cbf0764622d8f95fbb
-rw-r--r--arch/alpha/ev5.cc27
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 9193e40f0..2cbfe7fd6 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -163,33 +163,6 @@ ExecContext::ev5_temp_trap(Fault fault)
}
-void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
-{
- bool use_pc = (fault == NoFault);
-
- if (fault->isA<ArithmeticFault>())
- panic("arithmetic faults NYI...");
-
- // compute exception restart address
- if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
- // traps... skip faulting instruction
- regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
- } else {
- // fault, post fault at excepting instruction
- regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
- }
-
- // jump to expection address (PAL PC bit set here as well...)
- if (!use_pc)
- regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
- (dynamic_cast<AlphaFault *>(fault.get()))->vect();
- else
- regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-
- // that's it! (orders of magnitude less painful than x86)
-}
-
Fault
ExecContext::hwrei()
{