misc: added missing override specifier

Added missing specifier for various virtual functions.

Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458
Reviewed-on: https://gem5-review.googlesource.com/c/16103
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 files changed, 213 insertions, 193 deletions

diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 912bf45ca..406fe4ffa 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -131,7 +131,7 @@ class Interrupts : public SimObject
     void setIE(const uint64_t& val) { ie = val; }
 
     void
-    serialize(CheckpointOut &cp)
+    serialize(CheckpointOut &cp) const
     {
         SERIALIZE_SCALAR(ip.to_ulong());
         SERIALIZE_SCALAR(ie.to_ulong());
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 0983d03ef..9c8469cc0 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -90,54 +90,56 @@ class CheckerThreadContext : public ThreadContext
 
   public:
 
-    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
+    BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
 
-    uint32_t socketId() const { return actualTC->socketId(); }
+    uint32_t socketId() const override { return actualTC->socketId(); }
 
-    int cpuId() const { return actualTC->cpuId(); }
+    int cpuId() const override { return actualTC->cpuId(); }
 
-    ContextID contextId() const { return actualTC->contextId(); }
+    ContextID contextId() const override { return actualTC->contextId(); }
 
-    void setContextId(ContextID id)
+    void setContextId(ContextID id)override
     {
        actualTC->setContextId(id);
        checkerTC->setContextId(id);
     }
 
     /** Returns this thread's ID number. */
-    int threadId() const { return actualTC->threadId(); }
-    void setThreadId(int id)
+    int threadId() const override { return actualTC->threadId(); }
+    void setThreadId(int id) override
     {
         checkerTC->setThreadId(id);
         actualTC->setThreadId(id);
     }
 
-    BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
+    BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
 
-    BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
 
-    CheckerCPU *getCheckerCpuPtr()
+    CheckerCPU *getCheckerCpuPtr()override
     {
         return checkerCPU;
     }
 
-    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+    TheISA::Decoder *getDecoderPtr() override {
+        return actualTC->getDecoderPtr();
+    }
 
-    System *getSystemPtr() { return actualTC->getSystemPtr(); }
+    System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 
-    TheISA::Kernel::Statistics *getKernelStats()
+    TheISA::Kernel::Statistics *getKernelStats()override
     { return actualTC->getKernelStats(); }
 
-    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
+    Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 
-    void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
+    void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
 
-    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
+    PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 
-    FSTranslatingPortProxy &getVirtProxy()
+    FSTranslatingPortProxy &getVirtProxy() override
     { return actualTC->getVirtProxy(); }
 
-    void initMemProxies(ThreadContext *tc)
+    void initMemProxies(ThreadContext *tc) override
     { actualTC->initMemProxies(tc); }
 
     void connectMemPorts(ThreadContext *tc)
@@ -145,59 +147,63 @@ class CheckerThreadContext : public ThreadContext
         actualTC->connectMemPorts(tc);
     }
 
-    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
+    SETranslatingPortProxy &getMemProxy() override {
+        return actualTC->getMemProxy();
+    }
 
     /** Executes a syscall in SE mode. */
-    void syscall(int64_t callnum, Fault *fault)
+    void syscall(int64_t callnum, Fault *fault)override
     { return actualTC->syscall(callnum, fault); }
 
-    Status status() const { return actualTC->status(); }
+    Status status() const override { return actualTC->status(); }
 
-    void setStatus(Status new_status)
+    void setStatus(Status new_status) override
     {
         actualTC->setStatus(new_status);
         checkerTC->setStatus(new_status);
     }
 
     /// Set the status to Active.
-    void activate() { actualTC->activate(); }
+    void activate() override { actualTC->activate(); }
 
     /// Set the status to Suspended.
-    void suspend() { actualTC->suspend(); }
+    void suspend() override{ actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt() { actualTC->halt(); }
+    void halt() override{ actualTC->halt(); }
 
-    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
+    void dumpFuncProfile()  override{ actualTC->dumpFuncProfile(); }
 
-    void takeOverFrom(ThreadContext *oldContext)
+    void takeOverFrom(ThreadContext *oldContext) override
     {
         actualTC->takeOverFrom(oldContext);
         checkerTC->copyState(oldContext);
     }
 
-    void regStats(const std::string &name)
+    void regStats(const std::string &name) override
     {
         actualTC->regStats(name);
         checkerTC->regStats(name);
     }
 
-    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
+    EndQuiesceEvent *getQuiesceEvent() override {
+        return actualTC->getQuiesceEvent();
+    }
 
-    Tick readLastActivate() { return actualTC->readLastActivate(); }
-    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
+    Tick readLastActivate()  override{ return actualTC->readLastActivate(); }
+    Tick readLastSuspend()  override{ return actualTC->readLastSuspend(); }
 
-    void profileClear() { return actualTC->profileClear(); }
-    void profileSample() { return actualTC->profileSample(); }
+    void profileClear()  override{ return actualTC->profileClear(); }
+    void profileSample()  override{ return actualTC->profileSample(); }
 
     // @todo: Do I need this?
-    void copyArchRegs(ThreadContext *tc)
+    void copyArchRegs(ThreadContext *tc) override
     {
         actualTC->copyArchRegs(tc);
         checkerTC->copyArchRegs(tc);
     }
 
-    void clearArchRegs()
+    void clearArchRegs() override
     {
         actualTC->clearArchRegs();
         checkerTC->clearArchRegs();
@@ -206,61 +212,63 @@ class CheckerThreadContext : public ThreadContext
     //
     // New accessors for new decoder.
     //
-    RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
+    RegVal readIntReg(int reg_idx) override {
+        return actualTC->readIntReg(reg_idx);
+    }
 
     RegVal
-    readFloatReg(int reg_idx)
+    readFloatReg(int reg_idx) override
     {
         return actualTC->readFloatReg(reg_idx);
     }
 
-    const VecRegContainer& readVecReg(const RegId& reg) const
+    const VecRegContainer& readVecReg (const RegId& reg) const override
     { return actualTC->readVecReg(reg); }
 
     /**
      * Read vector register for modification, hierarchical indexing.
      */
-    VecRegContainer& getWritableVecReg(const RegId& reg)
+    VecRegContainer& getWritableVecReg (const RegId& reg) override
     { return actualTC->getWritableVecReg(reg); }
 
     /** Vector Register Lane Interfaces. */
     /** @{ */
     /** Reads source vector 8bit operand. */
     ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const
+    readVec8BitLaneReg(const RegId& reg) const override
     { return actualTC->readVec8BitLaneReg(reg); }
 
     /** Reads source vector 16bit operand. */
     ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const
+    readVec16BitLaneReg(const RegId& reg) const override
     { return actualTC->readVec16BitLaneReg(reg); }
 
     /** Reads source vector 32bit operand. */
     ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const
+    readVec32BitLaneReg(const RegId& reg) const override
     { return actualTC->readVec32BitLaneReg(reg); }
 
     /** Reads source vector 64bit operand. */
     ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const
+    readVec64BitLaneReg(const RegId& reg) const override
     { return actualTC->readVec64BitLaneReg(reg); }
 
     /** Write a lane of the destination vector register. */
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val)
+            const LaneData<LaneSize::Byte>& val) override
     { return actualTC->setVecLane(reg, val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val)
+            const LaneData<LaneSize::TwoByte>& val) override
     { return actualTC->setVecLane(reg, val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val)
+            const LaneData<LaneSize::FourByte>& val) override
     { return actualTC->setVecLane(reg, val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val)
+            const LaneData<LaneSize::EightByte>& val) override
     { return actualTC->setVecLane(reg, val); }
     /** @} */
 
-    const VecElem& readVecElem(const RegId& reg) const
+    const VecElem& readVecElem(const RegId& reg) const override
     { return actualTC->readVecElem(reg); }
 
     const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
@@ -269,58 +277,58 @@ class CheckerThreadContext : public ThreadContext
     VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
     { return actualTC->getWritableVecPredReg(reg); }
 
-    RegVal readCCReg(int reg_idx)
+    RegVal readCCReg(int reg_idx) override
     { return actualTC->readCCReg(reg_idx); }
 
     void
-    setIntReg(int reg_idx, RegVal val)
+    setIntReg(int reg_idx, RegVal val) override
     {
         actualTC->setIntReg(reg_idx, val);
         checkerTC->setIntReg(reg_idx, val);
     }
 
     void
-    setFloatReg(int reg_idx, RegVal val)
+    setFloatReg(int reg_idx, RegVal val) override
     {
         actualTC->setFloatReg(reg_idx, val);
         checkerTC->setFloatReg(reg_idx, val);
     }
 
     void
-    setVecReg(const RegId& reg, const VecRegContainer& val)
+    setVecReg(const RegId& reg, const VecRegContainer& val) override
     {
         actualTC->setVecReg(reg, val);
         checkerTC->setVecReg(reg, val);
     }
 
     void
-    setVecElem(const RegId& reg, const VecElem& val)
+    setVecElem(const RegId& reg, const VecElem& val) override
     {
         actualTC->setVecElem(reg, val);
         checkerTC->setVecElem(reg, val);
     }
 
     void
-    setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
+    setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
     {
         actualTC->setVecPredReg(reg, val);
         checkerTC->setVecPredReg(reg, val);
     }
 
     void
-    setCCReg(int reg_idx, RegVal val)
+    setCCReg(int reg_idx, RegVal val) override
     {
         actualTC->setCCReg(reg_idx, val);
         checkerTC->setCCReg(reg_idx, val);
     }
 
     /** Reads this thread's PC state. */
-    TheISA::PCState pcState()
+    TheISA::PCState pcState() override
     { return actualTC->pcState(); }
 
     /** Sets this thread's PC state. */
     void
-    pcState(const TheISA::PCState &val)
+    pcState(const TheISA::PCState &val) override
     {
         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
                          val, checkerTC->pcState());
@@ -337,31 +345,31 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    pcStateNoRecord(const TheISA::PCState &val)
+    pcStateNoRecord(const TheISA::PCState &val) override
     {
         return actualTC->pcState(val);
     }
 
     /** Reads this thread's PC. */
-    Addr instAddr()
+    Addr instAddr() override
     { return actualTC->instAddr(); }
 
     /** Reads this thread's next PC. */
-    Addr nextInstAddr()
+    Addr nextInstAddr() override
     { return actualTC->nextInstAddr(); }
 
     /** Reads this thread's next PC. */
-    MicroPC microPC()
+    MicroPC microPC() override
     { return actualTC->microPC(); }
 
-    RegVal readMiscRegNoEffect(int misc_reg) const
+    RegVal readMiscRegNoEffect(int misc_reg) const override
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
-    RegVal readMiscReg(int misc_reg)
+    RegVal readMiscReg(int misc_reg) override
     { return actualTC->readMiscReg(misc_reg); }
 
     void
-    setMiscRegNoEffect(int misc_reg, RegVal val)
+    setMiscRegNoEffect(int misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -370,7 +378,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setMiscReg(int misc_reg, RegVal val)
+    setMiscReg(int misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -379,44 +387,46 @@ class CheckerThreadContext : public ThreadContext
     }
 
     RegId
-    flattenRegId(const RegId& regId) const
+    flattenRegId(const RegId& regId) const override
     {
         return actualTC->flattenRegId(regId);
     }
 
-    unsigned readStCondFailures()
+    unsigned readStCondFailures() override
     { return actualTC->readStCondFailures(); }
 
     void
-    setStCondFailures(unsigned sc_failures)
+    setStCondFailures(unsigned sc_failures) override
     {
         actualTC->setStCondFailures(sc_failures);
     }
 
-    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
+    Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
 
-    RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
+    RegVal readIntRegFlat(int idx) override {
+        return actualTC->readIntRegFlat(idx);
+    }
 
     void
-    setIntRegFlat(int idx, RegVal val)
+    setIntRegFlat(int idx, RegVal val) override
     {
         actualTC->setIntRegFlat(idx, val);
     }
 
     RegVal
-    readFloatRegFlat(int idx)
+    readFloatRegFlat(int idx) override
     {
         return actualTC->readFloatRegFlat(idx);
     }
 
     void
-    setFloatRegFlat(int idx, RegVal val)
+    setFloatRegFlat(int idx, RegVal val) override
     {
         actualTC->setFloatRegFlat(idx, val);
     }
 
     const VecRegContainer &
-    readVecRegFlat(int idx) const
+    readVecRegFlat(int idx) const override
     {
         return actualTC->readVecRegFlat(idx);
     }
@@ -425,20 +435,20 @@ class CheckerThreadContext : public ThreadContext
      * Read vector register for modification, flat indexing.
      */
     VecRegContainer &
-    getWritableVecRegFlat(int idx)
+    getWritableVecRegFlat(int idx) override
     {
         return actualTC->getWritableVecRegFlat(idx);
     }
 
-    void setVecRegFlat(int idx, const VecRegContainer& val)
+    void setVecRegFlat(int idx, const VecRegContainer& val) override
     { actualTC->setVecRegFlat(idx, val); }
 
     const VecElem& readVecElemFlat(const RegIndex& idx,
-                                   const ElemIndex& elem_idx) const
+                                   const ElemIndex& elem_idx) const override
     { return actualTC->readVecElemFlat(idx, elem_idx); }
 
     void setVecElemFlat(const RegIndex& idx,
-                        const ElemIndex& elem_idx, const VecElem& val)
+                        const ElemIndex& elem_idx, const VecElem& val) override
     { actualTC->setVecElemFlat(idx, elem_idx, val); }
 
     const VecPredRegContainer& readVecPredRegFlat(int idx) const override
@@ -450,10 +460,10 @@ class CheckerThreadContext : public ThreadContext
     void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
     { actualTC->setVecPredRegFlat(idx, val); }
 
-    RegVal readCCRegFlat(int idx)
+    RegVal readCCRegFlat(int idx) override
     { return actualTC->readCCRegFlat(idx); }
 
-    void setCCRegFlat(int idx, RegVal val)
+    void setCCRegFlat(int idx, RegVal val) override
     { actualTC->setCCRegFlat(idx, val); }
 };
 
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 34bd71dfb..179883ecc 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -204,7 +204,7 @@ class ExecContext : public ::ExecContext
 
     void
     setVecPredRegOperand(const StaticInst *si, int idx,
-                         const TheISA::VecPredRegContainer& val)
+                         const TheISA::VecPredRegContainer& val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecPredReg());
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index fc9abb92e..640ebf850 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -137,7 +137,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     RegVal
-    readMiscReg(int misc_reg)
+    readMiscReg(int misc_reg) override
     {
         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscReg(int misc_reg, RegVal val)
+    setMiscReg(int misc_reg, RegVal val) override
     {
         /** Writes to misc. registers are recorded and deferred until the
          * commit stage, when updateMiscRegs() is called. First, check if
@@ -171,7 +171,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     RegVal
-    readMiscRegOperand(const StaticInst *si, int idx)
+    readMiscRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isMiscReg());
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
@@ -249,13 +249,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         }
     }
     /** Calls hardware return from error interrupt. */
-    Fault hwrei();
+    Fault hwrei() override;
     /** Traps to handle specified fault. */
     void trap(const Fault &fault);
-    bool simPalCheck(int palFunc);
+    bool simPalCheck(int palFunc) override;
 
     /** Emulates a syscall. */
-    void syscall(int64_t callnum, Fault *fault);
+    void syscall(int64_t callnum, Fault *fault) override;
 
   public:
 
@@ -271,19 +271,19 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     // to do).
 
     RegVal
-    readIntRegOperand(const StaticInst *si, int idx)
+    readIntRegOperand(const StaticInst *si, int idx) override
     {
         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
     }
 
     RegVal
-    readFloatRegOperandBits(const StaticInst *si, int idx)
+    readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
         return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
     }
 
     const VecRegContainer&
-    readVecRegOperand(const StaticInst *si, int idx) const
+    readVecRegOperand(const StaticInst *si, int idx) const override
     {
         return this->cpu->readVecReg(this->_srcRegIdx[idx]);
     }
@@ -292,7 +292,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * Read destination vector register operand for modification.
      */
     VecRegContainer&
-    getWritableVecRegOperand(const StaticInst *si, int idx)
+    getWritableVecRegOperand(const StaticInst *si, int idx) override
     {
         return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
     }
@@ -301,28 +301,28 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** @{ */
     /** Reads source vector 8bit operand. */
     ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const
+    readVec8BitLaneOperand(const StaticInst *si, int idx) const override
     {
         return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
     }
 
     /** Reads source vector 16bit operand. */
     ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const
+    readVec16BitLaneOperand(const StaticInst *si, int idx) const override
     {
         return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
     }
 
     /** Reads source vector 32bit operand. */
     ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const
+    readVec32BitLaneOperand(const StaticInst *si, int idx) const override
     {
         return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
     }
 
     /** Reads source vector 64bit operand. */
     ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const
+    readVec64BitLaneOperand(const StaticInst *si, int idx) const override
     {
         return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
     }
@@ -336,31 +336,31 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
     virtual void
     setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val)
+            const LaneData<LaneSize::Byte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
     virtual void
     setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val)
+            const LaneData<LaneSize::TwoByte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
     virtual void
     setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val)
+            const LaneData<LaneSize::FourByte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
     virtual void
     setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val)
+            const LaneData<LaneSize::EightByte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
     /** @} */
 
-    VecElem readVecElemOperand(const StaticInst *si, int idx) const
+    VecElem readVecElemOperand(const StaticInst *si, int idx) const override
     {
         return this->cpu->readVecElem(this->_srcRegIdx[idx]);
     }
@@ -378,7 +378,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
     RegVal
-    readCCRegOperand(const StaticInst *si, int idx)
+    readCCRegOperand(const StaticInst *si, int idx) override
     {
         return this->cpu->readCCReg(this->_srcRegIdx[idx]);
     }
@@ -387,14 +387,14 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      *  registers.
      */
     void
-    setIntRegOperand(const StaticInst *si, int idx, RegVal val)
+    setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setIntReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
     void
-    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
+    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setFloatReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
@@ -402,14 +402,14 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     void
     setVecRegOperand(const StaticInst *si, int idx,
-                     const VecRegContainer& val)
+                     const VecRegContainer& val) override
     {
         this->cpu->setVecReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
     }
 
     void setVecElemOperand(const StaticInst *si, int idx,
-                           const VecElem val)
+                           const VecElem val) override
     {
         int reg_idx = idx;
         this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
@@ -424,7 +424,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
+    void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setCCReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 003726c7c..81b7c04a5 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -234,7 +234,7 @@ class LSQ
         /** LQ/SQ entry idx. */
         uint32_t _entryIdx;
 
-        void markDelayed() { flags.set(Flag::Delayed); }
+        void markDelayed() override { flags.set(Flag::Delayed); }
         bool isDelayed() { return flags.isSet(Flag::Delayed); }
 
       public:
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 5a05c0200..022e71291 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -79,100 +79,106 @@ class O3ThreadContext : public ThreadContext
     O3ThreadState<Impl> *thread;
 
     /** Returns a pointer to the ITB. */
-    BaseTLB *getITBPtr() { return cpu->itb; }
+    BaseTLB *getITBPtr() override { return cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    BaseTLB *getDTBPtr() { return cpu->dtb; }
+    BaseTLB *getDTBPtr() override { return cpu->dtb; }
 
-    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
 
     TheISA::Decoder *
-    getDecoderPtr()
+    getDecoderPtr() override
     {
         return cpu->fetch.decoder[thread->threadId()];
     }
 
     /** Returns a pointer to this CPU. */
-    virtual BaseCPU *getCpuPtr() { return cpu; }
+    virtual BaseCPU *getCpuPtr() override { return cpu; }
 
     /** Reads this CPU's ID. */
-    virtual int cpuId() const { return cpu->cpuId(); }
+    virtual int cpuId() const override { return cpu->cpuId(); }
 
     /** Reads this CPU's Socket ID. */
-    virtual uint32_t socketId() const { return cpu->socketId(); }
+    virtual uint32_t socketId() const override { return cpu->socketId(); }
 
-    virtual ContextID contextId() const { return thread->contextId(); }
+    virtual ContextID
+    contextId() const override { return thread->contextId(); }
 
-    virtual void setContextId(int id) { thread->setContextId(id); }
+    virtual void setContextId(int id) override { thread->setContextId(id); }
 
     /** Returns this thread's ID number. */
-    virtual int threadId() const { return thread->threadId(); }
-    virtual void setThreadId(int id) { return thread->setThreadId(id); }
+    virtual int threadId() const override
+    { return thread->threadId(); }
+    virtual void setThreadId(int id) override
+    { return thread->setThreadId(id); }
 
     /** Returns a pointer to the system. */
-    virtual System *getSystemPtr() { return cpu->system; }
+    virtual System *getSystemPtr() override { return cpu->system; }
 
     /** Returns a pointer to this thread's kernel statistics. */
-    virtual TheISA::Kernel::Statistics *getKernelStats()
+    virtual TheISA::Kernel::Statistics *getKernelStats() override
     { return thread->kernelStats; }
 
     /** Returns a pointer to this thread's process. */
-    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
+    virtual Process *getProcessPtr() override
+    { return thread->getProcessPtr(); }
 
-    virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); }
+    virtual void setProcessPtr(Process *p) override
+    { thread->setProcessPtr(p); }
 
-    virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
+    virtual PortProxy &getPhysProxy() override
+    { return thread->getPhysProxy(); }
 
-    virtual FSTranslatingPortProxy &getVirtProxy();
+    virtual FSTranslatingPortProxy &getVirtProxy() override;
 
-    virtual void initMemProxies(ThreadContext *tc)
+    virtual void initMemProxies(ThreadContext *tc) override
     { thread->initMemProxies(tc); }
 
-    virtual SETranslatingPortProxy &getMemProxy()
+    virtual SETranslatingPortProxy &getMemProxy() override
     { return thread->getMemProxy(); }
 
     /** Returns this thread's status. */
-    virtual Status status() const { return thread->status(); }
+    virtual Status status() const override { return thread->status(); }
 
     /** Sets this thread's status. */
-    virtual void setStatus(Status new_status)
+    virtual void setStatus(Status new_status) override
     { thread->setStatus(new_status); }
 
     /** Set the status to Active. */
-    virtual void activate();
+    virtual void activate() override;
 
     /** Set the status to Suspended. */
-    virtual void suspend();
+    virtual void suspend() override;
 
     /** Set the status to Halted. */
-    virtual void halt();
+    virtual void halt() override;
 
     /** Dumps the function profiling information.
      * @todo: Implement.
      */
-    virtual void dumpFuncProfile();
+    virtual void dumpFuncProfile() override;
 
     /** Takes over execution of a thread from another CPU. */
-    virtual void takeOverFrom(ThreadContext *old_context);
+    virtual void takeOverFrom(ThreadContext *old_context) override;
 
     /** Registers statistics associated with this TC. */
-    virtual void regStats(const std::string &name);
+    virtual void regStats(const std::string &name) override;
 
     /** Reads the last tick that this thread was activated on. */
-    virtual Tick readLastActivate();
+    virtual Tick readLastActivate() override;
     /** Reads the last tick that this thread was suspended on. */
-    virtual Tick readLastSuspend();
+    virtual Tick readLastSuspend() override;
 
     /** Clears the function profiling information. */
-    virtual void profileClear();
+    virtual void profileClear() override;
     /** Samples the function profiling information. */
-    virtual void profileSample();
+    virtual void profileSample() override;
 
     /** Copies the architectural registers from another TC into this TC. */
-    virtual void copyArchRegs(ThreadContext *tc);
+    virtual void copyArchRegs(ThreadContext *tc) override;
 
     /** Resets all architectural registers to 0. */
-    virtual void clearArchRegs();
+    virtual void clearArchRegs() override;
 
     /** Reads an integer register. */
     virtual RegVal
@@ -182,21 +188,21 @@ class O3ThreadContext : public ThreadContext
                                                  reg_idx)).index());
     }
     virtual RegVal
-    readIntReg(int reg_idx)
+    readIntReg(int reg_idx) override
     {
         return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                  reg_idx)).index());
     }
 
     virtual RegVal
-    readFloatReg(int reg_idx)
+    readFloatReg(int reg_idx) override
     {
         return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                              reg_idx)).index());
     }
 
     virtual const VecRegContainer &
-    readVecReg(const RegId& id) const
+    readVecReg(const RegId& id) const override
     {
         return readVecRegFlat(flattenRegId(id).index());
     }
@@ -205,7 +211,7 @@ class O3ThreadContext : public ThreadContext
      * Read vector register operand for modification, hierarchical indexing.
      */
     virtual VecRegContainer &
-    getWritableVecReg(const RegId& id)
+    getWritableVecReg(const RegId& id) override
     {
         return getWritableVecRegFlat(flattenRegId(id).index());
     }
@@ -214,7 +220,7 @@ class O3ThreadContext : public ThreadContext
     /** @{ */
     /** Reads source vector 8bit operand. */
     virtual ConstVecLane8
-    readVec8BitLaneReg(const RegId& id) const
+    readVec8BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
                     id.elemIndex());
@@ -222,7 +228,7 @@ class O3ThreadContext : public ThreadContext
 
     /** Reads source vector 16bit operand. */
     virtual ConstVecLane16
-    readVec16BitLaneReg(const RegId& id) const
+    readVec16BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
                     id.elemIndex());
@@ -230,7 +236,7 @@ class O3ThreadContext : public ThreadContext
 
     /** Reads source vector 32bit operand. */
     virtual ConstVecLane32
-    readVec32BitLaneReg(const RegId& id) const
+    readVec32BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
                     id.elemIndex());
@@ -238,7 +244,7 @@ class O3ThreadContext : public ThreadContext
 
     /** Reads source vector 64bit operand. */
     virtual ConstVecLane64
-    readVec64BitLaneReg(const RegId& id) const
+    readVec64BitLaneReg(const RegId& id) const override
     {
         return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
                     id.elemIndex());
@@ -246,33 +252,35 @@ class O3ThreadContext : public ThreadContext
 
     /** Write a lane of the destination vector register. */
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val)
+            const LaneData<LaneSize::Byte>& val) override
     { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val)
+            const LaneData<LaneSize::TwoByte>& val) override
     { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val)
+            const LaneData<LaneSize::FourByte>& val) override
     { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
     virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val)
+            const LaneData<LaneSize::EightByte>& val) override
     { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
     /** @} */
 
-    virtual const VecElem& readVecElem(const RegId& reg) const {
+    virtual const VecElem& readVecElem(const RegId& reg) const override {
         return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
     }
 
-    virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const {
+    virtual const VecPredRegContainer&
+    readVecPredReg(const RegId& id) const override {
         return readVecPredRegFlat(flattenRegId(id).index());
     }
 
-    virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) {
+    virtual VecPredRegContainer&
+    getWritableVecPredReg(const RegId& id) override {
         return getWritableVecPredRegFlat(flattenRegId(id).index());
     }
 
     virtual RegVal
-    readCCReg(int reg_idx)
+    readCCReg(int reg_idx) override
     {
         return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                  reg_idx)).index());
@@ -280,101 +288,101 @@ class O3ThreadContext : public ThreadContext
 
     /** Sets an integer register to a value. */
     virtual void
-    setIntReg(int reg_idx, RegVal val)
+    setIntReg(int reg_idx, RegVal val) override
     {
         setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
     }
 
     virtual void
-    setFloatReg(int reg_idx, RegVal val)
+    setFloatReg(int reg_idx, RegVal val) override
     {
         setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                            reg_idx)).index(), val);
     }
 
     virtual void
-    setVecReg(const RegId& reg, const VecRegContainer& val)
+    setVecReg(const RegId& reg, const VecRegContainer& val) override
     {
         setVecRegFlat(flattenRegId(reg).index(), val);
     }
 
     virtual void
-    setVecElem(const RegId& reg, const VecElem& val)
+    setVecElem(const RegId& reg, const VecElem& val) override
     {
         setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
     }
 
     virtual void
     setVecPredReg(const RegId& reg,
-                  const VecPredRegContainer& val)
+                  const VecPredRegContainer& val) override
     {
         setVecPredRegFlat(flattenRegId(reg).index(), val);
     }
 
     virtual void
-    setCCReg(int reg_idx, RegVal val)
+    setCCReg(int reg_idx, RegVal val) override
     {
         setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
     }
 
     /** Reads this thread's PC state. */
-    virtual TheISA::PCState pcState()
+    virtual TheISA::PCState pcState() override
     { return cpu->pcState(thread->threadId()); }
 
     /** Sets this thread's PC state. */
-    virtual void pcState(const TheISA::PCState &val);
+    virtual void pcState(const TheISA::PCState &val) override;
 
-    virtual void pcStateNoRecord(const TheISA::PCState &val);
+    virtual void pcStateNoRecord(const TheISA::PCState &val) override;
 
     /** Reads this thread's PC. */
-    virtual Addr instAddr()
+    virtual Addr instAddr() override
     { return cpu->instAddr(thread->threadId()); }
 
     /** Reads this thread's next PC. */
-    virtual Addr nextInstAddr()
+    virtual Addr nextInstAddr() override
     { return cpu->nextInstAddr(thread->threadId()); }
 
     /** Reads this thread's next PC. */
-    virtual MicroPC microPC()
+    virtual MicroPC microPC() override
     { return cpu->microPC(thread->threadId()); }
 
     /** Reads a miscellaneous register. */
-    virtual RegVal readMiscRegNoEffect(int misc_reg) const
+    virtual RegVal readMiscRegNoEffect(int misc_reg) const override
     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual RegVal readMiscReg(int misc_reg)
+    virtual RegVal readMiscReg(int misc_reg) override
     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
+    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override;
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscReg(int misc_reg, RegVal val);
+    virtual void setMiscReg(int misc_reg, RegVal val) override;
 
-    virtual RegId flattenRegId(const RegId& regId) const;
+    virtual RegId flattenRegId(const RegId& regId) const override;
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
-    virtual unsigned readStCondFailures()
+    virtual unsigned readStCondFailures() override
     { return thread->storeCondFailures; }
 
     /** Sets the number of consecutive store conditional failures. */
-    virtual void setStCondFailures(unsigned sc_failures)
+    virtual void setStCondFailures(unsigned sc_failures) override
     { thread->storeCondFailures = sc_failures; }
 
     /** Executes a syscall in SE mode. */
-    virtual void syscall(int64_t callnum, Fault *fault)
+    virtual void syscall(int64_t callnum, Fault *fault) override
     { return cpu->syscall(callnum, thread->threadId(), fault); }
 
     /** Reads the funcExeInst counter. */
-    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
+    virtual Counter readFuncExeInst() override { return thread->funcExeInst; }
 
     /** Returns pointer to the quiesce event. */
     virtual EndQuiesceEvent *
-    getQuiesceEvent()
+    getQuiesceEvent() override
     {
         return this->thread->quiesceEvent;
     }
@@ -390,16 +398,16 @@ class O3ThreadContext : public ThreadContext
             cpu->squashFromTC(thread->threadId());
     }
 
-    virtual RegVal readIntRegFlat(int idx);
-    virtual void setIntRegFlat(int idx, RegVal val);
+    virtual RegVal readIntRegFlat(int idx) override;
+    virtual void setIntRegFlat(int idx, RegVal val) override;
 
-    virtual RegVal readFloatRegFlat(int idx);
-    virtual void setFloatRegFlat(int idx, RegVal val);
+    virtual RegVal readFloatRegFlat(int idx) override;
+    virtual void setFloatRegFlat(int idx, RegVal val) override;
 
-    virtual const VecRegContainer& readVecRegFlat(int idx) const;
+    virtual const VecRegContainer& readVecRegFlat(int idx) const override;
     /** Read vector register operand for modification, flat indexing. */
-    virtual VecRegContainer& getWritableVecRegFlat(int idx);
-    virtual void setVecRegFlat(int idx, const VecRegContainer& val);
+    virtual VecRegContainer& getWritableVecRegFlat(int idx) override;
+    virtual void setVecRegFlat(int idx, const VecRegContainer& val) override;
 
     template <typename VecElem>
     VecLaneT<VecElem, true>
@@ -415,10 +423,12 @@ class O3ThreadContext : public ThreadContext
         cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
     }
 
-    virtual const VecElem& readVecElemFlat(const RegIndex& idx,
-                                           const ElemIndex& elemIndex) const;
-    virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
-                                const VecElem& val);
+    virtual const VecElem& readVecElemFlat(
+        const RegIndex& idx,
+        const ElemIndex& elemIndex) const override;
+    virtual void setVecElemFlat(
+        const RegIndex& idx,
+        const ElemIndex& elemIdx, const VecElem& val) override;
 
     virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
         const override;
@@ -426,8 +436,8 @@ class O3ThreadContext : public ThreadContext
     virtual void setVecPredRegFlat(int idx,
                                    const VecPredRegContainer& val) override;
 
-    virtual RegVal readCCRegFlat(int idx);
-    virtual void setCCRegFlat(int idx, RegVal val);
+    virtual RegVal readCCRegFlat(int idx) override;
+    virtual void setCCRegFlat(int idx, RegVal val) override;
 };
 
 #endif