diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-07-27 01:03:44 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-07-27 01:03:44 -0400 |
| commit | 1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926 (patch) | |
| tree | 8deb8fa950c8c4045cb9492804ebfb6b5731499f | |
| parent | 97d245278d4b4bee844c141c3b6f370e27f73a45 (diff) | |
| download | gem5-1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926.tar.xz | |
ARM: Add regression tests
64 files changed, 7826 insertions, 0 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..5226b78e6 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..95afc07f5 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 298674141000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..f2e408360 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2670640 # Simulator instruction rate (inst/s) +host_mem_usage 197140 # Number of bytes of host memory used +host_seconds 223.66 # Real time elapsed on the host +host_tick_rate 1335369827 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 597325393 # Number of instructions simulated +sim_seconds 0.298674 # Number of seconds simulated +sim_ticks 298674141000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 597348283 # number of cpu cycles simulated +system.cpu.num_insts 597325393 # Number of instructions executed +system.cpu.num_refs 219174038 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..c729d1474 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..86786e4fe --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 808121048000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..e4204dab3 --- /dev/null +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1588198 # Simulator instruction rate (inst/s) +host_mem_usage 204824 # Number of bytes of host memory used +host_seconds 374.87 # Real time elapsed on the host +host_tick_rate 2155749682 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 595363823 # Number of instructions simulated +sim_seconds 0.808121 # Number of seconds simulated +sim_ticks 808121048000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses +system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 216713991 # number of overall hits +system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses +system.cpu.dcache.overall_misses 498477 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 433495 # number of replacements +system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use +system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 305427 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 570070553 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 570069910 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 886578.398134 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 570070553 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency +system.cpu.icache.demand_hits 570069910 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 643 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context +system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 570069910 # number of overall hits +system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 643 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use +system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 157466 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 280768 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 81265 # number of replacements +system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use +system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 61092 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1616242096 # number of cpu cycles simulated +system.cpu.num_insts 595363823 # Number of instructions executed +system.cpu.num_refs 219174038 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..51e730713 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:268435455 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..c7a7ab51b --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:59:27 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 54182628000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..80fc2bb27 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2639601 # Simulator instruction rate (inst/s) +host_mem_usage 330716 # Number of bytes of host memory used +host_seconds 34.53 # Real time elapsed on the host +host_tick_rate 1569281777 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 91136893 # Number of instructions simulated +sim_seconds 0.054183 # Number of seconds simulated +sim_ticks 54182628000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 108365257 # number of cpu cycles simulated +system.cpu.num_insts 91136893 # Number of instructions executed +system.cpu.num_refs 27330336 # Number of memory references +system.cpu.workload.PROG:num_syscalls 442 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..7b31977b8 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:268435455 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..d65963e33 --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 152158072000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..ae84c8f2c --- /dev/null +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1187634 # Simulator instruction rate (inst/s) +host_mem_usage 338364 # Number of bytes of host memory used +host_seconds 76.72 # Real time elapsed on the host +host_tick_rate 1983393949 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 91110245 # Number of instructions simulated +sim_seconds 0.152158 # Number of seconds simulated +sim_ticks 152158072000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 21664622 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12615288000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.039894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 900198 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9914694000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4642722 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5384176000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.020289 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 96146 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5095738000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.020289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 96146 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18065.511510 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26307344 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17999464000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.036491 # miss rate for demand accesses +system.cpu.dcache.demand_misses 996344 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 15010432000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.036491 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 996344 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.874740 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3582.934837 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18065.511510 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 26307344 # number of overall hits +system.cpu.dcache.overall_miss_latency 17999464000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.036491 # miss rate for overall accesses +system.cpu.dcache.overall_misses 996344 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 15010432000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.036491 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 996344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 942711 # number of replacements +system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3582.934837 # Cycle average of tags in use +system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 54489025000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 96053 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 107819118 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 54667.779633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 51667.779633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 107818519 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32746000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 30949000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 179997.527546 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 107819118 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 54667.779633 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency +system.cpu.icache.demand_hits 107818519 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32746000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 599 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30949000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.249734 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 511.454894 # Average occupied blocks per context +system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 107818519 # number of overall hits +system.cpu.icache.overall_miss_latency 32746000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 599 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30949000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.454894 # Cycle average of tags in use +system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2423668000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 46609 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 46609 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 899919 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 45656000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.000975 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 878 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 49537 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2575924000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 49537 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1981480000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 49537 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 96053 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 96053 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 52.567404 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 899919 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2469324000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050123 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47487 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 1899480000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050123 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47487 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.009182 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.265752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 300.880505 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8708.164911 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 899919 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2469324000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050123 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47487 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 1899480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050123 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47487 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 678 # number of replacements +system.cpu.l2cache.sampled_refs 15333 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 9009.045417 # Cycle average of tags in use +system.cpu.l2cache.total_refs 806016 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 35 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 304316144 # number of cpu cycles simulated +system.cpu.num_insts 91110245 # Number of instructions executed +system.cpu.num_refs 27330336 # Number of memory references +system.cpu.workload.PROG:num_syscalls 442 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..e9a6bfef4 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..e9989c308 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:59:31 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 284221891000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..613d26cc7 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3798348 # Simulator instruction rate (inst/s) +host_mem_usage 200684 # Number of bytes of host memory used +host_seconds 147.02 # Real time elapsed on the host +host_tick_rate 1933283176 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 558414014 # Number of instructions simulated +sim_seconds 0.284222 # Number of seconds simulated +sim_ticks 284221891000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 568443783 # number of cpu cycles simulated +system.cpu.num_insts 558414014 # Number of instructions executed +system.cpu.num_refs 184987503 # Number of memory references +system.cpu.workload.PROG:num_syscalls 548 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..7672e8015 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..9d8b1ad31 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 755274721000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..8d9317660 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1423169 # Simulator instruction rate (inst/s) +host_mem_usage 208376 # Number of bytes of host memory used +host_seconds 391.02 # Real time elapsed on the host +host_tick_rate 1931572776 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 556480686 # Number of instructions simulated +sim_seconds 0.755275 # Number of seconds simulated +sim_ticks 755274721000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 22055.619697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19055.619697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17269462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 14920474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.902227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.902227 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 54940305 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44102275000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.014132 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 787542 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 41739649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.014132 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 787542 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 39076.887665 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency +system.cpu.dcache.demand_hits 181483635 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 61371737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008580 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1570538 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 56660123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.008580 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1570538 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.993060 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4067.574815 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 39076.887665 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 181483635 # number of overall hits +system.cpu.dcache.overall_miss_latency 61371737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008580 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1570538 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 56660123000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.008580 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1570538 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1135200 # number of replacements +system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4067.574815 # Cycle average of tags in use +system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11579638000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 784411 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 24746.983769 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 21746.983769 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 285110000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 250547000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 44452.238521 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 24746.983769 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency +system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 285110000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 250547000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.485758 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 994.831789 # Average occupied blocks per context +system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 24746.983769 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 512134240 # number of overall hits +system.cpu.icache.overall_miss_latency 285110000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_misses 11521 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 250547000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 9788 # number of replacements +system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 994.831789 # Cycle average of tags in use +system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 18527600000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 356300 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 14252000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 356300 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 641390 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 7962604000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.192730 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 153127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 6125080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.192730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 153127 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 431242 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.715190 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 22420580000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 431242 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 17249680000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 431242 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 784411 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 784411 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 4.037361 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 641390 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 26490204000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.442666 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 509427 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 20377080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.442666 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 509427 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.106439 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.402713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3487.785932 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13196.100733 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 641390 # number of overall hits +system.cpu.l2cache.overall_miss_latency 26490204000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.442666 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 509427 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 20377080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.442666 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 509427 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 258533 # number of replacements +system.cpu.l2cache.sampled_refs 276277 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 16683.886665 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1115430 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 531606891000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 206160 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1510549442 # number of cpu cycles simulated +system.cpu.num_insts 556480686 # Number of instructions executed +system.cpu.num_refs 184987503 # Number of memory references +system.cpu.workload.PROG:num_syscalls 548 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..0f7678eb4 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..0de362399 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,49 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 +hack: be nice to actually delete the event here diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..13460aa66 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,21 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:56:52 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +OO-style eon Time= 0.210000 +Exiting @ tick 210098857000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..624970b79 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2179170 # Simulator instruction rate (inst/s) +host_mem_usage 205868 # Number of bytes of host memory used +host_seconds 158.12 # Real time elapsed on the host +host_tick_rate 1328711028 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 344575026 # Number of instructions simulated +sim_seconds 0.210099 # Number of seconds simulated +sim_ticks 210098857000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 420197715 # number of cpu cycles simulated +system.cpu.num_insts 344575026 # Number of instructions executed +system.cpu.num_refs 177028576 # Number of memory references +system.cpu.workload.PROG:num_syscalls 191 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..3e8fe5eab --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..0de362399 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,49 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 +hack: be nice to actually delete the event here diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..986b22d40 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -0,0 +1,21 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:36 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +OO-style eon Time= 0.520000 +Exiting @ tick 525836291000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..792d75c5d --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1001528 # Simulator instruction rate (inst/s) +host_mem_usage 213556 # Number of bytes of host memory used +host_seconds 343.67 # Real time elapsed on the host +host_tick_rate 1530053892 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 344196749 # Number of instructions simulated +sim_seconds 0.525836 # Number of seconds simulated +sim_ticks 525836291000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94585118 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 79912000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1607 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 82060523 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 170744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000037 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3049 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 161597000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000037 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 3049 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 53835.051546 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency +system.cpu.dcache.demand_hits 176645641 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 250656000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4656 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 236688000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4656 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.751811 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3079.417400 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 53835.051546 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 176645641 # number of overall hits +system.cpu.dcache.overall_miss_latency 250656000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4656 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 236688000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4656 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1332 # number of replacements +system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3079.417400 # Cycle average of tags in use +system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 974 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 348627536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 348611933 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 22342.622124 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 348627536 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency +system.cpu.icache.demand_hits 348611933 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses +system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.862302 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1765.994016 # Average occupied blocks per context +system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 348611933 # number of overall hits +system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses +system.cpu.icache.overall_misses 15603 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 13796 # number of replacements +system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1765.994016 # Cycle average of tags in use +system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 149344000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 2872 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 114880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 2872 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 13233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.231087 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 177 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 9204000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 177 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7080000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 177 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.776587 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 13233 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 356148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.341052 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 6849 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 273960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.341052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 6849 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.091337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.010370 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2992.938866 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 339.814124 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 13233 # number of overall hits +system.cpu.l2cache.overall_miss_latency 356148000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.341052 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 6849 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 273960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.341052 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 6849 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 48 # number of replacements +system.cpu.l2cache.sampled_refs 4758 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 3332.752990 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1051672582 # number of cpu cycles simulated +system.cpu.num_insts 344196749 # Number of instructions executed +system.cpu.num_refs 177028576 # Number of memory references +system.cpu.workload.PROG:num_syscalls 191 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..3428438b6 --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..805a6606f --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: fcntl64(3, 2) passed through to host +For more information see: http://www.m5sim.org/warn/a55e2c46 +hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..57190e92a --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,1393 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:56 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 3428045644 +1332000: 2815822229 +1331000: 1093465585 +1330000: 3012217108 +1329000: 2230916791 +1328000: 208547885 +1327000: 3592585825 +1326000: 3948677052 +1325000: 1817805162 +1324000: 135366494 +1323000: 3309148112 +1322000: 1685035744 +1321000: 3293068577 +1320000: 4097808567 +1319000: 1594097274 +1318000: 2607196971 +1317000: 1763785306 +1316000: 2157394178 +1315000: 2399031328 +1314000: 2954547004 +1313000: 82348686 +1312000: 3120930785 +1311000: 2192747320 +1310000: 1580299400 +1309000: 4085061477 +1308000: 3627048345 +1307000: 3756533178 +1306000: 77997329 +1305000: 1343359499 +1304000: 1124031730 +1303000: 1161755432 +1302000: 1855858423 +1301000: 3985872257 +1300000: 3188250811 +1299000: 3621615933 +1298000: 962624248 +1297000: 447138785 +1296000: 1459144309 +1295000: 3454504226 +1294000: 2154913347 +1293000: 2356291788 +1292000: 458348817 +1291000: 3639562699 +1290000: 3596847973 +1289000: 117168222 +1288000: 3531023849 +1287000: 3135920051 +1286000: 234987844 +1285000: 2048767180 +1284000: 2437301839 +1283000: 522886780 +1282000: 2274133042 +1281000: 1415703448 +1280000: 4145574054 +1279000: 4283494580 +1278000: 3305365779 +1277000: 604711974 +1276000: 2031548723 +1275000: 1809515149 +1274000: 1664703088 +1273000: 4149809153 +1272000: 4045608138 +1271000: 1687605659 +1270000: 1292294527 +1269000: 3120968162 +1268000: 3502898850 +1267000: 371380256 +1266000: 1683884245 +1265000: 1849576817 +1264000: 1559050991 +1263000: 66820972 +1262000: 4023539201 +1261000: 3452295398 +1260000: 4188778026 +1259000: 2008091854 +1258000: 2691158394 +1257000: 2030818206 +1256000: 2715523403 +1255000: 3473414015 +1254000: 138826953 +1253000: 69386516 +1252000: 1174725971 +1251000: 4130510373 +1250000: 1649788328 +1249000: 1589122801 +1248000: 1108688101 +1247000: 2906355484 +1246000: 379539929 +1245000: 914026021 +1244000: 4074858468 +1243000: 505989635 +1242000: 2487288773 +1241000: 1991248111 +1240000: 2415456875 +1239000: 2571192525 +1238000: 2897090536 +1237000: 2761178989 +1236000: 1296601829 +1235000: 594696756 +1234000: 264562726 +1233000: 3630852367 +1232000: 1605618457 +1231000: 2857419452 +1230000: 3028672437 +1229000: 361833758 +1228000: 4046013938 +1227000: 1031775583 +1226000: 3475227831 +1225000: 802168737 +1224000: 3819194009 +1223000: 851157666 +1222000: 2656457905 +1221000: 2579045204 +1220000: 2091024410 +1219000: 4070633834 +1218000: 1926611791 +1217000: 1903813761 +1216000: 3107168794 +1215000: 2975081979 +1214000: 4097089273 +1213000: 328943233 +1212000: 2912404803 +1211000: 181334180 +1210000: 863898367 +1209000: 1894902343 +1208000: 1531985231 +1207000: 1412503751 +1206000: 662457490 +1205000: 3447925432 +1204000: 2320889638 +1203000: 303282255 +1202000: 1568632659 +1201000: 1108711074 +1200000: 953936964 +1199000: 3576987258 +1198000: 466163300 +1197000: 1159551420 +1196000: 529807534 +1195000: 1528979627 +1194000: 1795576953 +1193000: 2050917610 +1192000: 4068219994 +1191000: 3573497288 +1190000: 776005286 +1189000: 2643125982 +1188000: 2240857507 +1187000: 43353719 +1186000: 2474198261 +1185000: 1711347056 +1184000: 3046018343 +1183000: 664346074 +1182000: 3532392595 +1181000: 3145347726 +1180000: 2203928246 +1179000: 4275910811 +1178000: 3260065240 +1177000: 3216083720 +1176000: 3588515377 +1175000: 1432542416 +1174000: 173159992 +1173000: 4115057268 +1172000: 223456174 +1171000: 1192164227 +1170000: 2059254624 +1169000: 279921804 +1168000: 1100495449 +1167000: 264813624 +1166000: 2839280440 +1165000: 301796904 +1164000: 1331933822 +1163000: 647427882 +1162000: 3872813324 +1161000: 2231068824 +1160000: 4222672618 +1159000: 3629229584 +1158000: 2262586804 +1157000: 2837951671 +1156000: 1780662312 +1155000: 31553143 +1154000: 3230861653 +1153000: 1991458597 +1152000: 2277829165 +1151000: 3864184029 +1150000: 630158826 +1149000: 4028889917 +1148000: 1662505287 +1147000: 4121796538 +1146000: 3215277282 +1145000: 2019794999 +1144000: 4124433286 +1143000: 181819953 +1142000: 2704380222 +1141000: 2487909897 +1140000: 1753570204 +1139000: 2337507591 +1138000: 3235449912 +1137000: 3819353806 +1136000: 3435413746 +1135000: 3288196653 +1134000: 2705083758 +1133000: 997301031 +1132000: 1871866706 +1131000: 2298991521 +1130000: 1516060457 +1129000: 3393393053 +1128000: 2795526466 +1127000: 1177801041 +1126000: 4226698729 +1125000: 567826718 +1124000: 2425735007 +1123000: 1090360485 +1122000: 2508061782 +1121000: 3476086116 +1120000: 2952087827 +1119000: 2238445545 +1118000: 2937037425 +1117000: 1773353797 +1116000: 3033333765 +1115000: 3086246055 +1114000: 944390435 +1113000: 2944932895 +1112000: 534683663 +1111000: 2002175399 +1110000: 1876265996 +1109000: 4148000592 +1108000: 3857174625 +1107000: 843045539 +1106000: 307772960 +1105000: 4161975075 +1104000: 3675447412 +1103000: 1232242543 +1102000: 1019583281 +1101000: 1983565552 +1100000: 2490901544 +1099000: 2990982808 +1098000: 1586955629 +1097000: 1629138000 +1096000: 1870655270 +1095000: 2201093764 +1094000: 696079363 +1093000: 1526904315 +1092000: 553848190 +1091000: 4234411636 +1090000: 1027439894 +1089000: 1319115149 +1088000: 1147708285 +1087000: 3364503693 +1086000: 528432422 +1085000: 3289100476 +1084000: 3074065438 +1083000: 3664250869 +1082000: 2950591670 +1081000: 4207904839 +1080000: 3425353965 +1079000: 1069646286 +1078000: 1004956209 +1077000: 2642475281 +1076000: 364759474 +1075000: 2334969932 +1074000: 3907002684 +1073000: 273633783 +1072000: 4113182592 +1071000: 1404306188 +1070000: 3286171051 +1069000: 3531039414 +1068000: 4147513318 +1067000: 2466290219 +1066000: 2089005579 +1065000: 2617563073 +1064000: 3124838472 +1063000: 3731008114 +1062000: 4154022628 +1061000: 3389258714 +1060000: 3915149371 +1059000: 2280932986 +1058000: 2872952978 +1057000: 2381277834 +1056000: 1236179469 +1055000: 3256417375 +1054000: 2700213407 +1053000: 3418122897 +1052000: 3130247908 +1051000: 1897033028 +1050000: 2349143738 +1049000: 3789736749 +1048000: 409522147 +1047000: 3149279018 +1046000: 1323133366 +1045000: 3881472077 +1044000: 3363874422 +1043000: 3931657349 +1042000: 1220007174 +1041000: 3634450249 +1040000: 695184634 +1039000: 529508167 +1038000: 449827627 +1037000: 2817424280 +1036000: 1613482057 +1035000: 2632612792 +1034000: 852422020 +1033000: 4098325966 +1032000: 177298753 +1031000: 2286807874 +1030000: 2745349553 +1029000: 2387386570 +1028000: 2004317534 +1027000: 971343564 +1026000: 1583732447 +1025000: 2340780818 +1024000: 561110245 +1023000: 3012020895 +1022000: 1677066870 +1021000: 3046208682 +1020000: 2695506079 +1019000: 780536149 +1018000: 4225713741 +1017000: 420500410 +1016000: 3642094643 +1015000: 608695027 +1014000: 2161592269 +1013000: 930784800 +1012000: 1924051276 +1011000: 1889733886 +1010000: 1476038251 +1009000: 2908577467 +1008000: 2584082136 +1007000: 1713214537 +1006000: 3374346754 +1005000: 1173203719 +1004000: 1142288559 +1003000: 4195961973 +1002000: 1211260974 +1001000: 474231127 +1000000: 3967090782 +999000: 1543103493 +998000: 1018646803 +997000: 1799037982 +996000: 3416426509 +995000: 3581729971 +994000: 3044504127 +993000: 2975704335 +992000: 280018795 +991000: 330300280 +990000: 3557016064 +989000: 3856724468 +988000: 2124201285 +987000: 3683893247 +986000: 3331663795 +985000: 1980057740 +984000: 2908437859 +983000: 4074086941 +982000: 1162307093 +981000: 3855413476 +980000: 2799155731 +979000: 2477822501 +978000: 497762075 +977000: 1650233426 +976000: 3061573902 +975000: 2224673611 +974000: 868725340 +973000: 1630206962 +972000: 2549398924 +971000: 602424332 +970000: 1172502721 +969000: 2923795552 +968000: 1394164637 +967000: 1088479837 +966000: 898709052 +965000: 3983150961 +964000: 2463803866 +963000: 4181117626 +962000: 2151137820 +961000: 1342513757 +960000: 1507689687 +959000: 3652624918 +958000: 4169721124 +957000: 531022334 +956000: 3161389505 +955000: 1197637232 +954000: 2927231791 +953000: 2552305374 +952000: 2988512039 +951000: 2448639370 +950000: 3560951660 +949000: 948988399 +948000: 2488188856 +947000: 2804177113 +946000: 1991587461 +945000: 2480044082 +944000: 1954588624 +943000: 924231798 +942000: 3269047595 +941000: 2078696579 +940000: 2822989969 +939000: 2295885951 +938000: 1815612561 +937000: 4182254074 +936000: 2753223967 +935000: 2840201908 +934000: 4058383142 +933000: 4270167260 +932000: 1203124158 +931000: 3039861400 +930000: 4247472610 +929000: 2297661055 +928000: 2376159704 +927000: 3861417958 +926000: 1968685250 +925000: 1156966624 +924000: 3568580529 +923000: 866582344 +922000: 2263113297 +921000: 3643523016 +920000: 3252268544 +919000: 2413309783 +918000: 3463124619 +917000: 3965291932 +916000: 1309181143 +915000: 2321282614 +914000: 2286584604 +913000: 3271924727 +912000: 1719841316 +911000: 3966124343 +910000: 607707072 +909000: 61942114 +908000: 903881820 +907000: 4136948835 +906000: 3663861210 +905000: 3251888710 +904000: 227984688 +903000: 495030333 +902000: 863290992 +901000: 3297482717 +900000: 3821175085 +899000: 1679874522 +898000: 2033358728 +897000: 3495513776 +896000: 1613181881 +895000: 1729312232 +894000: 2171317375 +893000: 2508603694 +892000: 151095866 +891000: 1926096901 +890000: 4292888210 +889000: 2716307666 +888000: 737310728 +887000: 4172392976 +886000: 2322084662 +885000: 1034961047 +884000: 665072958 +883000: 368014441 +882000: 1914585160 +881000: 3836900884 +880000: 2073827187 +879000: 1650543625 +878000: 3581099222 +877000: 147580905 +876000: 4009421518 +875000: 3294244820 +874000: 2786720968 +873000: 1682434702 +872000: 620473876 +871000: 742752376 +870000: 385116650 +869000: 3882475387 +868000: 4259210265 +867000: 1329675866 +866000: 539876515 +865000: 2761681036 +864000: 2192063038 +863000: 1512848001 +862000: 3911973718 +861000: 399349760 +860000: 1449497249 +859000: 4241714042 +858000: 18611709 +857000: 1550083097 +856000: 3322762748 +855000: 283796511 +854000: 227907270 +853000: 3162559866 +852000: 1331946455 +851000: 2328467927 +850000: 1640242501 +849000: 3390154083 +848000: 22088346 +847000: 636412590 +846000: 1550672808 +845000: 763937899 +844000: 430123910 +843000: 3413971543 +842000: 900018421 +841000: 3295874222 +840000: 2470678073 +839000: 821401909 +838000: 3923898844 +837000: 429069328 +836000: 2030779868 +835000: 464625222 +834000: 3593024182 +833000: 3564354808 +832000: 2794783695 +831000: 97817593 +830000: 4197446076 +829000: 2367560230 +828000: 2180262123 +827000: 3149571964 +826000: 1364436763 +825000: 21599634 +824000: 448490256 +823000: 3775294409 +822000: 1132631425 +821000: 2046352434 +820000: 3380435217 +819000: 3672496486 +818000: 1634548077 +817000: 2881316258 +816000: 1808599559 +815000: 3298310748 +814000: 3744285741 +813000: 3540737709 +812000: 1143844515 +811000: 3091026783 +810000: 3771757792 +809000: 631375816 +808000: 1353831646 +807000: 3047756240 +806000: 818136890 +805000: 783072818 +804000: 3923416267 +803000: 3233085529 +802000: 674747602 +801000: 758523180 +800000: 2232308489 +799000: 2919643710 +798000: 623631722 +797000: 1302202741 +796000: 1083055596 +795000: 2358048936 +794000: 2836842068 +793000: 1612571734 +792000: 4243459584 +791000: 1585511173 +790000: 1493369943 +789000: 3649557715 +788000: 3223859588 +787000: 4001130195 +786000: 2949323631 +785000: 3887611007 +784000: 4091766333 +783000: 2954277998 +782000: 1281850218 +781000: 771664458 +780000: 2242576209 +779000: 3865479146 +778000: 1885013114 +777000: 2032659742 +776000: 4221167450 +775000: 1962824751 +774000: 209539683 +773000: 262945027 +772000: 452388820 +771000: 2006266573 +770000: 990063860 +769000: 1377951885 +768000: 4240978277 +767000: 2206801004 +766000: 258015097 +765000: 1990217201 +764000: 1336410303 +763000: 1004853228 +762000: 1404152873 +761000: 3356554358 +760000: 4052430907 +759000: 2833671166 +758000: 1561723151 +757000: 1752620777 +756000: 2622547462 +755000: 1843933196 +754000: 3728801998 +753000: 2776832730 +752000: 2626131293 +751000: 1528525830 +750000: 2716112581 +749000: 3306039713 +748000: 915271993 +747000: 4205133363 +746000: 3136321783 +745000: 1203154793 +744000: 3370017183 +743000: 4036456207 +742000: 3377556743 +741000: 3688568185 +740000: 3349738887 +739000: 1606411092 +738000: 331980874 +737000: 744409647 +736000: 3845688101 +735000: 3654026084 +734000: 786733128 +733000: 1938791337 +732000: 843210299 +731000: 622237260 +730000: 2851984401 +729000: 874906210 +728000: 485670931 +727000: 1522238607 +726000: 2167917076 +725000: 2304482464 +724000: 1053513779 +723000: 3535437378 +722000: 2842397393 +721000: 864490421 +720000: 920591184 +719000: 238249003 +718000: 400999105 +717000: 2476588521 +716000: 2501770197 +715000: 2307183887 +714000: 2461504446 +713000: 1055961242 +712000: 2112756603 +711000: 1691285107 +710000: 2318101701 +709000: 1113470660 +708000: 2880817109 +707000: 2105866601 +706000: 1441912219 +705000: 1684930572 +704000: 1652788290 +703000: 2359919145 +702000: 554008403 +701000: 3292620387 +700000: 3528106952 +699000: 3096375697 +698000: 4201459210 +697000: 1450879661 +696000: 3743939389 +695000: 3595614062 +694000: 4101634764 +693000: 364538097 +692000: 4204120947 +691000: 3706729229 +690000: 23134581 +689000: 2585120038 +688000: 488096133 +687000: 3437179533 +686000: 4233790378 +685000: 3093374794 +684000: 4054579709 +683000: 1275606548 +682000: 1966964511 +681000: 354765069 +680000: 3812578933 +679000: 781104418 +678000: 3281747368 +677000: 38547527 +676000: 1005246555 +675000: 74753563 +674000: 676561715 +673000: 1571462591 +672000: 1876054379 +671000: 1899005137 +670000: 4188106842 +669000: 1210903253 +668000: 2909261468 +667000: 3100970839 +666000: 758568698 +665000: 2456763236 +664000: 686978785 +663000: 349808361 +662000: 2804776250 +661000: 2660993423 +660000: 1758165672 +659000: 2116094507 +658000: 473425247 +657000: 563682488 +656000: 1454194093 +655000: 3211379305 +654000: 1298793267 +653000: 3374836733 +652000: 586356525 +651000: 1490379306 +650000: 2444980288 +649000: 47671514 +648000: 568687171 +647000: 452676234 +646000: 2752247721 +645000: 1473254180 +644000: 4189470166 +643000: 2619721788 +642000: 348627393 +641000: 675341258 +640000: 3183922211 +639000: 1266115377 +638000: 2331844572 +637000: 250721255 +636000: 4017517385 +635000: 1279621530 +634000: 1500904407 +633000: 2495457137 +632000: 1919479114 +631000: 1900388354 +630000: 370039669 +629000: 1207459690 +628000: 2314286843 +627000: 80099285 +626000: 2465533600 +625000: 1056979505 +624000: 4289445503 +623000: 1234007489 +622000: 2015973003 +621000: 2281387627 +620000: 1115405564 +619000: 1407699260 +618000: 3940256761 +617000: 3639431367 +616000: 3498942818 +615000: 2982957031 +614000: 3800830694 +613000: 1454837486 +612000: 158454584 +611000: 3414923339 +610000: 3752581462 +609000: 195868045 +608000: 3165948362 +607000: 2335822431 +606000: 3229210414 +605000: 1963422803 +604000: 2355005929 +603000: 2009365872 +602000: 1343084455 +601000: 2935056539 +600000: 2354171524 +599000: 3621510708 +598000: 3992266416 +597000: 682368260 +596000: 3290472265 +595000: 2215475388 +594000: 258049456 +593000: 365234760 +592000: 291875022 +591000: 3307168950 +590000: 2233802778 +589000: 1944100586 +588000: 7070250 +587000: 882601802 +586000: 1231725137 +585000: 4169259917 +584000: 2123453163 +583000: 631823798 +582000: 2039925673 +581000: 2238172862 +580000: 1479379031 +579000: 2363652063 +578000: 3186953219 +577000: 1893181853 +576000: 2598096173 +575000: 938779920 +574000: 927622241 +573000: 3105026014 +572000: 2412852365 +571000: 644810722 +570000: 3576393744 +569000: 2625468928 +568000: 2167447563 +567000: 3391359662 +566000: 3178493511 +565000: 24044406 +564000: 3298992941 +563000: 2054886551 +562000: 42479754 +561000: 2681525651 +560000: 1110769583 +559000: 2140540905 +558000: 780964175 +557000: 1320986796 +556000: 3624725635 +555000: 2920977559 +554000: 4017386186 +553000: 1800018968 +552000: 2137743255 +551000: 2282561617 +550000: 1466333871 +549000: 2567190002 +548000: 3280136825 +547000: 1761114084 +546000: 413841088 +545000: 829808286 +544000: 283842712 +543000: 3524860517 +542000: 1853927454 +541000: 3087398009 +540000: 2535138654 +539000: 2224833733 +538000: 1673737994 +537000: 3963575809 +536000: 289926670 +535000: 2411609896 +534000: 1866933324 +533000: 259728174 +532000: 786327819 +531000: 870136645 +530000: 3603849411 +529000: 1687141824 +528000: 2973109656 +527000: 2120372902 +526000: 3554894341 +525000: 369365218 +524000: 2336210870 +523000: 1352671703 +522000: 4093185231 +521000: 44309897 +520000: 1308207751 +519000: 1489447779 +518000: 497784082 +517000: 2370135551 +516000: 2393982064 +515000: 3453216376 +514000: 349616264 +513000: 1057922348 +512000: 2061823561 +511000: 2221803921 +510000: 2518047997 +509000: 2783356981 +508000: 3842023593 +507000: 3105321997 +506000: 3540124104 +505000: 334821209 +504000: 2867156116 +503000: 3824184936 +502000: 2432119674 +501000: 3759474841 +500000: 3381305904 +499000: 3106640260 +498000: 4241569809 +497000: 2499659818 +496000: 3971155346 +495000: 2297624439 +494000: 3455216298 +493000: 2152855317 +492000: 3915728702 +491000: 1087687366 +490000: 3976823873 +489000: 1813936857 +488000: 2803197060 +487000: 4026575712 +486000: 3867909271 +485000: 644795069 +484000: 1051897856 +483000: 3091023530 +482000: 558963440 +481000: 2516346710 +480000: 2405618228 +479000: 1595155902 +478000: 1699460683 +477000: 645434559 +476000: 1457238083 +475000: 101746166 +474000: 1054127445 +473000: 1703635926 +472000: 3228750510 +471000: 2570095523 +470000: 2671516672 +469000: 219569232 +468000: 245973042 +467000: 1785352151 +466000: 1828704556 +465000: 2993350381 +464000: 1802995474 +463000: 3689392931 +462000: 2612188341 +461000: 1970287287 +460000: 179729165 +459000: 1971694777 +458000: 3031333568 +457000: 844564594 +456000: 979968160 +455000: 2169589334 +454000: 2315813244 +453000: 2333801403 +452000: 27632567 +451000: 3752181065 +450000: 3965825733 +449000: 969798494 +448000: 1028884180 +447000: 1127216392 +446000: 2477366335 +445000: 3752023316 +444000: 1679036165 +443000: 4241934865 +442000: 3360200587 +441000: 3533494907 +440000: 1888455616 +439000: 2668699748 +438000: 2728196631 +437000: 31348508 +436000: 2192326452 +435000: 286955043 +434000: 4097630027 +433000: 1185622743 +432000: 2870795553 +431000: 2246074692 +430000: 14797454 +429000: 2606207217 +428000: 2143322684 +427000: 1289559127 +426000: 3922285071 +425000: 590638427 +424000: 1098669098 +423000: 1597510568 +422000: 1623191243 +421000: 558862770 +420000: 3846690181 +419000: 3187756225 +418000: 2520849981 +417000: 492022774 +416000: 1621927303 +415000: 2828836994 +414000: 2840605981 +413000: 4260845378 +412000: 2200645444 +411000: 393061550 +410000: 3334889686 +409000: 1926958198 +408000: 2939424440 +407000: 4207748941 +406000: 4155428743 +405000: 89797563 +404000: 427509452 +403000: 1154877029 +402000: 4023324583 +401000: 359413604 +400000: 964788206 +399000: 3843097093 +398000: 1871599521 +397000: 2361845870 +396000: 4103568192 +395000: 622493054 +394000: 954921337 +393000: 3664395297 +392000: 2429042528 +391000: 1361036260 +390000: 1944048082 +389000: 1452288555 +388000: 1619598577 +387000: 481096019 +386000: 3719595713 +385000: 1840199850 +384000: 421723640 +383000: 2976677668 +382000: 618336385 +381000: 1777037748 +380000: 901802032 +379000: 621392881 +378000: 3857241587 +377000: 3115040335 +376000: 3173790487 +375000: 2517831056 +374000: 4125976072 +373000: 2294107866 +372000: 4127359945 +371000: 333946663 +370000: 3307391606 +369000: 4268094300 +368000: 91056295 +367000: 882600429 +366000: 730521557 +365000: 3957048081 +364000: 2139992409 +363000: 3504327478 +362000: 2637042137 +361000: 2718540805 +360000: 903036675 +359000: 1858031956 +358000: 1868403889 +357000: 2677157063 +356000: 1865569815 +355000: 224528281 +354000: 3144318856 +353000: 1968806079 +352000: 2836077060 +351000: 1981309964 +350000: 3105869514 +349000: 3793296439 +348000: 1267294125 +347000: 1962520375 +346000: 2150839102 +345000: 3811064048 +344000: 1298671776 +343000: 2150950779 +342000: 3522997671 +341000: 1378798782 +340000: 2213936395 +339000: 2117978968 +338000: 2444486361 +337000: 3928234621 +336000: 1645335376 +335000: 540013781 +334000: 1103798645 +333000: 1723781016 +332000: 1805323374 +331000: 3590394804 +330000: 4178797476 +329000: 3350975600 +328000: 1556948383 +327000: 2282601074 +326000: 1709618426 +325000: 637957139 +324000: 2719080929 +323000: 1847444832 +322000: 547261068 +321000: 581409575 +320000: 586567018 +319000: 1579880779 +318000: 1049735969 +317000: 3233747918 +316000: 351376358 +315000: 3446473138 +314000: 2099035319 +313000: 2827833754 +312000: 2717063452 +311000: 2212978977 +310000: 1583494069 +309000: 3119642323 +308000: 2946038826 +307000: 167580491 +306000: 3916319765 +305000: 3480693946 +304000: 2709010304 +303000: 3265576420 +302000: 3439318492 +301000: 1896109937 +300000: 339896540 +299000: 313850585 +298000: 2600289987 +297000: 4060531515 +296000: 3894455718 +295000: 3183544633 +294000: 1551799240 +293000: 3574197425 +292000: 2380783887 +291000: 3130665581 +290000: 1135162832 +289000: 3460550191 +288000: 3366619355 +287000: 501626025 +286000: 1070097358 +285000: 1023235560 +284000: 925313877 +283000: 3758987940 +282000: 1935539406 +281000: 3727463323 +280000: 4040081802 +279000: 2462105177 +278000: 322183212 +277000: 2437872102 +276000: 1085894622 +275000: 2118601354 +274000: 1720719726 +273000: 56294175 +272000: 2046218040 +271000: 2871320919 +270000: 3111863367 +269000: 726835633 +268000: 916866344 +267000: 1208374677 +266000: 2914608557 +265000: 449456198 +264000: 2645640532 +263000: 997311800 +262000: 2872564998 +261000: 1964496124 +260000: 2802080932 +259000: 387636194 +258000: 3813984224 +257000: 1921258264 +256000: 1414333533 +255000: 997845727 +254000: 3671258247 +253000: 3244313331 +252000: 44297738 +251000: 1055697350 +250000: 403951609 +249000: 3558182356 +248000: 3441722116 +247000: 3598259825 +246000: 2495236386 +245000: 4150113079 +244000: 4092477475 +243000: 1352323466 +242000: 4228179784 +241000: 3509286314 +240000: 1117669666 +239000: 1821539001 +238000: 2685425558 +237000: 3282158412 +236000: 976807931 +235000: 1960913234 +234000: 675404937 +233000: 2016845981 +232000: 3778769531 +231000: 1321297859 +230000: 84609577 +229000: 2736973360 +228000: 1143462599 +227000: 1152334102 +226000: 2661675401 +225000: 3384049744 +224000: 3321570349 +223000: 2151575803 +222000: 2950365334 +221000: 2791341163 +220000: 2912181889 +219000: 700726300 +218000: 3236687629 +217000: 384678680 +216000: 3027284798 +215000: 2124466541 +214000: 1634885735 +213000: 3025139089 +212000: 1913485355 +211000: 2451444114 +210000: 1597224573 +209000: 2863042887 +208000: 1462999033 +207000: 853998677 +206000: 1532111742 +205000: 3533822378 +204000: 1057056422 +203000: 2585913344 +202000: 1776380902 +201000: 2652271540 +200000: 2500553547 +199000: 3943435104 +198000: 615742187 +197000: 2089667313 +196000: 1649690458 +195000: 582691711 +194000: 1197398266 +193000: 2682453813 +192000: 1739971049 +191000: 1543584807 +190000: 4224852565 +189000: 2330603128 +188000: 2738873539 +187000: 2462336661 +186000: 538134005 +185000: 618406175 +184000: 3258203829 +183000: 3565635398 +182000: 2437456159 +181000: 1103703144 +180000: 3142082412 +179000: 3635072449 +178000: 2831183465 +177000: 3067391696 +176000: 4243880329 +175000: 3847103503 +174000: 1886736895 +173000: 3994782354 +172000: 2180961421 +171000: 2657714328 +170000: 1783032069 +169000: 3288794122 +168000: 4214505744 +167000: 3893811403 +166000: 301673242 +165000: 1008606441 +164000: 4241744599 +163000: 4077366883 +162000: 947408771 +161000: 2893412067 +160000: 4239854096 +159000: 837488883 +158000: 1035341013 +157000: 2979612216 +156000: 622879904 +155000: 2239033946 +154000: 1793603359 +153000: 3403674755 +152000: 1757769702 +151000: 3104338771 +150000: 4050901279 +149000: 1064027760 +148000: 1232980113 +147000: 1940798204 +146000: 1520506974 +145000: 1602654645 +144000: 3827165041 +143000: 2333560581 +142000: 1078945096 +141000: 4164769913 +140000: 1004088705 +139000: 1918334274 +138000: 2376094733 +137000: 2114404244 +136000: 610887654 +135000: 2061314834 +134000: 2934949429 +133000: 1384359308 +132000: 2214638498 +131000: 4091637905 +130000: 1178600936 +129000: 3673332079 +128000: 335936353 +127000: 1680711257 +126000: 1535342908 +125000: 1797602927 +124000: 1277174958 +123000: 3114077321 +122000: 149498793 +121000: 864366602 +120000: 104510626 +119000: 1518395286 +118000: 3111302078 +117000: 3110116836 +116000: 3233967498 +115000: 1017896311 +114000: 692827001 +113000: 3779537224 +112000: 2905474934 +111000: 3465999202 +110000: 1915694049 +109000: 2628022627 +108000: 875271541 +107000: 2022225002 +106000: 1671971011 +105000: 3334748297 +104000: 1332184097 +103000: 1555681497 +102000: 3406253965 +101000: 4045141299 +100000: 3058680000 +99000: 555036606 +98000: 46275609 +97000: 3853135904 +96000: 4229006385 +95000: 4108164708 +94000: 2566945975 +93000: 3797900910 +92000: 3355992329 +91000: 1635484145 +90000: 1382023482 +89000: 3690432221 +88000: 1892056918 +87000: 1120722079 +86000: 2675052236 +85000: 4165748502 +84000: 10230467 +83000: 4138070209 +82000: 1570296924 +81000: 3126342757 +80000: 598265835 +79000: 541475291 +78000: 2784920265 +77000: 4169891577 +76000: 1101249184 +75000: 2090307927 +74000: 3780559777 +73000: 19873425 +72000: 1118190767 +71000: 3485912405 +70000: 1322638834 +69000: 1096526516 +68000: 1370553703 +67000: 3631120381 +66000: 1806420191 +65000: 2701118072 +64000: 483879470 +63000: 2124403158 +62000: 1877513812 +61000: 1289006766 +60000: 3733667461 +59000: 3457358686 +58000: 732502949 +57000: 3971773677 +56000: 883589946 +55000: 290212168 +54000: 2244967385 +53000: 3848247179 +52000: 2228476206 +51000: 2372703555 +50000: 1200411530 +49000: 2060190456 +48000: 2511902942 +47000: 4007272287 +46000: 2854231300 +45000: 2518671311 +44000: 815143404 +43000: 1972543143 +42000: 3063716128 +41000: 3326571310 +40000: 3180391453 +39000: 2568545510 +38000: 573110821 +37000: 3814257324 +36000: 4163248735 +35000: 943584186 +34000: 387069186 +33000: 3519377243 +32000: 3861206003 +31000: 2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 +Exiting @ tick 922809447000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..6f84a3553 --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2704949 # Simulator instruction rate (inst/s) +host_mem_usage 202656 # Number of bytes of host memory used +host_seconds 680.13 # Real time elapsed on the host +host_tick_rate 1356804201 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1839728999 # Number of instructions simulated +sim_seconds 0.922809 # Number of seconds simulated +sim_ticks 922809447000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1845618895 # number of cpu cycles simulated +system.cpu.num_insts 1839728999 # Number of instructions executed +system.cpu.num_refs 908401146 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..406381ed3 --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..805a6606f --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: fcntl64(3, 2) passed through to host +For more information see: http://www.m5sim.org/warn/a55e2c46 +hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..55aff9333 --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -0,0 +1,1393 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:56:56 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 3428045644 +1332000: 2815822229 +1331000: 1093465585 +1330000: 3012217108 +1329000: 2230916791 +1328000: 208547885 +1327000: 3592585825 +1326000: 3948677052 +1325000: 1817805162 +1324000: 135366494 +1323000: 3309148112 +1322000: 1685035744 +1321000: 3293068577 +1320000: 4097808567 +1319000: 1594097274 +1318000: 2607196971 +1317000: 1763785306 +1316000: 2157394178 +1315000: 2399031328 +1314000: 2954547004 +1313000: 82348686 +1312000: 3120930785 +1311000: 2192747320 +1310000: 1580299400 +1309000: 4085061477 +1308000: 3627048345 +1307000: 3756533178 +1306000: 77997329 +1305000: 1343359499 +1304000: 1124031730 +1303000: 1161755432 +1302000: 1855858423 +1301000: 3985872257 +1300000: 3188250811 +1299000: 3621615933 +1298000: 962624248 +1297000: 447138785 +1296000: 1459144309 +1295000: 3454504226 +1294000: 2154913347 +1293000: 2356291788 +1292000: 458348817 +1291000: 3639562699 +1290000: 3596847973 +1289000: 117168222 +1288000: 3531023849 +1287000: 3135920051 +1286000: 234987844 +1285000: 2048767180 +1284000: 2437301839 +1283000: 522886780 +1282000: 2274133042 +1281000: 1415703448 +1280000: 4145574054 +1279000: 4283494580 +1278000: 3305365779 +1277000: 604711974 +1276000: 2031548723 +1275000: 1809515149 +1274000: 1664703088 +1273000: 4149809153 +1272000: 4045608138 +1271000: 1687605659 +1270000: 1292294527 +1269000: 3120968162 +1268000: 3502898850 +1267000: 371380256 +1266000: 1683884245 +1265000: 1849576817 +1264000: 1559050991 +1263000: 66820972 +1262000: 4023539201 +1261000: 3452295398 +1260000: 4188778026 +1259000: 2008091854 +1258000: 2691158394 +1257000: 2030818206 +1256000: 2715523403 +1255000: 3473414015 +1254000: 138826953 +1253000: 69386516 +1252000: 1174725971 +1251000: 4130510373 +1250000: 1649788328 +1249000: 1589122801 +1248000: 1108688101 +1247000: 2906355484 +1246000: 379539929 +1245000: 914026021 +1244000: 4074858468 +1243000: 505989635 +1242000: 2487288773 +1241000: 1991248111 +1240000: 2415456875 +1239000: 2571192525 +1238000: 2897090536 +1237000: 2761178989 +1236000: 1296601829 +1235000: 594696756 +1234000: 264562726 +1233000: 3630852367 +1232000: 1605618457 +1231000: 2857419452 +1230000: 3028672437 +1229000: 361833758 +1228000: 4046013938 +1227000: 1031775583 +1226000: 3475227831 +1225000: 802168737 +1224000: 3819194009 +1223000: 851157666 +1222000: 2656457905 +1221000: 2579045204 +1220000: 2091024410 +1219000: 4070633834 +1218000: 1926611791 +1217000: 1903813761 +1216000: 3107168794 +1215000: 2975081979 +1214000: 4097089273 +1213000: 328943233 +1212000: 2912404803 +1211000: 181334180 +1210000: 863898367 +1209000: 1894902343 +1208000: 1531985231 +1207000: 1412503751 +1206000: 662457490 +1205000: 3447925432 +1204000: 2320889638 +1203000: 303282255 +1202000: 1568632659 +1201000: 1108711074 +1200000: 953936964 +1199000: 3576987258 +1198000: 466163300 +1197000: 1159551420 +1196000: 529807534 +1195000: 1528979627 +1194000: 1795576953 +1193000: 2050917610 +1192000: 4068219994 +1191000: 3573497288 +1190000: 776005286 +1189000: 2643125982 +1188000: 2240857507 +1187000: 43353719 +1186000: 2474198261 +1185000: 1711347056 +1184000: 3046018343 +1183000: 664346074 +1182000: 3532392595 +1181000: 3145347726 +1180000: 2203928246 +1179000: 4275910811 +1178000: 3260065240 +1177000: 3216083720 +1176000: 3588515377 +1175000: 1432542416 +1174000: 173159992 +1173000: 4115057268 +1172000: 223456174 +1171000: 1192164227 +1170000: 2059254624 +1169000: 279921804 +1168000: 1100495449 +1167000: 264813624 +1166000: 2839280440 +1165000: 301796904 +1164000: 1331933822 +1163000: 647427882 +1162000: 3872813324 +1161000: 2231068824 +1160000: 4222672618 +1159000: 3629229584 +1158000: 2262586804 +1157000: 2837951671 +1156000: 1780662312 +1155000: 31553143 +1154000: 3230861653 +1153000: 1991458597 +1152000: 2277829165 +1151000: 3864184029 +1150000: 630158826 +1149000: 4028889917 +1148000: 1662505287 +1147000: 4121796538 +1146000: 3215277282 +1145000: 2019794999 +1144000: 4124433286 +1143000: 181819953 +1142000: 2704380222 +1141000: 2487909897 +1140000: 1753570204 +1139000: 2337507591 +1138000: 3235449912 +1137000: 3819353806 +1136000: 3435413746 +1135000: 3288196653 +1134000: 2705083758 +1133000: 997301031 +1132000: 1871866706 +1131000: 2298991521 +1130000: 1516060457 +1129000: 3393393053 +1128000: 2795526466 +1127000: 1177801041 +1126000: 4226698729 +1125000: 567826718 +1124000: 2425735007 +1123000: 1090360485 +1122000: 2508061782 +1121000: 3476086116 +1120000: 2952087827 +1119000: 2238445545 +1118000: 2937037425 +1117000: 1773353797 +1116000: 3033333765 +1115000: 3086246055 +1114000: 944390435 +1113000: 2944932895 +1112000: 534683663 +1111000: 2002175399 +1110000: 1876265996 +1109000: 4148000592 +1108000: 3857174625 +1107000: 843045539 +1106000: 307772960 +1105000: 4161975075 +1104000: 3675447412 +1103000: 1232242543 +1102000: 1019583281 +1101000: 1983565552 +1100000: 2490901544 +1099000: 2990982808 +1098000: 1586955629 +1097000: 1629138000 +1096000: 1870655270 +1095000: 2201093764 +1094000: 696079363 +1093000: 1526904315 +1092000: 553848190 +1091000: 4234411636 +1090000: 1027439894 +1089000: 1319115149 +1088000: 1147708285 +1087000: 3364503693 +1086000: 528432422 +1085000: 3289100476 +1084000: 3074065438 +1083000: 3664250869 +1082000: 2950591670 +1081000: 4207904839 +1080000: 3425353965 +1079000: 1069646286 +1078000: 1004956209 +1077000: 2642475281 +1076000: 364759474 +1075000: 2334969932 +1074000: 3907002684 +1073000: 273633783 +1072000: 4113182592 +1071000: 1404306188 +1070000: 3286171051 +1069000: 3531039414 +1068000: 4147513318 +1067000: 2466290219 +1066000: 2089005579 +1065000: 2617563073 +1064000: 3124838472 +1063000: 3731008114 +1062000: 4154022628 +1061000: 3389258714 +1060000: 3915149371 +1059000: 2280932986 +1058000: 2872952978 +1057000: 2381277834 +1056000: 1236179469 +1055000: 3256417375 +1054000: 2700213407 +1053000: 3418122897 +1052000: 3130247908 +1051000: 1897033028 +1050000: 2349143738 +1049000: 3789736749 +1048000: 409522147 +1047000: 3149279018 +1046000: 1323133366 +1045000: 3881472077 +1044000: 3363874422 +1043000: 3931657349 +1042000: 1220007174 +1041000: 3634450249 +1040000: 695184634 +1039000: 529508167 +1038000: 449827627 +1037000: 2817424280 +1036000: 1613482057 +1035000: 2632612792 +1034000: 852422020 +1033000: 4098325966 +1032000: 177298753 +1031000: 2286807874 +1030000: 2745349553 +1029000: 2387386570 +1028000: 2004317534 +1027000: 971343564 +1026000: 1583732447 +1025000: 2340780818 +1024000: 561110245 +1023000: 3012020895 +1022000: 1677066870 +1021000: 3046208682 +1020000: 2695506079 +1019000: 780536149 +1018000: 4225713741 +1017000: 420500410 +1016000: 3642094643 +1015000: 608695027 +1014000: 2161592269 +1013000: 930784800 +1012000: 1924051276 +1011000: 1889733886 +1010000: 1476038251 +1009000: 2908577467 +1008000: 2584082136 +1007000: 1713214537 +1006000: 3374346754 +1005000: 1173203719 +1004000: 1142288559 +1003000: 4195961973 +1002000: 1211260974 +1001000: 474231127 +1000000: 3967090782 +999000: 1543103493 +998000: 1018646803 +997000: 1799037982 +996000: 3416426509 +995000: 3581729971 +994000: 3044504127 +993000: 2975704335 +992000: 280018795 +991000: 330300280 +990000: 3557016064 +989000: 3856724468 +988000: 2124201285 +987000: 3683893247 +986000: 3331663795 +985000: 1980057740 +984000: 2908437859 +983000: 4074086941 +982000: 1162307093 +981000: 3855413476 +980000: 2799155731 +979000: 2477822501 +978000: 497762075 +977000: 1650233426 +976000: 3061573902 +975000: 2224673611 +974000: 868725340 +973000: 1630206962 +972000: 2549398924 +971000: 602424332 +970000: 1172502721 +969000: 2923795552 +968000: 1394164637 +967000: 1088479837 +966000: 898709052 +965000: 3983150961 +964000: 2463803866 +963000: 4181117626 +962000: 2151137820 +961000: 1342513757 +960000: 1507689687 +959000: 3652624918 +958000: 4169721124 +957000: 531022334 +956000: 3161389505 +955000: 1197637232 +954000: 2927231791 +953000: 2552305374 +952000: 2988512039 +951000: 2448639370 +950000: 3560951660 +949000: 948988399 +948000: 2488188856 +947000: 2804177113 +946000: 1991587461 +945000: 2480044082 +944000: 1954588624 +943000: 924231798 +942000: 3269047595 +941000: 2078696579 +940000: 2822989969 +939000: 2295885951 +938000: 1815612561 +937000: 4182254074 +936000: 2753223967 +935000: 2840201908 +934000: 4058383142 +933000: 4270167260 +932000: 1203124158 +931000: 3039861400 +930000: 4247472610 +929000: 2297661055 +928000: 2376159704 +927000: 3861417958 +926000: 1968685250 +925000: 1156966624 +924000: 3568580529 +923000: 866582344 +922000: 2263113297 +921000: 3643523016 +920000: 3252268544 +919000: 2413309783 +918000: 3463124619 +917000: 3965291932 +916000: 1309181143 +915000: 2321282614 +914000: 2286584604 +913000: 3271924727 +912000: 1719841316 +911000: 3966124343 +910000: 607707072 +909000: 61942114 +908000: 903881820 +907000: 4136948835 +906000: 3663861210 +905000: 3251888710 +904000: 227984688 +903000: 495030333 +902000: 863290992 +901000: 3297482717 +900000: 3821175085 +899000: 1679874522 +898000: 2033358728 +897000: 3495513776 +896000: 1613181881 +895000: 1729312232 +894000: 2171317375 +893000: 2508603694 +892000: 151095866 +891000: 1926096901 +890000: 4292888210 +889000: 2716307666 +888000: 737310728 +887000: 4172392976 +886000: 2322084662 +885000: 1034961047 +884000: 665072958 +883000: 368014441 +882000: 1914585160 +881000: 3836900884 +880000: 2073827187 +879000: 1650543625 +878000: 3581099222 +877000: 147580905 +876000: 4009421518 +875000: 3294244820 +874000: 2786720968 +873000: 1682434702 +872000: 620473876 +871000: 742752376 +870000: 385116650 +869000: 3882475387 +868000: 4259210265 +867000: 1329675866 +866000: 539876515 +865000: 2761681036 +864000: 2192063038 +863000: 1512848001 +862000: 3911973718 +861000: 399349760 +860000: 1449497249 +859000: 4241714042 +858000: 18611709 +857000: 1550083097 +856000: 3322762748 +855000: 283796511 +854000: 227907270 +853000: 3162559866 +852000: 1331946455 +851000: 2328467927 +850000: 1640242501 +849000: 3390154083 +848000: 22088346 +847000: 636412590 +846000: 1550672808 +845000: 763937899 +844000: 430123910 +843000: 3413971543 +842000: 900018421 +841000: 3295874222 +840000: 2470678073 +839000: 821401909 +838000: 3923898844 +837000: 429069328 +836000: 2030779868 +835000: 464625222 +834000: 3593024182 +833000: 3564354808 +832000: 2794783695 +831000: 97817593 +830000: 4197446076 +829000: 2367560230 +828000: 2180262123 +827000: 3149571964 +826000: 1364436763 +825000: 21599634 +824000: 448490256 +823000: 3775294409 +822000: 1132631425 +821000: 2046352434 +820000: 3380435217 +819000: 3672496486 +818000: 1634548077 +817000: 2881316258 +816000: 1808599559 +815000: 3298310748 +814000: 3744285741 +813000: 3540737709 +812000: 1143844515 +811000: 3091026783 +810000: 3771757792 +809000: 631375816 +808000: 1353831646 +807000: 3047756240 +806000: 818136890 +805000: 783072818 +804000: 3923416267 +803000: 3233085529 +802000: 674747602 +801000: 758523180 +800000: 2232308489 +799000: 2919643710 +798000: 623631722 +797000: 1302202741 +796000: 1083055596 +795000: 2358048936 +794000: 2836842068 +793000: 1612571734 +792000: 4243459584 +791000: 1585511173 +790000: 1493369943 +789000: 3649557715 +788000: 3223859588 +787000: 4001130195 +786000: 2949323631 +785000: 3887611007 +784000: 4091766333 +783000: 2954277998 +782000: 1281850218 +781000: 771664458 +780000: 2242576209 +779000: 3865479146 +778000: 1885013114 +777000: 2032659742 +776000: 4221167450 +775000: 1962824751 +774000: 209539683 +773000: 262945027 +772000: 452388820 +771000: 2006266573 +770000: 990063860 +769000: 1377951885 +768000: 4240978277 +767000: 2206801004 +766000: 258015097 +765000: 1990217201 +764000: 1336410303 +763000: 1004853228 +762000: 1404152873 +761000: 3356554358 +760000: 4052430907 +759000: 2833671166 +758000: 1561723151 +757000: 1752620777 +756000: 2622547462 +755000: 1843933196 +754000: 3728801998 +753000: 2776832730 +752000: 2626131293 +751000: 1528525830 +750000: 2716112581 +749000: 3306039713 +748000: 915271993 +747000: 4205133363 +746000: 3136321783 +745000: 1203154793 +744000: 3370017183 +743000: 4036456207 +742000: 3377556743 +741000: 3688568185 +740000: 3349738887 +739000: 1606411092 +738000: 331980874 +737000: 744409647 +736000: 3845688101 +735000: 3654026084 +734000: 786733128 +733000: 1938791337 +732000: 843210299 +731000: 622237260 +730000: 2851984401 +729000: 874906210 +728000: 485670931 +727000: 1522238607 +726000: 2167917076 +725000: 2304482464 +724000: 1053513779 +723000: 3535437378 +722000: 2842397393 +721000: 864490421 +720000: 920591184 +719000: 238249003 +718000: 400999105 +717000: 2476588521 +716000: 2501770197 +715000: 2307183887 +714000: 2461504446 +713000: 1055961242 +712000: 2112756603 +711000: 1691285107 +710000: 2318101701 +709000: 1113470660 +708000: 2880817109 +707000: 2105866601 +706000: 1441912219 +705000: 1684930572 +704000: 1652788290 +703000: 2359919145 +702000: 554008403 +701000: 3292620387 +700000: 3528106952 +699000: 3096375697 +698000: 4201459210 +697000: 1450879661 +696000: 3743939389 +695000: 3595614062 +694000: 4101634764 +693000: 364538097 +692000: 4204120947 +691000: 3706729229 +690000: 23134581 +689000: 2585120038 +688000: 488096133 +687000: 3437179533 +686000: 4233790378 +685000: 3093374794 +684000: 4054579709 +683000: 1275606548 +682000: 1966964511 +681000: 354765069 +680000: 3812578933 +679000: 781104418 +678000: 3281747368 +677000: 38547527 +676000: 1005246555 +675000: 74753563 +674000: 676561715 +673000: 1571462591 +672000: 1876054379 +671000: 1899005137 +670000: 4188106842 +669000: 1210903253 +668000: 2909261468 +667000: 3100970839 +666000: 758568698 +665000: 2456763236 +664000: 686978785 +663000: 349808361 +662000: 2804776250 +661000: 2660993423 +660000: 1758165672 +659000: 2116094507 +658000: 473425247 +657000: 563682488 +656000: 1454194093 +655000: 3211379305 +654000: 1298793267 +653000: 3374836733 +652000: 586356525 +651000: 1490379306 +650000: 2444980288 +649000: 47671514 +648000: 568687171 +647000: 452676234 +646000: 2752247721 +645000: 1473254180 +644000: 4189470166 +643000: 2619721788 +642000: 348627393 +641000: 675341258 +640000: 3183922211 +639000: 1266115377 +638000: 2331844572 +637000: 250721255 +636000: 4017517385 +635000: 1279621530 +634000: 1500904407 +633000: 2495457137 +632000: 1919479114 +631000: 1900388354 +630000: 370039669 +629000: 1207459690 +628000: 2314286843 +627000: 80099285 +626000: 2465533600 +625000: 1056979505 +624000: 4289445503 +623000: 1234007489 +622000: 2015973003 +621000: 2281387627 +620000: 1115405564 +619000: 1407699260 +618000: 3940256761 +617000: 3639431367 +616000: 3498942818 +615000: 2982957031 +614000: 3800830694 +613000: 1454837486 +612000: 158454584 +611000: 3414923339 +610000: 3752581462 +609000: 195868045 +608000: 3165948362 +607000: 2335822431 +606000: 3229210414 +605000: 1963422803 +604000: 2355005929 +603000: 2009365872 +602000: 1343084455 +601000: 2935056539 +600000: 2354171524 +599000: 3621510708 +598000: 3992266416 +597000: 682368260 +596000: 3290472265 +595000: 2215475388 +594000: 258049456 +593000: 365234760 +592000: 291875022 +591000: 3307168950 +590000: 2233802778 +589000: 1944100586 +588000: 7070250 +587000: 882601802 +586000: 1231725137 +585000: 4169259917 +584000: 2123453163 +583000: 631823798 +582000: 2039925673 +581000: 2238172862 +580000: 1479379031 +579000: 2363652063 +578000: 3186953219 +577000: 1893181853 +576000: 2598096173 +575000: 938779920 +574000: 927622241 +573000: 3105026014 +572000: 2412852365 +571000: 644810722 +570000: 3576393744 +569000: 2625468928 +568000: 2167447563 +567000: 3391359662 +566000: 3178493511 +565000: 24044406 +564000: 3298992941 +563000: 2054886551 +562000: 42479754 +561000: 2681525651 +560000: 1110769583 +559000: 2140540905 +558000: 780964175 +557000: 1320986796 +556000: 3624725635 +555000: 2920977559 +554000: 4017386186 +553000: 1800018968 +552000: 2137743255 +551000: 2282561617 +550000: 1466333871 +549000: 2567190002 +548000: 3280136825 +547000: 1761114084 +546000: 413841088 +545000: 829808286 +544000: 283842712 +543000: 3524860517 +542000: 1853927454 +541000: 3087398009 +540000: 2535138654 +539000: 2224833733 +538000: 1673737994 +537000: 3963575809 +536000: 289926670 +535000: 2411609896 +534000: 1866933324 +533000: 259728174 +532000: 786327819 +531000: 870136645 +530000: 3603849411 +529000: 1687141824 +528000: 2973109656 +527000: 2120372902 +526000: 3554894341 +525000: 369365218 +524000: 2336210870 +523000: 1352671703 +522000: 4093185231 +521000: 44309897 +520000: 1308207751 +519000: 1489447779 +518000: 497784082 +517000: 2370135551 +516000: 2393982064 +515000: 3453216376 +514000: 349616264 +513000: 1057922348 +512000: 2061823561 +511000: 2221803921 +510000: 2518047997 +509000: 2783356981 +508000: 3842023593 +507000: 3105321997 +506000: 3540124104 +505000: 334821209 +504000: 2867156116 +503000: 3824184936 +502000: 2432119674 +501000: 3759474841 +500000: 3381305904 +499000: 3106640260 +498000: 4241569809 +497000: 2499659818 +496000: 3971155346 +495000: 2297624439 +494000: 3455216298 +493000: 2152855317 +492000: 3915728702 +491000: 1087687366 +490000: 3976823873 +489000: 1813936857 +488000: 2803197060 +487000: 4026575712 +486000: 3867909271 +485000: 644795069 +484000: 1051897856 +483000: 3091023530 +482000: 558963440 +481000: 2516346710 +480000: 2405618228 +479000: 1595155902 +478000: 1699460683 +477000: 645434559 +476000: 1457238083 +475000: 101746166 +474000: 1054127445 +473000: 1703635926 +472000: 3228750510 +471000: 2570095523 +470000: 2671516672 +469000: 219569232 +468000: 245973042 +467000: 1785352151 +466000: 1828704556 +465000: 2993350381 +464000: 1802995474 +463000: 3689392931 +462000: 2612188341 +461000: 1970287287 +460000: 179729165 +459000: 1971694777 +458000: 3031333568 +457000: 844564594 +456000: 979968160 +455000: 2169589334 +454000: 2315813244 +453000: 2333801403 +452000: 27632567 +451000: 3752181065 +450000: 3965825733 +449000: 969798494 +448000: 1028884180 +447000: 1127216392 +446000: 2477366335 +445000: 3752023316 +444000: 1679036165 +443000: 4241934865 +442000: 3360200587 +441000: 3533494907 +440000: 1888455616 +439000: 2668699748 +438000: 2728196631 +437000: 31348508 +436000: 2192326452 +435000: 286955043 +434000: 4097630027 +433000: 1185622743 +432000: 2870795553 +431000: 2246074692 +430000: 14797454 +429000: 2606207217 +428000: 2143322684 +427000: 1289559127 +426000: 3922285071 +425000: 590638427 +424000: 1098669098 +423000: 1597510568 +422000: 1623191243 +421000: 558862770 +420000: 3846690181 +419000: 3187756225 +418000: 2520849981 +417000: 492022774 +416000: 1621927303 +415000: 2828836994 +414000: 2840605981 +413000: 4260845378 +412000: 2200645444 +411000: 393061550 +410000: 3334889686 +409000: 1926958198 +408000: 2939424440 +407000: 4207748941 +406000: 4155428743 +405000: 89797563 +404000: 427509452 +403000: 1154877029 +402000: 4023324583 +401000: 359413604 +400000: 964788206 +399000: 3843097093 +398000: 1871599521 +397000: 2361845870 +396000: 4103568192 +395000: 622493054 +394000: 954921337 +393000: 3664395297 +392000: 2429042528 +391000: 1361036260 +390000: 1944048082 +389000: 1452288555 +388000: 1619598577 +387000: 481096019 +386000: 3719595713 +385000: 1840199850 +384000: 421723640 +383000: 2976677668 +382000: 618336385 +381000: 1777037748 +380000: 901802032 +379000: 621392881 +378000: 3857241587 +377000: 3115040335 +376000: 3173790487 +375000: 2517831056 +374000: 4125976072 +373000: 2294107866 +372000: 4127359945 +371000: 333946663 +370000: 3307391606 +369000: 4268094300 +368000: 91056295 +367000: 882600429 +366000: 730521557 +365000: 3957048081 +364000: 2139992409 +363000: 3504327478 +362000: 2637042137 +361000: 2718540805 +360000: 903036675 +359000: 1858031956 +358000: 1868403889 +357000: 2677157063 +356000: 1865569815 +355000: 224528281 +354000: 3144318856 +353000: 1968806079 +352000: 2836077060 +351000: 1981309964 +350000: 3105869514 +349000: 3793296439 +348000: 1267294125 +347000: 1962520375 +346000: 2150839102 +345000: 3811064048 +344000: 1298671776 +343000: 2150950779 +342000: 3522997671 +341000: 1378798782 +340000: 2213936395 +339000: 2117978968 +338000: 2444486361 +337000: 3928234621 +336000: 1645335376 +335000: 540013781 +334000: 1103798645 +333000: 1723781016 +332000: 1805323374 +331000: 3590394804 +330000: 4178797476 +329000: 3350975600 +328000: 1556948383 +327000: 2282601074 +326000: 1709618426 +325000: 637957139 +324000: 2719080929 +323000: 1847444832 +322000: 547261068 +321000: 581409575 +320000: 586567018 +319000: 1579880779 +318000: 1049735969 +317000: 3233747918 +316000: 351376358 +315000: 3446473138 +314000: 2099035319 +313000: 2827833754 +312000: 2717063452 +311000: 2212978977 +310000: 1583494069 +309000: 3119642323 +308000: 2946038826 +307000: 167580491 +306000: 3916319765 +305000: 3480693946 +304000: 2709010304 +303000: 3265576420 +302000: 3439318492 +301000: 1896109937 +300000: 339896540 +299000: 313850585 +298000: 2600289987 +297000: 4060531515 +296000: 3894455718 +295000: 3183544633 +294000: 1551799240 +293000: 3574197425 +292000: 2380783887 +291000: 3130665581 +290000: 1135162832 +289000: 3460550191 +288000: 3366619355 +287000: 501626025 +286000: 1070097358 +285000: 1023235560 +284000: 925313877 +283000: 3758987940 +282000: 1935539406 +281000: 3727463323 +280000: 4040081802 +279000: 2462105177 +278000: 322183212 +277000: 2437872102 +276000: 1085894622 +275000: 2118601354 +274000: 1720719726 +273000: 56294175 +272000: 2046218040 +271000: 2871320919 +270000: 3111863367 +269000: 726835633 +268000: 916866344 +267000: 1208374677 +266000: 2914608557 +265000: 449456198 +264000: 2645640532 +263000: 997311800 +262000: 2872564998 +261000: 1964496124 +260000: 2802080932 +259000: 387636194 +258000: 3813984224 +257000: 1921258264 +256000: 1414333533 +255000: 997845727 +254000: 3671258247 +253000: 3244313331 +252000: 44297738 +251000: 1055697350 +250000: 403951609 +249000: 3558182356 +248000: 3441722116 +247000: 3598259825 +246000: 2495236386 +245000: 4150113079 +244000: 4092477475 +243000: 1352323466 +242000: 4228179784 +241000: 3509286314 +240000: 1117669666 +239000: 1821539001 +238000: 2685425558 +237000: 3282158412 +236000: 976807931 +235000: 1960913234 +234000: 675404937 +233000: 2016845981 +232000: 3778769531 +231000: 1321297859 +230000: 84609577 +229000: 2736973360 +228000: 1143462599 +227000: 1152334102 +226000: 2661675401 +225000: 3384049744 +224000: 3321570349 +223000: 2151575803 +222000: 2950365334 +221000: 2791341163 +220000: 2912181889 +219000: 700726300 +218000: 3236687629 +217000: 384678680 +216000: 3027284798 +215000: 2124466541 +214000: 1634885735 +213000: 3025139089 +212000: 1913485355 +211000: 2451444114 +210000: 1597224573 +209000: 2863042887 +208000: 1462999033 +207000: 853998677 +206000: 1532111742 +205000: 3533822378 +204000: 1057056422 +203000: 2585913344 +202000: 1776380902 +201000: 2652271540 +200000: 2500553547 +199000: 3943435104 +198000: 615742187 +197000: 2089667313 +196000: 1649690458 +195000: 582691711 +194000: 1197398266 +193000: 2682453813 +192000: 1739971049 +191000: 1543584807 +190000: 4224852565 +189000: 2330603128 +188000: 2738873539 +187000: 2462336661 +186000: 538134005 +185000: 618406175 +184000: 3258203829 +183000: 3565635398 +182000: 2437456159 +181000: 1103703144 +180000: 3142082412 +179000: 3635072449 +178000: 2831183465 +177000: 3067391696 +176000: 4243880329 +175000: 3847103503 +174000: 1886736895 +173000: 3994782354 +172000: 2180961421 +171000: 2657714328 +170000: 1783032069 +169000: 3288794122 +168000: 4214505744 +167000: 3893811403 +166000: 301673242 +165000: 1008606441 +164000: 4241744599 +163000: 4077366883 +162000: 947408771 +161000: 2893412067 +160000: 4239854096 +159000: 837488883 +158000: 1035341013 +157000: 2979612216 +156000: 622879904 +155000: 2239033946 +154000: 1793603359 +153000: 3403674755 +152000: 1757769702 +151000: 3104338771 +150000: 4050901279 +149000: 1064027760 +148000: 1232980113 +147000: 1940798204 +146000: 1520506974 +145000: 1602654645 +144000: 3827165041 +143000: 2333560581 +142000: 1078945096 +141000: 4164769913 +140000: 1004088705 +139000: 1918334274 +138000: 2376094733 +137000: 2114404244 +136000: 610887654 +135000: 2061314834 +134000: 2934949429 +133000: 1384359308 +132000: 2214638498 +131000: 4091637905 +130000: 1178600936 +129000: 3673332079 +128000: 335936353 +127000: 1680711257 +126000: 1535342908 +125000: 1797602927 +124000: 1277174958 +123000: 3114077321 +122000: 149498793 +121000: 864366602 +120000: 104510626 +119000: 1518395286 +118000: 3111302078 +117000: 3110116836 +116000: 3233967498 +115000: 1017896311 +114000: 692827001 +113000: 3779537224 +112000: 2905474934 +111000: 3465999202 +110000: 1915694049 +109000: 2628022627 +108000: 875271541 +107000: 2022225002 +106000: 1671971011 +105000: 3334748297 +104000: 1332184097 +103000: 1555681497 +102000: 3406253965 +101000: 4045141299 +100000: 3058680000 +99000: 555036606 +98000: 46275609 +97000: 3853135904 +96000: 4229006385 +95000: 4108164708 +94000: 2566945975 +93000: 3797900910 +92000: 3355992329 +91000: 1635484145 +90000: 1382023482 +89000: 3690432221 +88000: 1892056918 +87000: 1120722079 +86000: 2675052236 +85000: 4165748502 +84000: 10230467 +83000: 4138070209 +82000: 1570296924 +81000: 3126342757 +80000: 598265835 +79000: 541475291 +78000: 2784920265 +77000: 4169891577 +76000: 1101249184 +75000: 2090307927 +74000: 3780559777 +73000: 19873425 +72000: 1118190767 +71000: 3485912405 +70000: 1322638834 +69000: 1096526516 +68000: 1370553703 +67000: 3631120381 +66000: 1806420191 +65000: 2701118072 +64000: 483879470 +63000: 2124403158 +62000: 1877513812 +61000: 1289006766 +60000: 3733667461 +59000: 3457358686 +58000: 732502949 +57000: 3971773677 +56000: 883589946 +55000: 290212168 +54000: 2244967385 +53000: 3848247179 +52000: 2228476206 +51000: 2372703555 +50000: 1200411530 +49000: 2060190456 +48000: 2511902942 +47000: 4007272287 +46000: 2854231300 +45000: 2518671311 +44000: 815143404 +43000: 1972543143 +42000: 3063716128 +41000: 3326571310 +40000: 3180391453 +39000: 2568545510 +38000: 573110821 +37000: 3814257324 +36000: 4163248735 +35000: 943584186 +34000: 387069186 +33000: 3519377243 +32000: 3861206003 +31000: 2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 +Exiting @ tick 2371369572000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..489e4d962 --- /dev/null +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1313947 # Simulator instruction rate (inst/s) +host_mem_usage 210340 # Number of bytes of host memory used +host_seconds 1391.71 # Real time elapsed on the host +host_tick_rate 1703921021 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1828637582 # Number of instructions simulated +sim_seconds 2.371370 # Number of seconds simulated +sim_ticks 2371369572000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 55313.788145 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.788145 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 80822350000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 76438867000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.799022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.799022 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 276871028 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4179545000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 74635 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3955640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 74635 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 55347.126181 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency +system.cpu.dcache.demand_hits 895773932 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 85001895000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.001712 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1535796 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 80394507000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001712 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1535796 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999747 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.964018 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 55347.126181 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 895773932 # number of overall hits +system.cpu.dcache.overall_miss_latency 85001895000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.001712 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1535796 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 80394507000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001712 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1535796 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1529845 # number of replacements +system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4094.964018 # Cycle average of tags in use +system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 995704000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74508 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18784.729586 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15784.729586 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 371994000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 312585000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 70202.583043 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18784.729586 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency +system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 371994000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses +system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 312585000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1392.324951 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1390221752 # number of overall hits +system.cpu.icache.overall_miss_latency 371994000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses +system.cpu.icache.overall_misses 19803 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 312585000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 18364 # number of replacements +system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1392.324951 # Cycle average of tags in use +system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3784560000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 72780 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 72780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 41420 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 74856288000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.972032 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1439544 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 57581760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972032 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1439544 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 1855 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51579.514825 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 95680000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1855 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 74200000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1855 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74508 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 74508 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.032124 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 41420 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 78640848000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.973342 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1512324 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 60492960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.973342 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1512324 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.927309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.046837 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 30386.057269 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1534.770026 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 41420 # number of overall hits +system.cpu.l2cache.overall_miss_latency 78640848000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.973342 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1512324 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 60492960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.973342 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1512324 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 1472870 # number of replacements +system.cpu.l2cache.sampled_refs 1505525 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 31920.827295 # Cycle average of tags in use +system.cpu.l2cache.total_refs 48363 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66101 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4742739144 # number of cpu cycles simulated +system.cpu.num_insts 1828637582 # Number of instructions executed +system.cpu.num_refs 908401146 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..f312b762a --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..2dc10edc6 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 52792656500 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..54b57c099 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 4246205 # Simulator instruction rate (inst/s) +host_mem_usage 204740 # Number of bytes of host memory used +host_seconds 23.16 # Real time elapsed on the host +host_tick_rate 2279192640 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 98353426 # Number of instructions simulated +sim_seconds 0.052793 # Number of seconds simulated +sim_ticks 52792656500 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 105585314 # number of cpu cycles simulated +system.cpu.num_insts 98353426 # Number of instructions executed +system.cpu.num_refs 47871034 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..13918f4b6 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..0a6111213 --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:59:20 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 133556162000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..7ded93bcd --- /dev/null +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1206944 # Simulator instruction rate (inst/s) +host_mem_usage 212432 # Number of bytes of host memory used +host_seconds 80.79 # Real time elapsed on the host +host_tick_rate 1653060218 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 97512652 # Number of instructions simulated +sim_seconds 0.133556 # Number of seconds simulated +sim_ticks 133556162000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35927.990796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32927.990796 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1904938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 53021 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1745875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 53021 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.910387 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.910387 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 19754229 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6249086000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 111591 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5914313000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 111591 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 292.838112 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 47030259 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 49534.809127 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency +system.cpu.dcache.demand_hits 46865647 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8154024000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003500 # miss rate for demand accesses +system.cpu.dcache.demand_misses 164612 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7660188000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003500 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 164612 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.995356 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.978068 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 47030259 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 49534.809127 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 46865647 # number of overall hits +system.cpu.dcache.overall_miss_latency 8154024000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003500 # miss rate for overall accesses +system.cpu.dcache.overall_misses 164612 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7660188000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003500 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 164612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 155959 # number of replacements +system.cpu.dcache.sampled_refs 160055 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4076.978068 # Cycle average of tags in use +system.cpu.dcache.total_refs 46870204 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1080546000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 109433 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 78097320 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 24226.782314 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 21226.782314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 78078412 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 458080000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 401356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 4129.385022 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 78097320 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 24226.782314 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency +system.cpu.icache.demand_hits 78078412 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 458080000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses +system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 401356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.847875 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1736.448416 # Average occupied blocks per context +system.cpu.icache.overall_accesses 78097320 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 24226.782314 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 78078412 # number of overall hits +system.cpu.icache.overall_miss_latency 458080000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses +system.cpu.icache.overall_misses 18908 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 401356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 16890 # number of replacements +system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1736.448416 # Cycle average of tags in use +system.cpu.icache.total_refs 78078412 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5565768000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 107034 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4281360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 107034 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 71929 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 39643 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1678872000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.448859 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32286 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1291440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.448859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32286 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4557 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51885.889840 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 236444000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4557 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 182280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4557 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 109433 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 109433 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.358187 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 178963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 39643 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 7244640000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.778485 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 139320 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 5572800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.778485 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 139320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.064995 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.477989 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2129.749713 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15662.741873 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 178963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 39643 # number of overall hits +system.cpu.l2cache.overall_miss_latency 7244640000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.778485 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 139320 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 5572800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.778485 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 139320 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 114093 # number of replacements +system.cpu.l2cache.sampled_refs 132791 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 17792.491585 # Cycle average of tags in use +system.cpu.l2cache.total_refs 47564 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 88579 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 267112324 # number of cpu cycles simulated +system.cpu.num_insts 97512652 # Number of instructions executed +system.cpu.num_refs 47871034 # Number of memory references +system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..33c0bcdab --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..574350233 --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 846553003000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..834bf11ae --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 3961270 # Simulator instruction rate (inst/s) +host_mem_usage 197588 # Number of bytes of host memory used +host_seconds 427.41 # Real time elapsed on the host +host_tick_rate 1980637218 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1693103458 # Number of instructions simulated +sim_seconds 0.846553 # Number of seconds simulated +sim_ticks 846553003000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1693106007 # number of cpu cycles simulated +system.cpu.num_insts 1693103458 # Number of instructions executed +system.cpu.num_refs 660773876 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..91f361a3e --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..c59cdfaa8 --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -0,0 +1,32 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2495902189000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..9dc5d12af --- /dev/null +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1188041 # Simulator instruction rate (inst/s) +host_mem_usage 205272 # Number of bytes of host memory used +host_seconds 1420.24 # Real time elapsed on the host +host_tick_rate 1757384537 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1687299939 # Number of instructions simulated +sim_seconds 2.495902 # Number of seconds simulated +sim_ticks 2495902189000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24911.078403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21911.078403 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180009844000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158331556000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.839740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839740 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 170339765 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125794848000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2246343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119055819000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013016 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2246343 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32283.627480 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency +system.cpu.dcache.demand_hits 645497917 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 305804692000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.014462 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9472439 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 277387375000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014462 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9472439 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.997080 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4084.040360 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32283.627480 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 645497917 # number of overall hits +system.cpu.dcache.overall_miss_latency 305804692000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.014462 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9472439 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 277387375000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014462 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9472439 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 9111149 # number of replacements +system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4084.040360 # Cycle average of tags in use +system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 25923946000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2243257 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 1544565415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1544564777 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2420947.926332 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1544565415 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency +system.cpu.icache.demand_hits 1544564777 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 638 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.251129 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 514.312841 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1544564777 # number of overall hits +system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 638 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 514.312841 # Cycle average of tags in use +system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98235748000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889149 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75565960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889149 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5348868 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 97649032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259850 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1877866 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75114640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259850 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1877866 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357194 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.591505 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18555368000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 357194 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14287760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 357194 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2243257 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2243257 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.405017 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9115883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5348868 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 195884780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413236 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3767015 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 150680600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413236 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3767015 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.425307 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.349424 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 13936.465557 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11449.922093 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 9115883 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5348868 # number of overall hits +system.cpu.l2cache.overall_miss_latency 195884780000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413236 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3767015 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 150680600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3767015 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 2752487 # number of replacements +system.cpu.l2cache.sampled_refs 2779653 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25386.387650 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6685114 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 562275129000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1196151 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4991804378 # number of cpu cycles simulated +system.cpu.num_insts 1687299939 # Number of instructions executed +system.cpu.num_refs 660773876 # Number of memory references +system.cpu.workload.PROG:num_syscalls 46 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..728db8d08 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..ece7183b0 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 102027363500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..ce3775dec --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 4203067 # Simulator instruction rate (inst/s) +host_mem_usage 200448 # Number of bytes of host memory used +host_seconds 44.38 # Real time elapsed on the host +host_tick_rate 2299185912 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 186512085 # Number of instructions simulated +sim_seconds 0.102027 # Number of seconds simulated +sim_ticks 102027363500 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 204054728 # number of cpu cycles simulated +system.cpu.num_insts 186512085 # Number of instructions executed +system.cpu.num_refs 42511846 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..60aa01177 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..77239148f --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -0,0 +1,31 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:54:29 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 232029492000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..6db773218 --- /dev/null +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,233 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1300701 # Simulator instruction rate (inst/s) +host_mem_usage 208132 # Number of bytes of host memory used +host_seconds 143.02 # Real time elapsed on the host +host_tick_rate 1622346657 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 186027114 # Number of instructions simulated +sim_seconds 0.232029 # Number of seconds simulated +sim_ticks 232029492000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 29639490 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36204000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 690 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 34134000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 690 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 12385567 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 63112000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1127 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 59731000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1127 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 54659.328564 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency +system.cpu.dcache.demand_hits 42025057 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 99316000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1817 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 93865000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1817 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.333153 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1364.595461 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 54659.328564 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 42025057 # number of overall hits +system.cpu.dcache.overall_miss_latency 99316000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1817 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 93865000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1817 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 40 # number of replacements +system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 1364.595461 # Cycle average of tags in use +system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 16 # number of writebacks +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses 189792839 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 189789788 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 62205.764667 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 189792839 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency +system.cpu.icache.demand_hits 189789788 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.560534 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1147.972858 # Average occupied blocks per context +system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 189789788 # number of overall hits +system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_misses 3051 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 1506 # number of replacements +system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1147.972858 # Cycle average of tags in use +system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 57200000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1100 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 44000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1100 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 3741 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1380 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 122772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.631115 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2361 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 27 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1404000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 27 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1080000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.588813 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 4841 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1380 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179972000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.714935 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3461 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 138440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.714935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.050372 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1650.604772 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2.043757 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1380 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179972000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.714935 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3461 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 138440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.714935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 2342 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 1652.648529 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 464058984 # number of cpu cycles simulated +system.cpu.num_insts 186027114 # Number of instructions executed +system.cpu.num_refs 42511846 # Number of memory references +system.cpu.workload.PROG:num_syscalls 400 # Number of system calls + +---------- End Simulation Statistics ---------- |