arm: Add a GICv2m device

This patch adds a new PIO-accessible GICv2m shim. This shim has a PIO
slave port on one side, and SPI 'wires' on the other. It accepts MSIs
from the system and triggers SPIs on the GIC. It is configurable with
a number of frames, each of which has a number of SPIs and a base SPI
offset.

A Linux driver for GICv2m is available upstream.

4 files changed, 310 insertions, 1 deletions

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 22ff50010..e5a0d0a7b 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,6 +37,7 @@
 
 from m5.params import *
 from m5.proxy import *
+from m5.SimObject import SimObject
 
 from Device import PioDevice
 from Platform import Platform
@@ -58,3 +59,18 @@ class Pl390(BaseGic):
     cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
     int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
     it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
+
+class Gicv2mFrame(SimObject):
+    type = 'Gicv2mFrame'
+    cxx_header = "dev/arm/gic_v2m.hh"
+    spi_base = Param.UInt32(0x0, "Frame SPI base number");
+    spi_len = Param.UInt32(0x0, "Frame SPI total number");
+    addr = Param.Addr("Address for frame PIO")
+
+class Gicv2m(PioDevice):
+    type = 'Gicv2m'
+    cxx_header = "dev/arm/gic_v2m.hh"
+
+    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
+    gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
+    frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index ad6a22b55..7ed85a587 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -50,6 +50,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('base_gic.cc')
     Source('generic_timer.cc')
     Source('gic_pl390.cc')
+    Source('gic_v2m.cc')
     Source('pl011.cc')
     Source('pl111.cc')
     Source('hdlcd.cc')
@@ -65,6 +66,7 @@ if env['TARGET_ISA'] == 'arm':
     DebugFlag('AMBA')
     DebugFlag('HDLcd')
     DebugFlag('PL111')
+    DebugFlag('GICV2M')
     DebugFlag('Pl050')
     DebugFlag('GIC')
     DebugFlag('RVCTRL')
diff --git a/src/dev/arm/gic_v2m.cc b/src/dev/arm/gic_v2m.cc
new file mode 100644
index 000000000..d90cb986e
--- /dev/null
+++ b/src/dev/arm/gic_v2m.cc
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matt Evans
+ */
+
+/** @file
+ * Implementiation of a GICv2m MSI shim.
+ *
+ * This shim adds MSI support to GICv2.
+ *
+ * This should be instantiated with the appropriate number of frames,
+ * and SPI numbers thereof, to the system being modelled.
+ *
+ * For example, in RealView.py (or whichever board setup is used), instantiate:
+ *
+ * gicv2m = Gicv2m(frames=[
+ *              Gicv2mFrame(addr=0x12340000, spi_base=320, spi_len=64),
+ *              Gicv2mFrame(addr=0x12350000, spi_base=100, spi_len=32),
+ *              Gicv2mFrame(addr=0x12360000, spi_base=150, spi_len=16),
+ *              Gicv2mFrame(addr=0x12370000, spi_base=190, spi_len=8),
+ *              ])
+ *
+ */
+
+#include "dev/arm/gic_v2m.hh"
+
+#include "base/bitunion.hh"
+#include "base/intmath.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/GICV2M.hh"
+#include "dev/io_device.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+Gicv2m *
+Gicv2mParams::create()
+{
+    return new Gicv2m(this);
+}
+
+Gicv2mFrame *
+Gicv2mFrameParams::create()
+{
+    return new Gicv2mFrame(this);
+}
+
+Gicv2m::Gicv2m(const Params *p)
+    : PioDevice(p), pioDelay(p->pio_delay), frames(p->frames), gic(p->gic)
+{
+    // Assert SPI ranges start at 32
+    for (int i = 0; i < frames.size(); i++) {
+        if (frames[i]->spi_base < 32)
+            fatal("Gicv2m: Frame %d's SPI base (%d) is not in SPI space\n",
+                  i, frames[i]->spi_base);
+    }
+    unsigned int x = frames.size();
+    fatal_if(!isPowerOf2(x), "Gicv2m: The v2m shim must be configured with "
+              "a power-of-two number of frames\n");
+    log2framenum = floorLog2(x);
+}
+
+AddrRangeList
+Gicv2m::getAddrRanges() const
+{
+    AddrRangeList ranges;
+    for (int i = 0; i < frames.size(); i++) {
+        ranges.push_back(RangeSize(frames[i]->addr, FRAME_SIZE));
+    }
+    return ranges;
+}
+
+Tick
+Gicv2m::read(PacketPtr pkt)
+{
+    int frame = frameFromAddr(pkt->getAddr());
+
+    assert(frame >= 0);
+
+    Addr offset = pkt->getAddr() - frames[frame]->addr;
+
+    switch (offset) {
+      case MSI_TYPER:
+        pkt->set<uint32_t>((frames[frame]->spi_base << 16) |
+                           frames[frame]->spi_len);
+        break;
+
+      case PER_ID4:
+        pkt->set<uint32_t>(0x4 | ((4+log2framenum) << 4));
+        // Nr of 4KB blocks used by component.  This is messy as frames are 64K
+        // (16, ie 2^4) and we should assert we're given a Po2 number of frames.
+        break;
+      default:
+        DPRINTF(GICV2M, "GICv2m: Read of unk reg %#x\n", offset);
+        pkt->set<uint32_t>(0);
+    };
+
+    pkt->makeAtomicResponse();
+
+    return pioDelay;
+}
+
+Tick
+Gicv2m::write(PacketPtr pkt)
+{
+    int frame = frameFromAddr(pkt->getAddr());
+
+    assert(frame >= 0);
+
+    Addr offset = pkt->getAddr() - frames[frame]->addr;
+
+    if (offset == MSI_SETSPI_NSR) {
+        /* Is payload SPI number within range? */
+        uint32_t m = pkt->get<uint32_t>();
+        if (m >= frames[frame]->spi_base &&
+            m < (frames[frame]->spi_base + frames[frame]->spi_len)) {
+            DPRINTF(GICV2M, "GICv2m: Frame %d raising MSI %d\n", frame, m);
+            gic->sendInt(m);
+        }
+    } else {
+        DPRINTF(GICV2M, "GICv2m: Write of unk reg %#x\n", offset);
+    }
+
+    pkt->makeAtomicResponse();
+
+    return pioDelay;
+}
+
+int
+Gicv2m::frameFromAddr(Addr a) const
+{
+    for (int i = 0; i < frames.size(); i++) {
+        if (a >= frames[i]->addr && a < (frames[i]->addr + FRAME_SIZE))
+            return i;
+    }
+    return -1;
+}
diff --git a/src/dev/arm/gic_v2m.hh b/src/dev/arm/gic_v2m.hh
new file mode 100644
index 000000000..11ee6bea5
--- /dev/null
+++ b/src/dev/arm/gic_v2m.hh
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matt Evans
+ */
+
+/** @file
+ * Implementiation of a GICv2m MSI shim.
+ *
+ * See gic_v2m.cc for an instantiation example.
+ */
+
+#ifndef __DEV_ARM_GIC_V2M_H__
+#define __DEV_ARM_GIC_V2M_H__
+
+#include "base/bitunion.hh"
+#include "cpu/intr_control.hh"
+#include "dev/arm/base_gic.hh"
+#include "dev/io_device.hh"
+#include "dev/platform.hh"
+#include "params/Gicv2m.hh"
+#include "params/Gicv2mFrame.hh"
+
+/**
+ * Ultimately this class should be embedded in the Gicv2m class, but
+ * this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame'
+ * in namespace Gicv2m.
+ */
+class Gicv2mFrame : public SimObject
+{
+  public:
+    const Addr          addr;
+    const unsigned int  spi_base;
+    const unsigned int  spi_len;
+
+    typedef Gicv2mFrameParams Params;
+    Gicv2mFrame(const Params *p) :
+        SimObject(p), addr(p->addr), spi_base(p->spi_base), spi_len(p->spi_len)
+    {}
+};
+
+class Gicv2m : public PioDevice
+{
+  private:
+    static const int FRAME_SIZE         = 0x10000;
+
+    static const int MSI_TYPER          = 0x0008;
+    static const int MSI_SETSPI_NSR     = 0x0040;
+    static const int PER_ID4            = 0x0fd0;
+
+    /** Latency for an MMIO operation */
+    const Tick pioDelay;
+
+    /** A set of configured hardware frames */
+    std::vector<Gicv2mFrame *> frames;
+
+    /** Gic to which we fire interrupts */
+    BaseGic *gic;
+
+    /** Count of number of configured frames, as log2(frames) */
+    unsigned int log2framenum;
+
+  public:
+    typedef Gicv2mParams Params;
+    Gicv2m(const Params *p);
+
+    /** @{ */
+    /** Return the address ranges used by the Gicv2m
+     * This is the set of frame addresses
+     */
+    virtual AddrRangeList getAddrRanges() const;
+
+    /** A PIO read to the device
+     */
+    virtual Tick read(PacketPtr pkt);
+
+    /** A PIO read to the device
+     */
+    virtual Tick write(PacketPtr pkt);
+    /** @} */
+
+  private:
+    /** Determine which frame a PIO access lands in
+     */
+    int frameFromAddr(Addr a) const;
+};
+
+#endif //__DEV_ARM_GIC_V2M_H__