diff options
| author | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-14 12:06:35 -0800 |
|---|---|---|
| committer | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-24 05:47:53 +0000 |
| commit | 331d3cf41701dd714bd5b835a55a0ae5cca950d3 (patch) | |
| tree | 8dd56336dbc19273eec5ba538ec1036ee58577a5 | |
| parent | 7b62df85f8d5513b6fab5a8c40ad2e48ac5010ec (diff) | |
| download | gem5-331d3cf41701dd714bd5b835a55a0ae5cca950d3.tar.xz | |
tests: Removed 20.parser tests
In an effort to cleanup the old tests, and migrate useful tests to be
executed via `test/main.py`, it has been decided that the
`test/long/se/70.twolf` tests should be removed.
Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Ie0c0cd310ee51a37e80a84af3bf1cb603061da7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24384
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
29 files changed, 0 insertions, 9941 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini deleted file mode 100644 index 2bcdda822..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ /dev/null @@ -1,997 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser -gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr deleted file mode 100755 index caeab8324..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout deleted file mode 100755 index e03b3777c..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ /dev/null @@ -1,73 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:47:38 -gem5 executing on e108600-lin, pid 17428 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -info: Increasing stack size by one page. -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 368600034500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt deleted file mode 100644 index c7d099813..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ /dev/null @@ -1,948 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.368651 # Number of seconds simulated -sim_ticks 368651185500 # Number of ticks simulated -final_tick 368651185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 378825 # Simulator instruction rate (inst/s) -host_op_rate 410318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275680946 # Simulator tick rate (ticks/s) -host_mem_usage 276920 # Number of bytes of host memory used -host_seconds 1337.24 # Real time elapsed on the host -sim_insts 506579366 # Number of instructions simulated -sim_ops 548692589 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 179712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9049216 # Number of bytes read from this memory -system.physmem.bytes_read::total 9228928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6241472 # Number of bytes written to this memory -system.physmem.bytes_written::total 6241472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141394 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144202 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97523 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 487485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24546825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25034310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 487485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 487485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16930563 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16930563 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16930563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 487485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24546825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41964873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144202 # Number of read requests accepted -system.physmem.writeReqs 97523 # Number of write requests accepted -system.physmem.readBursts 144202 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97523 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9222208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6240000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9228928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6241472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9327 # Per bank write bursts -system.physmem.perBankRdBursts::1 8931 # Per bank write bursts -system.physmem.perBankRdBursts::2 8953 # Per bank write bursts -system.physmem.perBankRdBursts::3 8672 # Per bank write bursts -system.physmem.perBankRdBursts::4 9421 # Per bank write bursts -system.physmem.perBankRdBursts::5 9371 # Per bank write bursts -system.physmem.perBankRdBursts::6 8975 # Per bank write bursts -system.physmem.perBankRdBursts::7 8126 # Per bank write bursts -system.physmem.perBankRdBursts::8 8631 # Per bank write bursts -system.physmem.perBankRdBursts::9 8699 # Per bank write bursts -system.physmem.perBankRdBursts::10 8760 # Per bank write bursts -system.physmem.perBankRdBursts::11 9484 # Per bank write bursts -system.physmem.perBankRdBursts::12 9351 # Per bank write bursts -system.physmem.perBankRdBursts::13 9541 # Per bank write bursts -system.physmem.perBankRdBursts::14 8731 # Per bank write bursts -system.physmem.perBankRdBursts::15 9124 # Per bank write bursts -system.physmem.perBankWrBursts::0 6232 # Per bank write bursts -system.physmem.perBankWrBursts::1 6121 # Per bank write bursts -system.physmem.perBankWrBursts::2 6045 # Per bank write bursts -system.physmem.perBankWrBursts::3 5902 # Per bank write bursts -system.physmem.perBankWrBursts::4 6267 # Per bank write bursts -system.physmem.perBankWrBursts::5 6264 # Per bank write bursts -system.physmem.perBankWrBursts::6 6070 # Per bank write bursts -system.physmem.perBankWrBursts::7 5535 # Per bank write bursts -system.physmem.perBankWrBursts::8 5819 # Per bank write bursts -system.physmem.perBankWrBursts::9 5921 # Per bank write bursts -system.physmem.perBankWrBursts::10 5985 # Per bank write bursts -system.physmem.perBankWrBursts::11 6509 # Per bank write bursts -system.physmem.perBankWrBursts::12 6365 # Per bank write bursts -system.physmem.perBankWrBursts::13 6345 # Per bank write bursts -system.physmem.perBankWrBursts::14 6018 # Per bank write bursts -system.physmem.perBankWrBursts::15 6102 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368651160000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144202 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97523 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64014 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.533165 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.867212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.438904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22835 35.67% 35.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18294 28.58% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7516 11.74% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7993 12.49% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2085 3.26% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1176 1.84% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 786 1.23% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 642 1.00% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2687 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64014 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5742 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.094566 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 375.615355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5739 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5742 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5742 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.980146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.950575 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.005103 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2875 50.07% 50.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 152 2.65% 52.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2688 46.81% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 17 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 6 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5742 # Writes before turning the bus around for reads -system.physmem.totQLat 3587327500 # Total ticks spent queuing -system.physmem.totMemAccLat 6289146250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720485000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24895.23 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43645.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.33 # Data bus utilization in percentage -system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing -system.physmem.readRowHits 110436 # Number of row buffer hits during reads -system.physmem.writeRowHits 67138 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1525084.95 # Average gap between requests -system.physmem.pageHitRate 73.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229772340 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 122107920 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512480640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 252835920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7717419840.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4012679730 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 354856800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24782953050 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8303052480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68829850950 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115120015110 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.273551 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358922434750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 536706250 # Time in different power states -system.physmem_0.memoryStateTime::REF 3274898000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282951785250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21622731000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5916696250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54348368750 # Time in different power states -system.physmem_1.actEnergy 227351880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 120825210 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 516371940 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 256114080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7627682400.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3951722790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 344311680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24510614460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8148381600 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69110361900 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114816583080 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.450463 # Core power per rank (mW) -system.physmem_1.totalIdleTime 359082796500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 515499000 # Time in different power states -system.physmem_1.memoryStateTime::REF 3236866000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284111116500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 21219892250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5815970250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 53751841500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132096754 # Number of BP lookups -system.cpu.branchPred.condPredicted 98183062 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5916233 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68556674 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60606255 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.403144 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10020256 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 19127 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891736 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3883139 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8597 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54132 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737302371 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506579366 # Number of instructions committed -system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12932918 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.455453 # CPI: cycles per instruction -system.cpu.ipc 0.687071 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction -system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694166450 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43135921 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1141334 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.216677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171085721 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1145430 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.363751 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5072789500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.216677 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 548 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346341652 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346341652 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114567880 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114567880 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537967 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537967 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2792 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2792 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168105847 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168105847 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168108639 # number of overall hits -system.cpu.dcache.overall_hits::total 168108639 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 811293 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 811293 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701082 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701082 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1512375 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1512375 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1512390 # number of overall misses -system.cpu.dcache.overall_misses::total 1512390 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14512864500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14512864500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24025186500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24025186500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38538051000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38538051000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38538051000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38538051000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115379173 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115379173 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2807 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2807 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169618222 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169618222 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169621029 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169621029 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005344 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005344 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008916 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008916 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008916 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008916 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17888.561223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17888.561223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34268.725342 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34268.725342 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25481.809075 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25481.809075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25481.556345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25481.556345 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1068964 # number of writebacks -system.cpu.dcache.writebacks::total 1068964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22242 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22242 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344715 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344715 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366957 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366957 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366957 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366957 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789051 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 789051 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356367 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356367 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1145418 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1145418 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1145430 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1145430 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13418418500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13418418500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12201205500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12201205500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4179500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4179500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25619624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25619624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25623803500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25623803500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006570 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004275 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004275 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17005.768322 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17005.768322 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34237.753496 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34237.753496 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 348291.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 348291.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22367.052028 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22367.052028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22370.466550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22370.466550 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18132 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.493230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199187334 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 20004 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9957.375225 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.493230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1398 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398434680 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398434680 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199187334 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199187334 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199187334 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199187334 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199187334 # number of overall hits -system.cpu.icache.overall_hits::total 199187334 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20004 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20004 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20004 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20004 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20004 # number of overall misses -system.cpu.icache.overall_misses::total 20004 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 543340500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 543340500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 543340500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 543340500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 543340500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 543340500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199207338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199207338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199207338 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199207338 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199207338 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199207338 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27161.592681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27161.592681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27161.592681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27161.592681 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 18132 # number of writebacks -system.cpu.icache.writebacks::total 18132 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20004 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 20004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20004 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 20004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20004 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523336500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 523336500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523336500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 523336500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523336500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 523336500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26161.592681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26161.592681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112700 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29077.009680 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2174426 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145468 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.947796 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102124248000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 135.271970 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.139631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28633.598078 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004128 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.873828 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.887360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 988 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31579 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18704732 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18704732 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1068964 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1068964 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17895 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17895 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255662 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255662 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17195 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17195 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748361 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748361 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1004023 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1021218 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17195 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1004023 # number of overall hits -system.cpu.l2cache.overall_hits::total 1021218 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100957 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100957 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40450 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 40450 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141407 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144216 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141407 # number of overall misses -system.cpu.l2cache.overall_misses::total 144216 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8984700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8984700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312111000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 312111000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4361406500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4361406500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 312111000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13346107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13658218000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 312111000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13346107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13658218000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068964 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1068964 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 17895 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 17895 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20004 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 20004 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788811 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 788811 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 20004 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1145430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1165434 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 20004 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1145430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1165434 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283095 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283095 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140422 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140422 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051280 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051280 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140422 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123453 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123744 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140422 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123453 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123744 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88995.319790 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88995.319790 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111111.071556 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111111.071556 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107822.163164 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107822.163164 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94706.676097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94706.676097 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97523 # number of writebacks -system.cpu.l2cache.writebacks::total 97523 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100957 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100957 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2808 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2808 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40437 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40437 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2808 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144202 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141394 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144202 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975130500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975130500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283956000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283956000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3955182000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3955182000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283956000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11930312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12214268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283956000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11930312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12214268500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283095 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283095 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140372 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123732 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123732 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78995.319790 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78995.319790 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101123.931624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101123.931624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97810.965205 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97810.965205 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2324900 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159536 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4992 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 808815 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 20004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 788811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3490334 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141721216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144161920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112700 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6241472 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1278134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006011 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270454 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7677 0.60% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1278134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249546000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30029453 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718153483 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 254284 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 110251 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 43245 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97523 # Transaction distribution -system.membus.trans_dist::CleanEvict 12559 # Transaction distribution -system.membus.trans_dist::ReadExReq 100957 # Transaction distribution -system.membus.trans_dist::ReadExResp 100957 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43245 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398486 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398486 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15470400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15470400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 144202 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 144202 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 144202 # Request fanout histogram -system.membus.reqLayer0.occupancy 684899000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765515250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini deleted file mode 100644 index e92ae69a2..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ /dev/null @@ -1,962 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=16 -LSQCheckLoads=true -LSQDepCheckShift=0 -SQEntries=16 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cacheStorePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=2 -decodeWidth=3 -default_p_state=UNDEFINED -dispatchWidth=6 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=16 -fetchQueueSize=32 -fetchToDecodeDelay=3 -fetchTrapLatency=1 -fetchWidth=3 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=32 -numPhysCCRegs=640 -numPhysFloatRegs=192 -numPhysIntRegs=128 -numROBEntries=40 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=1 -renameToROBDelay=1 -renameWidth=3 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BiModeBP -BTBEntries=2048 -BTBTagSize=18 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=8 -write_buffers=16 -writeback_clean=true -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 opList2 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList1.opList2] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 - -[system.cpu.fuPool.FUList4.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList20] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList21] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList22] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList23] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=9 -pipelined=false - -[system.cpu.fuPool.FUList4.opList24] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=33 -pipelined=false - -[system.cpu.fuPool.FUList4.opList25] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList26] -type=OpDesc -eventq_index=0 -opClass=FloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList27] -type=OpDesc -eventq_index=0 -opClass=FloatMisc -opLat=3 -pipelined=true - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=1 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=1 -sequential_access=false -size=32768 -system=system -tag_latency=1 -tags=system.cpu.icache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=1 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=1 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=prefetcher tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=16 -clk_domain=system.cpu_clk_domain -clusivity=mostly_excl -data_latency=12 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=true -prefetcher=system.cpu.l2cache.prefetcher -response_latency=12 -sequential_access=false -size=1048576 -system=system -tag_latency=12 -tags=system.cpu.l2cache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.prefetcher] -type=StridePrefetcher -cache_snoop=false -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -degree=8 -eventq_index=0 -latency=1 -max_conf=7 -min_conf=0 -on_data=true -on_inst=true -on_miss=false -on_read=true -on_write=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -queue_filter=true -queue_size=32 -queue_squash=true -start_conf=4 -sys=system -table_assoc=4 -table_sets=16 -tag_prefetch=true -thresh_conf=4 -use_master_id=true - -[system.cpu.l2cache.tags] -type=RandomRepl -assoc=16 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=12 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1048576 -tag_latency=12 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr deleted file mode 100755 index edc1e135d..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout deleted file mode 100755 index 9e9d8d4ce..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ /dev/null @@ -1,70 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 18:14:44 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 235850129000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt deleted file mode 100644 index 90cdb7653..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ /dev/null @@ -1,1276 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.235850 -sim_ticks 235850129000 -final_tick 235850129000 -sim_freq 1000000000000 -host_inst_rate 106785 -host_op_rate 115686 -host_tick_rate 49848699 -host_mem_usage 313808 -host_seconds 4731.32 -sim_insts 505234934 -sim_ops 547348155 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.physmem.bytes_read::cpu.inst 651264 -system.physmem.bytes_read::cpu.data 10497792 -system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 -system.physmem.bytes_read::total 27559104 -system.physmem.bytes_inst_read::cpu.inst 651264 -system.physmem.bytes_inst_read::total 651264 -system.physmem.bytes_written::writebacks 18653440 -system.physmem.bytes_written::total 18653440 -system.physmem.num_reads::cpu.inst 10176 -system.physmem.num_reads::cpu.data 164028 -system.physmem.num_reads::cpu.l2cache.prefetcher 256407 -system.physmem.num_reads::total 430611 -system.physmem.num_writes::writebacks 291460 -system.physmem.num_writes::total 291460 -system.physmem.bw_read::cpu.inst 2761347 -system.physmem.bw_read::cpu.data 44510436 -system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 -system.physmem.bw_read::total 116850070 -system.physmem.bw_inst_read::cpu.inst 2761347 -system.physmem.bw_inst_read::total 2761347 -system.physmem.bw_write::writebacks 79090226 -system.physmem.bw_write::total 79090226 -system.physmem.bw_total::writebacks 79090226 -system.physmem.bw_total::cpu.inst 2761347 -system.physmem.bw_total::cpu.data 44510436 -system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 -system.physmem.bw_total::total 195940296 -system.physmem.readReqs 430611 -system.physmem.writeReqs 291460 -system.physmem.readBursts 430611 -system.physmem.writeBursts 291460 -system.physmem.bytesReadDRAM 27396288 -system.physmem.bytesReadWrQ 162816 -system.physmem.bytesWritten 18651392 -system.physmem.bytesReadSys 27559104 -system.physmem.bytesWrittenSys 18653440 -system.physmem.servicedByWrQ 2544 -system.physmem.mergedWrBursts 9 -system.physmem.neitherReadNorWriteReqs 0 -system.physmem.perBankRdBursts::0 27102 -system.physmem.perBankRdBursts::1 26174 -system.physmem.perBankRdBursts::2 25664 -system.physmem.perBankRdBursts::3 33006 -system.physmem.perBankRdBursts::4 27996 -system.physmem.perBankRdBursts::5 29984 -system.physmem.perBankRdBursts::6 25487 -system.physmem.perBankRdBursts::7 24586 -system.physmem.perBankRdBursts::8 25526 -system.physmem.perBankRdBursts::9 25681 -system.physmem.perBankRdBursts::10 25862 -system.physmem.perBankRdBursts::11 26092 -system.physmem.perBankRdBursts::12 27614 -system.physmem.perBankRdBursts::13 26106 -system.physmem.perBankRdBursts::14 25123 -system.physmem.perBankRdBursts::15 26064 -system.physmem.perBankWrBursts::0 18530 -system.physmem.perBankWrBursts::1 18172 -system.physmem.perBankWrBursts::2 17960 -system.physmem.perBankWrBursts::3 17946 -system.physmem.perBankWrBursts::4 18535 -system.physmem.perBankWrBursts::5 18092 -system.physmem.perBankWrBursts::6 17937 -system.physmem.perBankWrBursts::7 17864 -system.physmem.perBankWrBursts::8 17881 -system.physmem.perBankWrBursts::9 17814 -system.physmem.perBankWrBursts::10 18253 -system.physmem.perBankWrBursts::11 18685 -system.physmem.perBankWrBursts::12 18794 -system.physmem.perBankWrBursts::13 18180 -system.physmem.perBankWrBursts::14 18427 -system.physmem.perBankWrBursts::15 18358 -system.physmem.numRdRetry 0 -system.physmem.numWrRetry 0 -system.physmem.totGap 235850076500 -system.physmem.readPktSize::0 0 -system.physmem.readPktSize::1 0 -system.physmem.readPktSize::2 0 -system.physmem.readPktSize::3 0 -system.physmem.readPktSize::4 0 -system.physmem.readPktSize::5 0 -system.physmem.readPktSize::6 430611 -system.physmem.writePktSize::0 0 -system.physmem.writePktSize::1 0 -system.physmem.writePktSize::2 0 -system.physmem.writePktSize::3 0 -system.physmem.writePktSize::4 0 -system.physmem.writePktSize::5 0 -system.physmem.writePktSize::6 291460 -system.physmem.rdQLenPdf::0 318665 -system.physmem.rdQLenPdf::1 60579 -system.physmem.rdQLenPdf::2 13349 -system.physmem.rdQLenPdf::3 9026 -system.physmem.rdQLenPdf::4 7328 -system.physmem.rdQLenPdf::5 6151 -system.physmem.rdQLenPdf::6 5231 -system.physmem.rdQLenPdf::7 4311 -system.physmem.rdQLenPdf::8 3288 -system.physmem.rdQLenPdf::9 74 -system.physmem.rdQLenPdf::10 37 -system.physmem.rdQLenPdf::11 14 -system.physmem.rdQLenPdf::12 8 -system.physmem.rdQLenPdf::13 3 -system.physmem.rdQLenPdf::14 2 -system.physmem.rdQLenPdf::15 1 -system.physmem.rdQLenPdf::16 0 -system.physmem.rdQLenPdf::17 0 -system.physmem.rdQLenPdf::18 0 -system.physmem.rdQLenPdf::19 0 -system.physmem.rdQLenPdf::20 0 -system.physmem.rdQLenPdf::21 0 -system.physmem.rdQLenPdf::22 0 -system.physmem.rdQLenPdf::23 0 -system.physmem.rdQLenPdf::24 0 -system.physmem.rdQLenPdf::25 0 -system.physmem.rdQLenPdf::26 0 -system.physmem.rdQLenPdf::27 0 -system.physmem.rdQLenPdf::28 0 -system.physmem.rdQLenPdf::29 0 -system.physmem.rdQLenPdf::30 0 -system.physmem.rdQLenPdf::31 0 -system.physmem.wrQLenPdf::0 1 -system.physmem.wrQLenPdf::1 1 -system.physmem.wrQLenPdf::2 1 -system.physmem.wrQLenPdf::3 1 -system.physmem.wrQLenPdf::4 1 -system.physmem.wrQLenPdf::5 1 -system.physmem.wrQLenPdf::6 1 -system.physmem.wrQLenPdf::7 1 -system.physmem.wrQLenPdf::8 1 -system.physmem.wrQLenPdf::9 1 -system.physmem.wrQLenPdf::10 1 -system.physmem.wrQLenPdf::11 1 -system.physmem.wrQLenPdf::12 1 -system.physmem.wrQLenPdf::13 1 -system.physmem.wrQLenPdf::14 1 -system.physmem.wrQLenPdf::15 6820 -system.physmem.wrQLenPdf::16 7302 -system.physmem.wrQLenPdf::17 12035 -system.physmem.wrQLenPdf::18 14838 -system.physmem.wrQLenPdf::19 16182 -system.physmem.wrQLenPdf::20 16933 -system.physmem.wrQLenPdf::21 17312 -system.physmem.wrQLenPdf::22 17637 -system.physmem.wrQLenPdf::23 17893 -system.physmem.wrQLenPdf::24 18126 -system.physmem.wrQLenPdf::25 18306 -system.physmem.wrQLenPdf::26 18426 -system.physmem.wrQLenPdf::27 18598 -system.physmem.wrQLenPdf::28 18683 -system.physmem.wrQLenPdf::29 18906 -system.physmem.wrQLenPdf::30 18563 -system.physmem.wrQLenPdf::31 17444 -system.physmem.wrQLenPdf::32 17201 -system.physmem.wrQLenPdf::33 121 -system.physmem.wrQLenPdf::34 50 -system.physmem.wrQLenPdf::35 24 -system.physmem.wrQLenPdf::36 18 -system.physmem.wrQLenPdf::37 16 -system.physmem.wrQLenPdf::38 2 -system.physmem.wrQLenPdf::39 0 -system.physmem.wrQLenPdf::40 0 -system.physmem.wrQLenPdf::41 0 -system.physmem.wrQLenPdf::42 0 -system.physmem.wrQLenPdf::43 0 -system.physmem.wrQLenPdf::44 0 -system.physmem.wrQLenPdf::45 0 -system.physmem.wrQLenPdf::46 0 -system.physmem.wrQLenPdf::47 0 -system.physmem.wrQLenPdf::48 0 -system.physmem.wrQLenPdf::49 0 -system.physmem.wrQLenPdf::50 0 -system.physmem.wrQLenPdf::51 0 -system.physmem.wrQLenPdf::52 0 -system.physmem.wrQLenPdf::53 0 -system.physmem.wrQLenPdf::54 0 -system.physmem.wrQLenPdf::55 0 -system.physmem.wrQLenPdf::56 0 -system.physmem.wrQLenPdf::57 0 -system.physmem.wrQLenPdf::58 0 -system.physmem.wrQLenPdf::59 0 -system.physmem.wrQLenPdf::60 0 -system.physmem.wrQLenPdf::61 0 -system.physmem.wrQLenPdf::62 0 -system.physmem.wrQLenPdf::63 0 -system.physmem.bytesPerActivate::samples 329170 -system.physmem.bytesPerActivate::mean 139.885214 -system.physmem.bytesPerActivate::gmean 98.537517 -system.physmem.bytesPerActivate::stdev 178.782393 -system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% -system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% -system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% -system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% -system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% -system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% -system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% -system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% -system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% -system.physmem.bytesPerActivate::total 329170 -system.physmem.rdPerTurnAround::samples 17054 -system.physmem.rdPerTurnAround::mean 25.096224 -system.physmem.rdPerTurnAround::stdev 145.074041 -system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% -system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% -system.physmem.rdPerTurnAround::total 17054 -system.physmem.wrPerTurnAround::samples 17054 -system.physmem.wrPerTurnAround::mean 17.088542 -system.physmem.wrPerTurnAround::gmean 17.022727 -system.physmem.wrPerTurnAround::stdev 1.689258 -system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% -system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% -system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% -system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% -system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% -system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% -system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% -system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% -system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% -system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% -system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% -system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% -system.physmem.wrPerTurnAround::total 17054 -system.physmem.totQLat 14249250266 -system.physmem.totMemAccLat 22275506516 -system.physmem.totBusLat 2140335000 -system.physmem.avgQLat 33287.43 -system.physmem.avgBusLat 5000.00 -system.physmem.avgMemAccLat 52037.43 -system.physmem.avgRdBW 116.16 -system.physmem.avgWrBW 79.08 -system.physmem.avgRdBWSys 116.85 -system.physmem.avgWrBWSys 79.09 -system.physmem.peakBW 12800.00 -system.physmem.busUtil 1.53 -system.physmem.busUtilRead 0.91 -system.physmem.busUtilWrite 0.62 -system.physmem.avgRdQLen 1.13 -system.physmem.avgWrQLen 21.62 -system.physmem.readRowHits 308139 -system.physmem.writeRowHits 82177 -system.physmem.readRowHitRate 71.98 -system.physmem.writeRowHitRate 28.20 -system.physmem.avgGap 326630.04 -system.physmem.pageHitRate 54.25 -system.physmem_0.actEnergy 1195207440 -system.physmem_0.preEnergy 635245050 -system.physmem_0.readEnergy 1570792860 -system.physmem_0.writeEnergy 757087920 -system.physmem_0.refreshEnergy 15735398640.000004 -system.physmem_0.actBackEnergy 13510945980 -system.physmem_0.preBackEnergy 615046560 -system.physmem_0.actPowerDownEnergy 46117601610 -system.physmem_0.prePowerDownEnergy 17430135360 -system.physmem_0.selfRefreshEnergy 15587831640 -system.physmem_0.totalEnergy 113161874670 -system.physmem_0.averagePower 479.804155 -system.physmem_0.totalIdleTime 204603400415 -system.physmem_0.memoryStateTime::IDLE 912794276 -system.physmem_0.memoryStateTime::REF 6674692000 -system.physmem_0.memoryStateTime::SREF 58078463500 -system.physmem_0.memoryStateTime::PRE_PDN 45390268663 -system.physmem_0.memoryStateTime::ACT 23659127059 -system.physmem_0.memoryStateTime::ACT_PDN 101134783502 -system.physmem_1.actEnergy 1155130620 -system.physmem_1.preEnergy 613955100 -system.physmem_1.readEnergy 1485605520 -system.physmem_1.writeEnergy 764166240 -system.physmem_1.refreshEnergy 15039011520.000004 -system.physmem_1.actBackEnergy 13474802850 -system.physmem_1.preBackEnergy 604322400 -system.physmem_1.actPowerDownEnergy 42537889890 -system.physmem_1.prePowerDownEnergy 17081497440 -system.physmem_1.selfRefreshEnergy 17718944700 -system.physmem_1.totalEnergy 110481339780 -system.physmem_1.averagePower 468.438739 -system.physmem_1.totalIdleTime 204713337667 -system.physmem_1.memoryStateTime::IDLE 914400899 -system.physmem_1.memoryStateTime::REF 6380142000 -system.physmem_1.memoryStateTime::SREF 66945121250 -system.physmem_1.memoryStateTime::PRE_PDN 44482448304 -system.physmem_1.memoryStateTime::ACT 23842248434 -system.physmem_1.memoryStateTime::ACT_PDN 93285768113 -system.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.branchPred.lookups 174426540 -system.cpu.branchPred.condPredicted 130958868 -system.cpu.branchPred.condIncorrect 7258964 -system.cpu.branchPred.BTBLookups 89936054 -system.cpu.branchPred.BTBHits 78903188 -system.cpu.branchPred.BTBCorrect 0 -system.cpu.branchPred.BTBHitPct 87.732544 -system.cpu.branchPred.usedRAS 12071651 -system.cpu.branchPred.RASInCorrect 104612 -system.cpu.branchPred.indirectLookups 4685817 -system.cpu.branchPred.indirectHits 4672093 -system.cpu.branchPred.indirectMisses 13724 -system.cpu.branchPredindirectMispredicted 53795 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.hits 0 -system.cpu.istage2_mmu.stage2_tlb.misses 0 -system.cpu.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.itb.walker.walks 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.itb.walker.walkRequestOrigin::total 0 -system.cpu.itb.inst_hits 0 -system.cpu.itb.inst_misses 0 -system.cpu.itb.read_hits 0 -system.cpu.itb.read_misses 0 -system.cpu.itb.write_hits 0 -system.cpu.itb.write_misses 0 -system.cpu.itb.flush_tlb 0 -system.cpu.itb.flush_tlb_mva 0 -system.cpu.itb.flush_tlb_mva_asid 0 -system.cpu.itb.flush_tlb_asid 0 -system.cpu.itb.flush_entries 0 -system.cpu.itb.align_faults 0 -system.cpu.itb.prefetch_faults 0 -system.cpu.itb.domain_faults 0 -system.cpu.itb.perms_faults 0 -system.cpu.itb.read_accesses 0 -system.cpu.itb.write_accesses 0 -system.cpu.itb.inst_accesses 0 -system.cpu.itb.hits 0 -system.cpu.itb.misses 0 -system.cpu.itb.accesses 0 -system.cpu.workload.numSyscalls 548 -system.cpu.pwrStateResidencyTicks::ON 235850129000 -system.cpu.numCycles 471700259 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.fetch.icacheStallCycles 7689412 -system.cpu.fetch.Insts 726848478 -system.cpu.fetch.Branches 174426540 -system.cpu.fetch.predictedBranches 95646932 -system.cpu.fetch.Cycles 455559849 -system.cpu.fetch.SquashCycles 14571166 -system.cpu.fetch.MiscStallCycles 7088 -system.cpu.fetch.PendingTrapStallCycles 169 -system.cpu.fetch.IcacheWaitRetryStallCycles 15067 -system.cpu.fetch.CacheLines 235109896 -system.cpu.fetch.IcacheSquashes 36736 -system.cpu.fetch.rateDist::samples 470557168 -system.cpu.fetch.rateDist::mean 1.672087 -system.cpu.fetch.rateDist::stdev 1.189865 -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% -system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% -system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% -system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% -system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% -system.cpu.fetch.rateDist::min_value 0 -system.cpu.fetch.rateDist::max_value 3 -system.cpu.fetch.rateDist::total 470557168 -system.cpu.fetch.branchRate 0.369783 -system.cpu.fetch.rate 1.540912 -system.cpu.decode.IdleCycles 32637512 -system.cpu.decode.BlockedCycles 125886415 -system.cpu.decode.RunCycles 282414401 -system.cpu.decode.UnblockCycles 22855437 -system.cpu.decode.SquashCycles 6763403 -system.cpu.decode.BranchResolved 71909343 -system.cpu.decode.BranchMispred 530427 -system.cpu.decode.DecodedInsts 710086582 -system.cpu.decode.SquashedInsts 29127059 -system.cpu.rename.SquashCycles 6763403 -system.cpu.rename.IdleCycles 63488458 -system.cpu.rename.BlockCycles 61155779 -system.cpu.rename.serializeStallCycles 40463668 -system.cpu.rename.RunCycles 273022741 -system.cpu.rename.UnblockCycles 25663119 -system.cpu.rename.RenamedInsts 681926435 -system.cpu.rename.SquashedInsts 12775010 -system.cpu.rename.ROBFullEvents 10060236 -system.cpu.rename.IQFullEvents 2531231 -system.cpu.rename.LQFullEvents 1813266 -system.cpu.rename.SQFullEvents 2373970 -system.cpu.rename.RenamedOperands 826391408 -system.cpu.rename.RenameLookups 2997146717 -system.cpu.rename.int_rename_lookups 717894841 -system.cpu.rename.fp_rename_lookups 88 -system.cpu.rename.CommittedMaps 654095674 -system.cpu.rename.UndoneMaps 172295734 -system.cpu.rename.serializingInsts 1545774 -system.cpu.rename.tempSerializingInsts 1536126 -system.cpu.rename.skidInsts 43961162 -system.cpu.memDep0.insertedLoads 142203026 -system.cpu.memDep0.insertedStores 67513624 -system.cpu.memDep0.conflictingLoads 12913434 -system.cpu.memDep0.conflictingStores 11193544 -system.cpu.iq.iqInstsAdded 664083030 -system.cpu.iq.iqNonSpecInstsAdded 2979301 -system.cpu.iq.iqInstsIssued 608560988 -system.cpu.iq.iqSquashedInstsIssued 5743597 -system.cpu.iq.iqSquashedInstsExamined 119714175 -system.cpu.iq.iqSquashedOperandsExamined 304959820 -system.cpu.iq.iqSquashedNonSpecRemoved 1669 -system.cpu.iq.issued_per_cycle::samples 470557168 -system.cpu.iq.issued_per_cycle::mean 1.293277 -system.cpu.iq.issued_per_cycle::stdev 1.104886 -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% -system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% -system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% -system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% -system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% -system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% -system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% -system.cpu.iq.issued_per_cycle::min_value 0 -system.cpu.iq.issued_per_cycle::max_value 5 -system.cpu.iq.issued_per_cycle::total 470557168 -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% -system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% -system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% -system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% -system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% -system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% -system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% -system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% -system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% -system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% -system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% -system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% -system.cpu.iq.FU_type_0::total 608560988 -system.cpu.iq.rate 1.290143 -system.cpu.iq.fu_busy_cnt 135463169 -system.cpu.iq.fu_busy_rate 0.222596 -system.cpu.iq.int_inst_queue_reads 1828885813 -system.cpu.iq.int_inst_queue_writes 786805256 -system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 -system.cpu.iq.fp_inst_queue_reads 97 -system.cpu.iq.fp_inst_queue_writes 70 -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 -system.cpu.iq.int_alu_accesses 744024094 -system.cpu.iq.fp_alu_accesses 63 -system.cpu.iew.lsq.thread0.forwLoads 7272380 -system.cpu.iew.lsq.thread0.invAddrLoads 0 -system.cpu.iew.lsq.thread0.squashedLoads 26319743 -system.cpu.iew.lsq.thread0.ignoredResponses 24134 -system.cpu.iew.lsq.thread0.memOrderViolation 29234 -system.cpu.iew.lsq.thread0.squashedStores 10653404 -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 -system.cpu.iew.lsq.thread0.blockedLoads 0 -system.cpu.iew.lsq.thread0.rescheduledLoads 224604 -system.cpu.iew.lsq.thread0.cacheBlocked 23301 -system.cpu.iew.iewIdleCycles 0 -system.cpu.iew.iewSquashCycles 6763403 -system.cpu.iew.iewBlockCycles 23756716 -system.cpu.iew.iewUnblockCycles 981361 -system.cpu.iew.iewDispatchedInsts 668554311 -system.cpu.iew.iewDispSquashedInsts 0 -system.cpu.iew.iewDispLoadInsts 142203026 -system.cpu.iew.iewDispStoreInsts 67513624 -system.cpu.iew.iewDispNonSpecInsts 1490759 -system.cpu.iew.iewIQFullEvents 256987 -system.cpu.iew.iewLSQFullEvents 586437 -system.cpu.iew.memOrderViolationEvents 29234 -system.cpu.iew.predictedTakenIncorrect 3560929 -system.cpu.iew.predictedNotTakenIncorrect 3767464 -system.cpu.iew.branchMispredicts 7328393 -system.cpu.iew.iewExecutedInsts 598121332 -system.cpu.iew.iewExecLoadInsts 128978812 -system.cpu.iew.iewExecSquashedInsts 10439656 -system.cpu.iew.exec_swp 0 -system.cpu.iew.exec_nop 1491980 -system.cpu.iew.exec_refs 189925083 -system.cpu.iew.exec_branches 131214447 -system.cpu.iew.exec_stores 60946271 -system.cpu.iew.exec_rate 1.268011 -system.cpu.iew.wb_sent 595160432 -system.cpu.iew.wb_count 593918729 -system.cpu.iew.wb_producers 349300209 -system.cpu.iew.wb_consumers 571006140 -system.cpu.iew.wb_rate 1.259102 -system.cpu.iew.wb_fanout 0.611728 -system.cpu.commit.commitSquashedInsts 106531473 -system.cpu.commit.commitNonSpecStalls 2977632 -system.cpu.commit.branchMispredicts 6736784 -system.cpu.commit.committed_per_cycle::samples 453954004 -system.cpu.commit.committed_per_cycle::mean 1.208695 -system.cpu.commit.committed_per_cycle::stdev 1.885174 -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% -system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% -system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% -system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% -system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% -system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% -system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% -system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% -system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% -system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% -system.cpu.commit.committed_per_cycle::min_value 0 -system.cpu.commit.committed_per_cycle::max_value 8 -system.cpu.commit.committed_per_cycle::total 453954004 -system.cpu.commit.committedInsts 506578818 -system.cpu.commit.committedOps 548692039 -system.cpu.commit.swp_count 0 -system.cpu.commit.refs 172743503 -system.cpu.commit.loads 115883283 -system.cpu.commit.membars 1488542 -system.cpu.commit.branches 121552863 -system.cpu.commit.fp_insts 16 -system.cpu.commit.int_insts 448447003 -system.cpu.commit.function_calls 9757362 -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% -system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% -system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% -system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% -system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% -system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% -system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% -system.cpu.commit.op_class_0::total 548692039 -system.cpu.commit.bw_lim_events 13948036 -system.cpu.rob.rob_reads 1095222342 -system.cpu.rob.rob_writes 1327086116 -system.cpu.timesIdled 14782 -system.cpu.idleCycles 1143091 -system.cpu.committedInsts 505234934 -system.cpu.committedOps 547348155 -system.cpu.cpi 0.933626 -system.cpu.cpi_total 0.933626 -system.cpu.ipc 1.071093 -system.cpu.ipc_total 1.071093 -system.cpu.int_regfile_reads 609897818 -system.cpu.int_regfile_writes 327085541 -system.cpu.fp_regfile_reads 16 -system.cpu.cc_regfile_reads 2165040622 -system.cpu.cc_regfile_writes 376344417 -system.cpu.misc_regfile_reads 217537377 -system.cpu.misc_regfile_writes 2977084 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.dcache.tags.replacements 2817480 -system.cpu.dcache.tags.tagsinuse 511.627959 -system.cpu.dcache.tags.total_refs 168773991 -system.cpu.dcache.tags.sampled_refs 2817992 -system.cpu.dcache.tags.avg_refs 59.891579 -system.cpu.dcache.tags.warmup_cycle 504701000 -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 -system.cpu.dcache.tags.occ_percent::total 0.999273 -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 -system.cpu.dcache.tags.occ_task_id_percent::1024 1 -system.cpu.dcache.tags.tag_accesses 355076080 -system.cpu.dcache.tags.data_accesses 355076080 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.dcache.ReadReq_hits::cpu.data 114071383 -system.cpu.dcache.ReadReq_hits::total 114071383 -system.cpu.dcache.WriteReq_hits::cpu.data 51722665 -system.cpu.dcache.WriteReq_hits::total 51722665 -system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 -system.cpu.dcache.SoftPFReq_hits::total 2778 -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 -system.cpu.dcache.LoadLockedReq_hits::total 1488556 -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 -system.cpu.dcache.StoreCondReq_hits::total 1488541 -system.cpu.dcache.demand_hits::cpu.data 165794048 -system.cpu.dcache.demand_hits::total 165794048 -system.cpu.dcache.overall_hits::cpu.data 165796826 -system.cpu.dcache.overall_hits::total 165796826 -system.cpu.dcache.ReadReq_misses::cpu.data 4838662 -system.cpu.dcache.ReadReq_misses::total 4838662 -system.cpu.dcache.WriteReq_misses::cpu.data 2516384 -system.cpu.dcache.WriteReq_misses::total 2516384 -system.cpu.dcache.SoftPFReq_misses::cpu.data 10 -system.cpu.dcache.SoftPFReq_misses::total 10 -system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 -system.cpu.dcache.LoadLockedReq_misses::total 65 -system.cpu.dcache.demand_misses::cpu.data 7355046 -system.cpu.dcache.demand_misses::total 7355046 -system.cpu.dcache.overall_misses::cpu.data 7355056 -system.cpu.dcache.overall_misses::total 7355056 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 -system.cpu.dcache.ReadReq_miss_latency::total 63735397500 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 -system.cpu.dcache.WriteReq_miss_latency::total 19938555937 -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 -system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 -system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 -system.cpu.dcache.demand_miss_latency::total 83673953437 -system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 -system.cpu.dcache.overall_miss_latency::total 83673953437 -system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 -system.cpu.dcache.ReadReq_accesses::total 118910045 -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 -system.cpu.dcache.WriteReq_accesses::total 54239049 -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 -system.cpu.dcache.SoftPFReq_accesses::total 2788 -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 -system.cpu.dcache.LoadLockedReq_accesses::total 1488621 -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 -system.cpu.dcache.StoreCondReq_accesses::total 1488541 -system.cpu.dcache.demand_accesses::cpu.data 173149094 -system.cpu.dcache.demand_accesses::total 173149094 -system.cpu.dcache.overall_accesses::cpu.data 173151882 -system.cpu.dcache.overall_accesses::total 173151882 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 -system.cpu.dcache.ReadReq_miss_rate::total 0.040692 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 -system.cpu.dcache.WriteReq_miss_rate::total 0.046394 -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 -system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 -system.cpu.dcache.demand_miss_rate::total 0.042478 -system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 -system.cpu.dcache.overall_miss_rate::total 0.042477 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 -system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 -system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 -system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 -system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 -system.cpu.dcache.blocked_cycles::no_mshrs 14 -system.cpu.dcache.blocked_cycles::no_targets 1100252 -system.cpu.dcache.blocked::no_mshrs 3 -system.cpu.dcache.blocked::no_targets 221126 -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 -system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 -system.cpu.dcache.writebacks::writebacks 2817480 -system.cpu.dcache.writebacks::total 2817480 -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 -system.cpu.dcache.ReadReq_mshr_hits::total 2540507 -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 -system.cpu.dcache.WriteReq_mshr_hits::total 1996523 -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 -system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 -system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 -system.cpu.dcache.demand_mshr_hits::total 4537030 -system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 -system.cpu.dcache.overall_mshr_hits::total 4537030 -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 -system.cpu.dcache.ReadReq_mshr_misses::total 2298155 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 -system.cpu.dcache.WriteReq_mshr_misses::total 519861 -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 -system.cpu.dcache.SoftPFReq_mshr_misses::total 9 -system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 -system.cpu.dcache.demand_mshr_misses::total 2818016 -system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 -system.cpu.dcache.overall_mshr_misses::total 2818025 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 -system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 -system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 -system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 -system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.icache.tags.replacements 76537 -system.cpu.icache.tags.tagsinuse 465.899675 -system.cpu.icache.tags.total_refs 235023805 -system.cpu.icache.tags.sampled_refs 77049 -system.cpu.icache.tags.avg_refs 3050.316098 -system.cpu.icache.tags.warmup_cycle 116553680500 -system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 -system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 -system.cpu.icache.tags.occ_percent::total 0.909960 -system.cpu.icache.tags.occ_task_id_blocks::1024 512 -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 -system.cpu.icache.tags.age_task_id_blocks_1024::1 263 -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 -system.cpu.icache.tags.age_task_id_blocks_1024::4 14 -system.cpu.icache.tags.occ_task_id_percent::1024 1 -system.cpu.icache.tags.tag_accesses 470296624 -system.cpu.icache.tags.data_accesses 470296624 -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.icache.ReadReq_hits::cpu.inst 235023805 -system.cpu.icache.ReadReq_hits::total 235023805 -system.cpu.icache.demand_hits::cpu.inst 235023805 -system.cpu.icache.demand_hits::total 235023805 -system.cpu.icache.overall_hits::cpu.inst 235023805 -system.cpu.icache.overall_hits::total 235023805 -system.cpu.icache.ReadReq_misses::cpu.inst 85967 -system.cpu.icache.ReadReq_misses::total 85967 -system.cpu.icache.demand_misses::cpu.inst 85967 -system.cpu.icache.demand_misses::total 85967 -system.cpu.icache.overall_misses::cpu.inst 85967 -system.cpu.icache.overall_misses::total 85967 -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 -system.cpu.icache.ReadReq_miss_latency::total 1954653197 -system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 -system.cpu.icache.demand_miss_latency::total 1954653197 -system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 -system.cpu.icache.overall_miss_latency::total 1954653197 -system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 -system.cpu.icache.ReadReq_accesses::total 235109772 -system.cpu.icache.demand_accesses::cpu.inst 235109772 -system.cpu.icache.demand_accesses::total 235109772 -system.cpu.icache.overall_accesses::cpu.inst 235109772 -system.cpu.icache.overall_accesses::total 235109772 -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 -system.cpu.icache.ReadReq_miss_rate::total 0.000366 -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 -system.cpu.icache.demand_miss_rate::total 0.000366 -system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 -system.cpu.icache.overall_miss_rate::total 0.000366 -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 -system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 -system.cpu.icache.demand_avg_miss_latency::total 22737.250305 -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 -system.cpu.icache.overall_avg_miss_latency::total 22737.250305 -system.cpu.icache.blocked_cycles::no_mshrs 201943 -system.cpu.icache.blocked_cycles::no_targets 336 -system.cpu.icache.blocked::no_mshrs 7203 -system.cpu.icache.blocked::no_targets 8 -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 -system.cpu.icache.avg_blocked_cycles::no_targets 42 -system.cpu.icache.writebacks::writebacks 76537 -system.cpu.icache.writebacks::total 76537 -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 -system.cpu.icache.ReadReq_mshr_hits::total 8885 -system.cpu.icache.demand_mshr_hits::cpu.inst 8885 -system.cpu.icache.demand_mshr_hits::total 8885 -system.cpu.icache.overall_mshr_hits::cpu.inst 8885 -system.cpu.icache.overall_mshr_hits::total 8885 -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 -system.cpu.icache.ReadReq_mshr_misses::total 77082 -system.cpu.icache.demand_mshr_misses::cpu.inst 77082 -system.cpu.icache.demand_mshr_misses::total 77082 -system.cpu.icache.overall_mshr_misses::cpu.inst 77082 -system.cpu.icache.overall_mshr_misses::total 77082 -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 -system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 -system.cpu.icache.demand_mshr_miss_latency::total 1551815800 -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 -system.cpu.icache.overall_mshr_miss_latency::total 1551815800 -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 -system.cpu.icache.demand_mshr_miss_rate::total 0.000328 -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 -system.cpu.icache.overall_mshr_miss_rate::total 0.000328 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 -system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 -system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 -system.cpu.l2cache.prefetcher.pfIdentified 8515198 -system.cpu.l2cache.prefetcher.pfBufferHit 454 -system.cpu.l2cache.prefetcher.pfInCache 0 -system.cpu.l2cache.prefetcher.pfRemovedFull 0 -system.cpu.l2cache.prefetcher.pfSpanPage 744250 -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.l2cache.tags.replacements 390446 -system.cpu.l2cache.tags.tagsinuse 15006.522104 -system.cpu.l2cache.tags.total_refs 2698185 -system.cpu.l2cache.tags.sampled_refs 406039 -system.cpu.l2cache.tags.avg_refs 6.645138 -system.cpu.l2cache.tags.warmup_cycle 0 -system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 -system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 -system.cpu.l2cache.tags.occ_percent::total 0.915925 -system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 -system.cpu.l2cache.tags.tag_accesses 95374967 -system.cpu.l2cache.tags.data_accesses 95374967 -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 -system.cpu.l2cache.WritebackDirty_hits::total 2350430 -system.cpu.l2cache.WritebackClean_hits::writebacks 520007 -system.cpu.l2cache.WritebackClean_hits::total 520007 -system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 -system.cpu.l2cache.ReadExReq_hits::total 516734 -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 -system.cpu.l2cache.ReadCleanReq_hits::total 66859 -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 -system.cpu.l2cache.ReadSharedReq_hits::total 2131098 -system.cpu.l2cache.demand_hits::cpu.inst 66859 -system.cpu.l2cache.demand_hits::cpu.data 2647832 -system.cpu.l2cache.demand_hits::total 2714691 -system.cpu.l2cache.overall_hits::cpu.inst 66859 -system.cpu.l2cache.overall_hits::cpu.data 2647832 -system.cpu.l2cache.overall_hits::total 2714691 -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 -system.cpu.l2cache.UpgradeReq_misses::total 33 -system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 -system.cpu.l2cache.ReadExReq_misses::total 5281 -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 -system.cpu.l2cache.ReadCleanReq_misses::total 10187 -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 -system.cpu.l2cache.ReadSharedReq_misses::total 164879 -system.cpu.l2cache.demand_misses::cpu.inst 10187 -system.cpu.l2cache.demand_misses::cpu.data 170160 -system.cpu.l2cache.demand_misses::total 180347 -system.cpu.l2cache.overall_misses::cpu.inst 10187 -system.cpu.l2cache.overall_misses::cpu.data 170160 -system.cpu.l2cache.overall_misses::total 180347 -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 -system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 -system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 -system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 -system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 -system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 -system.cpu.l2cache.demand_miss_latency::total 17029812500 -system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 -system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 -system.cpu.l2cache.overall_miss_latency::total 17029812500 -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 -system.cpu.l2cache.WritebackDirty_accesses::total 2350430 -system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 -system.cpu.l2cache.WritebackClean_accesses::total 520007 -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 -system.cpu.l2cache.UpgradeReq_accesses::total 33 -system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 -system.cpu.l2cache.ReadExReq_accesses::total 522015 -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 -system.cpu.l2cache.ReadCleanReq_accesses::total 77046 -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 -system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 -system.cpu.l2cache.demand_accesses::cpu.inst 77046 -system.cpu.l2cache.demand_accesses::cpu.data 2817992 -system.cpu.l2cache.demand_accesses::total 2895038 -system.cpu.l2cache.overall_accesses::cpu.inst 77046 -system.cpu.l2cache.overall_accesses::cpu.data 2817992 -system.cpu.l2cache.overall_accesses::total 2895038 -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 -system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 -system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 -system.cpu.l2cache.demand_miss_rate::total 0.062295 -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 -system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 -system.cpu.l2cache.overall_miss_rate::total 0.062295 -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 -system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 -system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 -system.cpu.l2cache.blocked_cycles::no_mshrs 349 -system.cpu.l2cache.blocked_cycles::no_targets 0 -system.cpu.l2cache.blocked::no_mshrs 1 -system.cpu.l2cache.blocked::no_targets 0 -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 -system.cpu.l2cache.avg_blocked_cycles::no_targets nan -system.cpu.l2cache.unused_prefetches 1991 -system.cpu.l2cache.writebacks::writebacks 291460 -system.cpu.l2cache.writebacks::total 291460 -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 -system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 -system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 -system.cpu.l2cache.demand_mshr_hits::total 6142 -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 -system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 -system.cpu.l2cache.overall_mshr_hits::total 6142 -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 -system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 -system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 -system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 -system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 -system.cpu.l2cache.demand_mshr_misses::total 174205 -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 -system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 -system.cpu.l2cache.overall_mshr_misses::total 530331 -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 -system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 -system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 -system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 -system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.cpu.toL2Bus.trans_dist::ReadResp 2373057 -system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 -system.cpu.toL2Bus.trans_dist::WritebackClean 543587 -system.cpu.toL2Bus.trans_dist::CleanEvict 98986 -system.cpu.toL2Bus.trans_dist::HardPFReq 403295 -system.cpu.toL2Bus.trans_dist::HardPFResp 1 -system.cpu.toL2Bus.trans_dist::UpgradeReq 33 -system.cpu.toL2Bus.trans_dist::UpgradeResp 33 -system.cpu.toL2Bus.trans_dist::ReadExReq 522015 -system.cpu.toL2Bus.trans_dist::ReadExResp 522015 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 -system.cpu.toL2Bus.pkt_count::total 8684194 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 -system.cpu.toL2Bus.pkt_size::total 370499456 -system.cpu.toL2Bus.snoops 793778 -system.cpu.toL2Bus.snoopTraffic 18655808 -system.cpu.toL2Bus.snoop_fanout::samples 3688848 -system.cpu.toL2Bus.snoop_fanout::mean 0.034290 -system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% -system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% -system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 2 -system.cpu.toL2Bus.snoop_fanout::total 3688848 -system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 -system.cpu.toL2Bus.reqLayer0.utilization 2.5 -system.cpu.toL2Bus.snoopLayer0.occupancy 1506 -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer0.occupancy 115655928 -system.cpu.toL2Bus.respLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer1.occupancy 4227026456 -system.cpu.toL2Bus.respLayer1.utilization 1.8 -system.membus.snoop_filter.tot_requests 821093 -system.membus.snoop_filter.hit_single_requests 414041 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 -system.membus.trans_dist::ReadResp 426929 -system.membus.trans_dist::WritebackDirty 291460 -system.membus.trans_dist::CleanEvict 98986 -system.membus.trans_dist::UpgradeReq 36 -system.membus.trans_dist::ReadExReq 3681 -system.membus.trans_dist::ReadExResp 3681 -system.membus.trans_dist::ReadSharedReq 426930 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 -system.membus.pkt_count::total 1251703 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 -system.membus.pkt_size::total 46212480 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 430647 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 430647 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 430647 -system.membus.reqLayer0.occupancy 2213026745 -system.membus.reqLayer0.utilization 0.9 -system.membus.respLayer1.occupancy 2279181090 -system.membus.respLayer1.utilization 1.0 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index bd579b4cb..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,330 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index 094173d40..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index a36e35467..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,70 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 17:56:13 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 279360903000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index 30c0da648..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,262 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.279361 -sim_ticks 279360903000 -final_tick 279360903000 -sim_freq 1000000000000 -host_inst_rate 937755 -host_op_rate 1015713 -host_tick_rate 517139598 -host_mem_usage 274756 -host_seconds 540.20 -sim_insts 506578818 -sim_ops 548692039 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.physmem.bytes_read::cpu.inst 2066434344 -system.physmem.bytes_read::cpu.data 422848347 -system.physmem.bytes_read::total 2489282691 -system.physmem.bytes_inst_read::cpu.inst 2066434344 -system.physmem.bytes_inst_read::total 2066434344 -system.physmem.bytes_written::cpu.data 216066596 -system.physmem.bytes_written::total 216066596 -system.physmem.num_reads::cpu.inst 516608586 -system.physmem.num_reads::cpu.data 115590054 -system.physmem.num_reads::total 632198640 -system.physmem.num_writes::cpu.data 55727590 -system.physmem.num_writes::total 55727590 -system.physmem.bw_read::cpu.inst 7397006245 -system.physmem.bw_read::cpu.data 1513627506 -system.physmem.bw_read::total 8910633751 -system.physmem.bw_inst_read::cpu.inst 7397006245 -system.physmem.bw_inst_read::total 7397006245 -system.physmem.bw_write::cpu.data 773431764 -system.physmem.bw_write::total 773431764 -system.physmem.bw_total::cpu.inst 7397006245 -system.physmem.bw_total::cpu.data 2287059270 -system.physmem.bw_total::total 9684065515 -system.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.hits 0 -system.cpu.istage2_mmu.stage2_tlb.misses 0 -system.cpu.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.cpu.itb.walker.walks 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.itb.walker.walkRequestOrigin::total 0 -system.cpu.itb.inst_hits 0 -system.cpu.itb.inst_misses 0 -system.cpu.itb.read_hits 0 -system.cpu.itb.read_misses 0 -system.cpu.itb.write_hits 0 -system.cpu.itb.write_misses 0 -system.cpu.itb.flush_tlb 0 -system.cpu.itb.flush_tlb_mva 0 -system.cpu.itb.flush_tlb_mva_asid 0 -system.cpu.itb.flush_tlb_asid 0 -system.cpu.itb.flush_entries 0 -system.cpu.itb.align_faults 0 -system.cpu.itb.prefetch_faults 0 -system.cpu.itb.domain_faults 0 -system.cpu.itb.perms_faults 0 -system.cpu.itb.read_accesses 0 -system.cpu.itb.write_accesses 0 -system.cpu.itb.inst_accesses 0 -system.cpu.itb.hits 0 -system.cpu.itb.misses 0 -system.cpu.itb.accesses 0 -system.cpu.workload.numSyscalls 548 -system.cpu.pwrStateResidencyTicks::ON 279360903000 -system.cpu.numCycles 558721807 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 506578818 -system.cpu.committedOps 548692039 -system.cpu.num_int_alu_accesses 448447005 -system.cpu.num_fp_alu_accesses 16 -system.cpu.num_func_calls 19311615 -system.cpu.num_conditional_control_insts 90670594 -system.cpu.num_int_insts 448447005 -system.cpu.num_fp_insts 16 -system.cpu.num_int_register_reads 749023721 -system.cpu.num_int_register_writes 289993515 -system.cpu.num_fp_register_reads 16 -system.cpu.num_fp_register_writes 0 -system.cpu.num_cc_register_reads 1634221880 -system.cpu.num_cc_register_writes 344062197 -system.cpu.num_mem_refs 172743505 -system.cpu.num_load_insts 115883283 -system.cpu.num_store_insts 56860222 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 558721807 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 121552863 -system.cpu.op_class::No_OpClass 0 0.00% 0.00% -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% -system.cpu.op_class::IntMult 339219 0.06% 68.52% -system.cpu.op_class::IntDiv 0 0.00% 68.52% -system.cpu.op_class::FloatAdd 0 0.00% 68.52% -system.cpu.op_class::FloatCmp 0 0.00% 68.52% -system.cpu.op_class::FloatCvt 0 0.00% 68.52% -system.cpu.op_class::FloatMult 0 0.00% 68.52% -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% -system.cpu.op_class::FloatDiv 0 0.00% 68.52% -system.cpu.op_class::FloatMisc 0 0.00% 68.52% -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% -system.cpu.op_class::SimdAdd 0 0.00% 68.52% -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% -system.cpu.op_class::SimdAlu 0 0.00% 68.52% -system.cpu.op_class::SimdCmp 0 0.00% 68.52% -system.cpu.op_class::SimdCvt 0 0.00% 68.52% -system.cpu.op_class::SimdMisc 0 0.00% 68.52% -system.cpu.op_class::SimdMult 0 0.00% 68.52% -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% -system.cpu.op_class::SimdShift 0 0.00% 68.52% -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% -system.cpu.op_class::MemRead 115883283 21.12% 89.64% -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 548692589 -system.membus.snoop_filter.tot_requests 0 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 -system.membus.trans_dist::ReadReq 630707528 -system.membus.trans_dist::ReadResp 632196069 -system.membus.trans_dist::WriteReq 54239049 -system.membus.trans_dist::WriteResp 54239049 -system.membus.trans_dist::SoftPFReq 2571 -system.membus.trans_dist::SoftPFResp 2571 -system.membus.trans_dist::LoadLockedReq 1488541 -system.membus.trans_dist::StoreCondReq 1488541 -system.membus.trans_dist::StoreCondResp 1488541 -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 -system.membus.pkt_count::total 1375852460 -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 -system.membus.pkt_size::total 2705349287 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 687926230 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 687926230 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 687926230 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index cd5fa2511..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,499 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index 094173d40..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout deleted file mode 100755 index e4542abd6..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,70 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 18:35:18 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 708700329500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 78d65a20d..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,685 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.708700 -sim_ticks 708700329500 -final_tick 708700329500 -sim_freq 1000000000000 -host_inst_rate 679420 -host_op_rate 735782 -host_tick_rate 953505845 -host_mem_usage 285772 -host_seconds 743.26 -sim_insts 504984064 -sim_ops 546875315 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.physmem.bytes_read::cpu.inst 147392 -system.physmem.bytes_read::cpu.data 8988096 -system.physmem.bytes_read::total 9135488 -system.physmem.bytes_inst_read::cpu.inst 147392 -system.physmem.bytes_inst_read::total 147392 -system.physmem.bytes_written::writebacks 6185472 -system.physmem.bytes_written::total 6185472 -system.physmem.num_reads::cpu.inst 2303 -system.physmem.num_reads::cpu.data 140439 -system.physmem.num_reads::total 142742 -system.physmem.num_writes::writebacks 96648 -system.physmem.num_writes::total 96648 -system.physmem.bw_read::cpu.inst 207975 -system.physmem.bw_read::cpu.data 12682506 -system.physmem.bw_read::total 12890481 -system.physmem.bw_inst_read::cpu.inst 207975 -system.physmem.bw_inst_read::total 207975 -system.physmem.bw_write::writebacks 8727909 -system.physmem.bw_write::total 8727909 -system.physmem.bw_total::writebacks 8727909 -system.physmem.bw_total::cpu.inst 207975 -system.physmem.bw_total::cpu.data 12682506 -system.physmem.bw_total::total 21618390 -system.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.hits 0 -system.cpu.istage2_mmu.stage2_tlb.misses 0 -system.cpu.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.itb.walker.walks 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.itb.walker.walkRequestOrigin::total 0 -system.cpu.itb.inst_hits 0 -system.cpu.itb.inst_misses 0 -system.cpu.itb.read_hits 0 -system.cpu.itb.read_misses 0 -system.cpu.itb.write_hits 0 -system.cpu.itb.write_misses 0 -system.cpu.itb.flush_tlb 0 -system.cpu.itb.flush_tlb_mva 0 -system.cpu.itb.flush_tlb_mva_asid 0 -system.cpu.itb.flush_tlb_asid 0 -system.cpu.itb.flush_entries 0 -system.cpu.itb.align_faults 0 -system.cpu.itb.prefetch_faults 0 -system.cpu.itb.domain_faults 0 -system.cpu.itb.perms_faults 0 -system.cpu.itb.read_accesses 0 -system.cpu.itb.write_accesses 0 -system.cpu.itb.inst_accesses 0 -system.cpu.itb.hits 0 -system.cpu.itb.misses 0 -system.cpu.itb.accesses 0 -system.cpu.workload.numSyscalls 548 -system.cpu.pwrStateResidencyTicks::ON 708700329500 -system.cpu.numCycles 1417400659 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 504984064 -system.cpu.committedOps 546875315 -system.cpu.num_int_alu_accesses 448447005 -system.cpu.num_fp_alu_accesses 16 -system.cpu.num_func_calls 19311615 -system.cpu.num_conditional_control_insts 90670594 -system.cpu.num_int_insts 448447005 -system.cpu.num_fp_insts 16 -system.cpu.num_int_register_reads 748339627 -system.cpu.num_int_register_writes 289993515 -system.cpu.num_fp_register_reads 16 -system.cpu.num_fp_register_writes 0 -system.cpu.num_cc_register_reads 1984285070 -system.cpu.num_cc_register_writes 344062197 -system.cpu.num_mem_refs 172743505 -system.cpu.num_load_insts 115883283 -system.cpu.num_store_insts 56860222 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 1417400659 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 121552863 -system.cpu.op_class::No_OpClass 0 0.00% 0.00% -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% -system.cpu.op_class::IntMult 339219 0.06% 68.52% -system.cpu.op_class::IntDiv 0 0.00% 68.52% -system.cpu.op_class::FloatAdd 0 0.00% 68.52% -system.cpu.op_class::FloatCmp 0 0.00% 68.52% -system.cpu.op_class::FloatCvt 0 0.00% 68.52% -system.cpu.op_class::FloatMult 0 0.00% 68.52% -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% -system.cpu.op_class::FloatDiv 0 0.00% 68.52% -system.cpu.op_class::FloatMisc 0 0.00% 68.52% -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% -system.cpu.op_class::SimdAdd 0 0.00% 68.52% -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% -system.cpu.op_class::SimdAlu 0 0.00% 68.52% -system.cpu.op_class::SimdCmp 0 0.00% 68.52% -system.cpu.op_class::SimdCvt 0 0.00% 68.52% -system.cpu.op_class::SimdMisc 0 0.00% 68.52% -system.cpu.op_class::SimdMult 0 0.00% 68.52% -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% -system.cpu.op_class::SimdShift 0 0.00% 68.52% -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% -system.cpu.op_class::MemRead 115883283 21.12% 89.64% -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 548692589 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dcache.tags.replacements 1136276 -system.cpu.dcache.tags.tagsinuse 4065.253828 -system.cpu.dcache.tags.total_refs 170177272 -system.cpu.dcache.tags.sampled_refs 1140372 -system.cpu.dcache.tags.avg_refs 149.229613 -system.cpu.dcache.tags.warmup_cycle 11754931500 -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 -system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 -system.cpu.dcache.tags.occ_percent::total 0.992494 -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 -system.cpu.dcache.tags.occ_task_id_percent::1024 1 -system.cpu.dcache.tags.tag_accesses 343775660 -system.cpu.dcache.tags.data_accesses 343775660 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dcache.ReadReq_hits::cpu.data 113315079 -system.cpu.dcache.ReadReq_hits::total 113315079 -system.cpu.dcache.WriteReq_hits::cpu.data 53882541 -system.cpu.dcache.WriteReq_hits::total 53882541 -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 -system.cpu.dcache.SoftPFReq_hits::total 2570 -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 -system.cpu.dcache.LoadLockedReq_hits::total 1488541 -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 -system.cpu.dcache.StoreCondReq_hits::total 1488541 -system.cpu.dcache.demand_hits::cpu.data 167197620 -system.cpu.dcache.demand_hits::total 167197620 -system.cpu.dcache.overall_hits::cpu.data 167200190 -system.cpu.dcache.overall_hits::total 167200190 -system.cpu.dcache.ReadReq_misses::cpu.data 783863 -system.cpu.dcache.ReadReq_misses::total 783863 -system.cpu.dcache.WriteReq_misses::cpu.data 356508 -system.cpu.dcache.WriteReq_misses::total 356508 -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 -system.cpu.dcache.SoftPFReq_misses::total 1 -system.cpu.dcache.demand_misses::cpu.data 1140371 -system.cpu.dcache.demand_misses::total 1140371 -system.cpu.dcache.overall_misses::cpu.data 1140372 -system.cpu.dcache.overall_misses::total 1140372 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 -system.cpu.dcache.ReadReq_miss_latency::total 12176129500 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 -system.cpu.dcache.WriteReq_miss_latency::total 9680337500 -system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 -system.cpu.dcache.demand_miss_latency::total 21856467000 -system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 -system.cpu.dcache.overall_miss_latency::total 21856467000 -system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 -system.cpu.dcache.ReadReq_accesses::total 114098942 -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 -system.cpu.dcache.WriteReq_accesses::total 54239049 -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 -system.cpu.dcache.SoftPFReq_accesses::total 2571 -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 -system.cpu.dcache.StoreCondReq_accesses::total 1488541 -system.cpu.dcache.demand_accesses::cpu.data 168337991 -system.cpu.dcache.demand_accesses::total 168337991 -system.cpu.dcache.overall_accesses::cpu.data 168340562 -system.cpu.dcache.overall_accesses::total 168340562 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 -system.cpu.dcache.ReadReq_miss_rate::total 0.006870 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 -system.cpu.dcache.WriteReq_miss_rate::total 0.006573 -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 -system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 -system.cpu.dcache.demand_miss_rate::total 0.006774 -system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 -system.cpu.dcache.overall_miss_rate::total 0.006774 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 -system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 -system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 -system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 -system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 -system.cpu.dcache.blocked_cycles::no_mshrs 0 -system.cpu.dcache.blocked_cycles::no_targets 0 -system.cpu.dcache.blocked::no_mshrs 0 -system.cpu.dcache.blocked::no_targets 0 -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan -system.cpu.dcache.avg_blocked_cycles::no_targets nan -system.cpu.dcache.writebacks::writebacks 1065429 -system.cpu.dcache.writebacks::total 1065429 -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 -system.cpu.dcache.ReadReq_mshr_misses::total 783863 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 -system.cpu.dcache.WriteReq_mshr_misses::total 356508 -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 -system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 -system.cpu.dcache.demand_mshr_misses::total 1140371 -system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 -system.cpu.dcache.overall_mshr_misses::total 1140372 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 -system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 -system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 -system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 -system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.icache.tags.replacements 9788 -system.cpu.icache.tags.tagsinuse 983.167360 -system.cpu.icache.tags.total_refs 516597066 -system.cpu.icache.tags.sampled_refs 11521 -system.cpu.icache.tags.avg_refs 44839.602986 -system.cpu.icache.tags.warmup_cycle 0 -system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 -system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 -system.cpu.icache.tags.occ_percent::total 0.480062 -system.cpu.icache.tags.occ_task_id_blocks::1024 1733 -system.cpu.icache.tags.age_task_id_blocks_1024::0 27 -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 -system.cpu.icache.tags.age_task_id_blocks_1024::2 24 -system.cpu.icache.tags.age_task_id_blocks_1024::3 256 -system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 -system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 -system.cpu.icache.tags.tag_accesses 1033228695 -system.cpu.icache.tags.data_accesses 1033228695 -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.icache.ReadReq_hits::cpu.inst 516597066 -system.cpu.icache.ReadReq_hits::total 516597066 -system.cpu.icache.demand_hits::cpu.inst 516597066 -system.cpu.icache.demand_hits::total 516597066 -system.cpu.icache.overall_hits::cpu.inst 516597066 -system.cpu.icache.overall_hits::total 516597066 -system.cpu.icache.ReadReq_misses::cpu.inst 11521 -system.cpu.icache.ReadReq_misses::total 11521 -system.cpu.icache.demand_misses::cpu.inst 11521 -system.cpu.icache.demand_misses::total 11521 -system.cpu.icache.overall_misses::cpu.inst 11521 -system.cpu.icache.overall_misses::total 11521 -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 -system.cpu.icache.ReadReq_miss_latency::total 265513000 -system.cpu.icache.demand_miss_latency::cpu.inst 265513000 -system.cpu.icache.demand_miss_latency::total 265513000 -system.cpu.icache.overall_miss_latency::cpu.inst 265513000 -system.cpu.icache.overall_miss_latency::total 265513000 -system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 -system.cpu.icache.ReadReq_accesses::total 516608587 -system.cpu.icache.demand_accesses::cpu.inst 516608587 -system.cpu.icache.demand_accesses::total 516608587 -system.cpu.icache.overall_accesses::cpu.inst 516608587 -system.cpu.icache.overall_accesses::total 516608587 -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 -system.cpu.icache.ReadReq_miss_rate::total 0.000022 -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 -system.cpu.icache.demand_miss_rate::total 0.000022 -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 -system.cpu.icache.overall_miss_rate::total 0.000022 -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 -system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 -system.cpu.icache.demand_avg_miss_latency::total 23046.002951 -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 -system.cpu.icache.overall_avg_miss_latency::total 23046.002951 -system.cpu.icache.blocked_cycles::no_mshrs 0 -system.cpu.icache.blocked_cycles::no_targets 0 -system.cpu.icache.blocked::no_mshrs 0 -system.cpu.icache.blocked::no_targets 0 -system.cpu.icache.avg_blocked_cycles::no_mshrs nan -system.cpu.icache.avg_blocked_cycles::no_targets nan -system.cpu.icache.writebacks::writebacks 9788 -system.cpu.icache.writebacks::total 9788 -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 -system.cpu.icache.ReadReq_mshr_misses::total 11521 -system.cpu.icache.demand_mshr_misses::cpu.inst 11521 -system.cpu.icache.demand_mshr_misses::total 11521 -system.cpu.icache.overall_mshr_misses::cpu.inst 11521 -system.cpu.icache.overall_mshr_misses::total 11521 -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 -system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 -system.cpu.icache.demand_mshr_miss_latency::total 253992000 -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 -system.cpu.icache.overall_mshr_miss_latency::total 253992000 -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 -system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 -system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.l2cache.tags.replacements 110813 -system.cpu.l2cache.tags.tagsinuse 28700.010798 -system.cpu.l2cache.tags.total_refs 2150809 -system.cpu.l2cache.tags.sampled_refs 143581 -system.cpu.l2cache.tags.avg_refs 14.979761 -system.cpu.l2cache.tags.warmup_cycle 210357436000 -system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 -system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 -system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 -system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 -system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 -system.cpu.l2cache.tags.occ_percent::total 0.875855 -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 -system.cpu.l2cache.tags.tag_accesses 18498717 -system.cpu.l2cache.tags.data_accesses 18498717 -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 -system.cpu.l2cache.WritebackDirty_hits::total 1065429 -system.cpu.l2cache.WritebackClean_hits::writebacks 9751 -system.cpu.l2cache.WritebackClean_hits::total 9751 -system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 -system.cpu.l2cache.ReadExReq_hits::total 255675 -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 -system.cpu.l2cache.ReadCleanReq_hits::total 9218 -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 -system.cpu.l2cache.ReadSharedReq_hits::total 744258 -system.cpu.l2cache.demand_hits::cpu.inst 9218 -system.cpu.l2cache.demand_hits::cpu.data 999933 -system.cpu.l2cache.demand_hits::total 1009151 -system.cpu.l2cache.overall_hits::cpu.inst 9218 -system.cpu.l2cache.overall_hits::cpu.data 999933 -system.cpu.l2cache.overall_hits::total 1009151 -system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 -system.cpu.l2cache.ReadExReq_misses::total 100833 -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 -system.cpu.l2cache.ReadCleanReq_misses::total 2303 -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 -system.cpu.l2cache.ReadSharedReq_misses::total 39606 -system.cpu.l2cache.demand_misses::cpu.inst 2303 -system.cpu.l2cache.demand_misses::cpu.data 140439 -system.cpu.l2cache.demand_misses::total 142742 -system.cpu.l2cache.overall_misses::cpu.inst 2303 -system.cpu.l2cache.overall_misses::cpu.data 140439 -system.cpu.l2cache.overall_misses::total 142742 -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 -system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 -system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 -system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 -system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 -system.cpu.l2cache.demand_miss_latency::total 8642481500 -system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 -system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 -system.cpu.l2cache.overall_miss_latency::total 8642481500 -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 -system.cpu.l2cache.WritebackDirty_accesses::total 1065429 -system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 -system.cpu.l2cache.WritebackClean_accesses::total 9751 -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 -system.cpu.l2cache.ReadExReq_accesses::total 356508 -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 -system.cpu.l2cache.ReadCleanReq_accesses::total 11521 -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 -system.cpu.l2cache.ReadSharedReq_accesses::total 783864 -system.cpu.l2cache.demand_accesses::cpu.inst 11521 -system.cpu.l2cache.demand_accesses::cpu.data 1140372 -system.cpu.l2cache.demand_accesses::total 1151893 -system.cpu.l2cache.overall_accesses::cpu.inst 11521 -system.cpu.l2cache.overall_accesses::cpu.data 1140372 -system.cpu.l2cache.overall_accesses::total 1151893 -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 -system.cpu.l2cache.demand_miss_rate::total 0.123919 -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 -system.cpu.l2cache.overall_miss_rate::total 0.123919 -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 -system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 -system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 -system.cpu.l2cache.blocked_cycles::no_mshrs 0 -system.cpu.l2cache.blocked_cycles::no_targets 0 -system.cpu.l2cache.blocked::no_mshrs 0 -system.cpu.l2cache.blocked::no_targets 0 -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan -system.cpu.l2cache.avg_blocked_cycles::no_targets nan -system.cpu.l2cache.writebacks::writebacks 96648 -system.cpu.l2cache.writebacks::total 96648 -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 -system.cpu.l2cache.CleanEvict_mshr_misses::total 2 -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 -system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 -system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 -system.cpu.l2cache.demand_mshr_misses::total 142742 -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 -system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 -system.cpu.l2cache.overall_mshr_misses::total 142742 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 -system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 -system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 -system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 -system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.toL2Bus.trans_dist::ReadResp 795385 -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 -system.cpu.toL2Bus.trans_dist::WritebackClean 9788 -system.cpu.toL2Bus.trans_dist::CleanEvict 85012 -system.cpu.toL2Bus.trans_dist::ReadExReq 356508 -system.cpu.toL2Bus.trans_dist::ReadExResp 356508 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 -system.cpu.toL2Bus.pkt_count::total 3449850 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 -system.cpu.toL2Bus.pkt_size::total 142535040 -system.cpu.toL2Bus.snoops 110813 -system.cpu.toL2Bus.snoopTraffic 6185472 -system.cpu.toL2Bus.snoop_fanout::samples 1262706 -system.cpu.toL2Bus.snoop_fanout::mean 0.004570 -system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% -system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 2 -system.cpu.toL2Bus.snoop_fanout::total 1262706 -system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 -system.cpu.toL2Bus.reqLayer0.utilization 0.3 -system.cpu.toL2Bus.respLayer0.occupancy 17281500 -system.cpu.toL2Bus.respLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer1.occupancy 1710558000 -system.cpu.toL2Bus.respLayer1.utilization 0.2 -system.membus.snoop_filter.tot_requests 251405 -system.membus.snoop_filter.hit_single_requests 108784 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.membus.trans_dist::ReadResp 41909 -system.membus.trans_dist::WritebackDirty 96648 -system.membus.trans_dist::CleanEvict 12014 -system.membus.trans_dist::ReadExReq 100833 -system.membus.trans_dist::ReadExResp 100833 -system.membus.trans_dist::ReadSharedReq 41909 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 -system.membus.pkt_count::total 394146 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 -system.membus.pkt_size::total 15320960 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 142743 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 142743 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 142743 -system.membus.reqLayer0.occupancy 644372828 -system.membus.reqLayer0.utilization 0.1 -system.membus.respLayer1.occupancy 713710000 -system.membus.respLayer1.utilization 0.1 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini deleted file mode 100644 index a38a74511..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ /dev/null @@ -1,924 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kvm_vm=Null -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cacheStorePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=true -numIQEntries=64 -numPhysCCRegs=1280 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=1 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 opList3 opList4 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList3.opList3] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList4] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 opList1 -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList4.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 opList2 opList3 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatMemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList3] -type=OpDesc -eventq_index=0 -opClass=FloatMemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_latency=1000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -power_model=Null -system=system -int_master=system.membus.slave[2] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr deleted file mode 100755 index 630e657e6..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ /dev/null @@ -1,18 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout deleted file mode 100755 index e7ed8f409..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ /dev/null @@ -1,71 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 19:05:53 -gem5 started Apr 3 2017 19:06:22 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - 58924 words stored in 3784810 bytes - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 487050729500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt deleted file mode 100644 index 72edf9459..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ /dev/null @@ -1,1092 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.487051 -sim_ticks 487050729500 -final_tick 487050729500 -sim_freq 1000000000000 -host_inst_rate 109718 -host_op_rate 203033 -host_tick_rate 64628655 -host_mem_usage 330116 -host_seconds 7536.14 -sim_insts 826847303 -sim_ops 1530082520 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.physmem.bytes_read::cpu.inst 156352 -system.physmem.bytes_read::cpu.data 24658560 -system.physmem.bytes_read::total 24814912 -system.physmem.bytes_inst_read::cpu.inst 156352 -system.physmem.bytes_inst_read::total 156352 -system.physmem.bytes_written::writebacks 18911424 -system.physmem.bytes_written::total 18911424 -system.physmem.num_reads::cpu.inst 2443 -system.physmem.num_reads::cpu.data 385290 -system.physmem.num_reads::total 387733 -system.physmem.num_writes::writebacks 295491 -system.physmem.num_writes::total 295491 -system.physmem.bw_read::cpu.inst 321018 -system.physmem.bw_read::cpu.data 50628320 -system.physmem.bw_read::total 50949338 -system.physmem.bw_inst_read::cpu.inst 321018 -system.physmem.bw_inst_read::total 321018 -system.physmem.bw_write::writebacks 38828448 -system.physmem.bw_write::total 38828448 -system.physmem.bw_total::writebacks 38828448 -system.physmem.bw_total::cpu.inst 321018 -system.physmem.bw_total::cpu.data 50628320 -system.physmem.bw_total::total 89777786 -system.physmem.readReqs 387733 -system.physmem.writeReqs 295491 -system.physmem.readBursts 387733 -system.physmem.writeBursts 295491 -system.physmem.bytesReadDRAM 24795072 -system.physmem.bytesReadWrQ 19840 -system.physmem.bytesWritten 18909504 -system.physmem.bytesReadSys 24814912 -system.physmem.bytesWrittenSys 18911424 -system.physmem.servicedByWrQ 310 -system.physmem.mergedWrBursts 0 -system.physmem.neitherReadNorWriteReqs 0 -system.physmem.perBankRdBursts::0 24612 -system.physmem.perBankRdBursts::1 26389 -system.physmem.perBankRdBursts::2 24828 -system.physmem.perBankRdBursts::3 24571 -system.physmem.perBankRdBursts::4 23534 -system.physmem.perBankRdBursts::5 23661 -system.physmem.perBankRdBursts::6 24754 -system.physmem.perBankRdBursts::7 24509 -system.physmem.perBankRdBursts::8 23888 -system.physmem.perBankRdBursts::9 23557 -system.physmem.perBankRdBursts::10 24834 -system.physmem.perBankRdBursts::11 24002 -system.physmem.perBankRdBursts::12 23243 -system.physmem.perBankRdBursts::13 22894 -system.physmem.perBankRdBursts::14 23905 -system.physmem.perBankRdBursts::15 24242 -system.physmem.perBankWrBursts::0 18972 -system.physmem.perBankWrBursts::1 19954 -system.physmem.perBankWrBursts::2 19038 -system.physmem.perBankWrBursts::3 19006 -system.physmem.perBankWrBursts::4 18208 -system.physmem.perBankWrBursts::5 18444 -system.physmem.perBankWrBursts::6 19174 -system.physmem.perBankWrBursts::7 19116 -system.physmem.perBankWrBursts::8 18744 -system.physmem.perBankWrBursts::9 17955 -system.physmem.perBankWrBursts::10 18923 -system.physmem.perBankWrBursts::11 17774 -system.physmem.perBankWrBursts::12 17399 -system.physmem.perBankWrBursts::13 16985 -system.physmem.perBankWrBursts::14 17804 -system.physmem.perBankWrBursts::15 17965 -system.physmem.numRdRetry 0 -system.physmem.numWrRetry 0 -system.physmem.totGap 487050613500 -system.physmem.readPktSize::0 0 -system.physmem.readPktSize::1 0 -system.physmem.readPktSize::2 0 -system.physmem.readPktSize::3 0 -system.physmem.readPktSize::4 0 -system.physmem.readPktSize::5 0 -system.physmem.readPktSize::6 387733 -system.physmem.writePktSize::0 0 -system.physmem.writePktSize::1 0 -system.physmem.writePktSize::2 0 -system.physmem.writePktSize::3 0 -system.physmem.writePktSize::4 0 -system.physmem.writePktSize::5 0 -system.physmem.writePktSize::6 295491 -system.physmem.rdQLenPdf::0 381263 -system.physmem.rdQLenPdf::1 5754 -system.physmem.rdQLenPdf::2 361 -system.physmem.rdQLenPdf::3 34 -system.physmem.rdQLenPdf::4 9 -system.physmem.rdQLenPdf::5 2 -system.physmem.rdQLenPdf::6 0 -system.physmem.rdQLenPdf::7 0 -system.physmem.rdQLenPdf::8 0 -system.physmem.rdQLenPdf::9 0 -system.physmem.rdQLenPdf::10 0 -system.physmem.rdQLenPdf::11 0 -system.physmem.rdQLenPdf::12 0 -system.physmem.rdQLenPdf::13 0 -system.physmem.rdQLenPdf::14 0 -system.physmem.rdQLenPdf::15 0 -system.physmem.rdQLenPdf::16 0 -system.physmem.rdQLenPdf::17 0 -system.physmem.rdQLenPdf::18 0 -system.physmem.rdQLenPdf::19 0 -system.physmem.rdQLenPdf::20 0 -system.physmem.rdQLenPdf::21 0 -system.physmem.rdQLenPdf::22 0 -system.physmem.rdQLenPdf::23 0 -system.physmem.rdQLenPdf::24 0 -system.physmem.rdQLenPdf::25 0 -system.physmem.rdQLenPdf::26 0 -system.physmem.rdQLenPdf::27 0 -system.physmem.rdQLenPdf::28 0 -system.physmem.rdQLenPdf::29 0 -system.physmem.rdQLenPdf::30 0 -system.physmem.rdQLenPdf::31 0 -system.physmem.wrQLenPdf::0 1 -system.physmem.wrQLenPdf::1 1 -system.physmem.wrQLenPdf::2 1 -system.physmem.wrQLenPdf::3 1 -system.physmem.wrQLenPdf::4 1 -system.physmem.wrQLenPdf::5 1 -system.physmem.wrQLenPdf::6 1 -system.physmem.wrQLenPdf::7 1 -system.physmem.wrQLenPdf::8 1 -system.physmem.wrQLenPdf::9 1 -system.physmem.wrQLenPdf::10 1 -system.physmem.wrQLenPdf::11 1 -system.physmem.wrQLenPdf::12 1 -system.physmem.wrQLenPdf::13 1 -system.physmem.wrQLenPdf::14 1 -system.physmem.wrQLenPdf::15 6088 -system.physmem.wrQLenPdf::16 6353 -system.physmem.wrQLenPdf::17 17482 -system.physmem.wrQLenPdf::18 17661 -system.physmem.wrQLenPdf::19 17684 -system.physmem.wrQLenPdf::20 17682 -system.physmem.wrQLenPdf::21 17687 -system.physmem.wrQLenPdf::22 17686 -system.physmem.wrQLenPdf::23 17693 -system.physmem.wrQLenPdf::24 17689 -system.physmem.wrQLenPdf::25 17695 -system.physmem.wrQLenPdf::26 17698 -system.physmem.wrQLenPdf::27 17697 -system.physmem.wrQLenPdf::28 17702 -system.physmem.wrQLenPdf::29 17729 -system.physmem.wrQLenPdf::30 17821 -system.physmem.wrQLenPdf::31 17712 -system.physmem.wrQLenPdf::32 17704 -system.physmem.wrQLenPdf::33 7 -system.physmem.wrQLenPdf::34 4 -system.physmem.wrQLenPdf::35 2 -system.physmem.wrQLenPdf::36 0 -system.physmem.wrQLenPdf::37 0 -system.physmem.wrQLenPdf::38 0 -system.physmem.wrQLenPdf::39 0 -system.physmem.wrQLenPdf::40 0 -system.physmem.wrQLenPdf::41 0 -system.physmem.wrQLenPdf::42 0 -system.physmem.wrQLenPdf::43 0 -system.physmem.wrQLenPdf::44 0 -system.physmem.wrQLenPdf::45 0 -system.physmem.wrQLenPdf::46 0 -system.physmem.wrQLenPdf::47 0 -system.physmem.wrQLenPdf::48 0 -system.physmem.wrQLenPdf::49 0 -system.physmem.wrQLenPdf::50 0 -system.physmem.wrQLenPdf::51 0 -system.physmem.wrQLenPdf::52 0 -system.physmem.wrQLenPdf::53 0 -system.physmem.wrQLenPdf::54 0 -system.physmem.wrQLenPdf::55 0 -system.physmem.wrQLenPdf::56 0 -system.physmem.wrQLenPdf::57 0 -system.physmem.wrQLenPdf::58 0 -system.physmem.wrQLenPdf::59 0 -system.physmem.wrQLenPdf::60 0 -system.physmem.wrQLenPdf::61 0 -system.physmem.wrQLenPdf::62 0 -system.physmem.wrQLenPdf::63 0 -system.physmem.bytesPerActivate::samples 146416 -system.physmem.bytesPerActivate::mean 298.484100 -system.physmem.bytesPerActivate::gmean 176.719176 -system.physmem.bytesPerActivate::stdev 324.748192 -system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% -system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% -system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% -system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% -system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% -system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% -system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% -system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% -system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% -system.physmem.bytesPerActivate::total 146416 -system.physmem.rdPerTurnAround::samples 17678 -system.physmem.rdPerTurnAround::mean 21.914866 -system.physmem.rdPerTurnAround::gmean 18.161180 -system.physmem.rdPerTurnAround::stdev 216.039339 -system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% -system.physmem.rdPerTurnAround::total 17678 -system.physmem.wrPerTurnAround::samples 17678 -system.physmem.wrPerTurnAround::mean 16.713486 -system.physmem.wrPerTurnAround::gmean 16.686282 -system.physmem.wrPerTurnAround::stdev 0.965426 -system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% -system.physmem.wrPerTurnAround::17 269 1.52% 65.53% -system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% -system.physmem.wrPerTurnAround::19 123 0.70% 99.92% -system.physmem.wrPerTurnAround::20 10 0.06% 99.98% -system.physmem.wrPerTurnAround::21 3 0.02% 99.99% -system.physmem.wrPerTurnAround::22 1 0.01% 100.00% -system.physmem.wrPerTurnAround::total 17678 -system.physmem.totQLat 9794922250 -system.physmem.totMemAccLat 17059103500 -system.physmem.totBusLat 1937115000 -system.physmem.avgQLat 25282.24 -system.physmem.avgBusLat 5000.00 -system.physmem.avgMemAccLat 44032.24 -system.physmem.avgRdBW 50.91 -system.physmem.avgWrBW 38.82 -system.physmem.avgRdBWSys 50.95 -system.physmem.avgWrBWSys 38.83 -system.physmem.peakBW 12800.00 -system.physmem.busUtil 0.70 -system.physmem.busUtilRead 0.40 -system.physmem.busUtilWrite 0.30 -system.physmem.avgRdQLen 1.04 -system.physmem.avgWrQLen 20.96 -system.physmem.readRowHits 316322 -system.physmem.writeRowHits 220133 -system.physmem.readRowHitRate 81.65 -system.physmem.writeRowHitRate 74.50 -system.physmem.avgGap 712871.05 -system.physmem.pageHitRate 78.55 -system.physmem_0.actEnergy 538191780 -system.physmem_0.preEnergy 286032945 -system.physmem_0.readEnergy 1405566120 -system.physmem_0.writeEnergy 792980640 -system.physmem_0.refreshEnergy 13571251200.000004 -system.physmem_0.actBackEnergy 8851881120 -system.physmem_0.preBackEnergy 742850400 -system.physmem_0.actPowerDownEnergy 36305173020 -system.physmem_0.prePowerDownEnergy 16998972000 -system.physmem_0.selfRefreshEnergy 84070895340 -system.physmem_0.totalEnergy 163568832135 -system.physmem_0.averagePower 335.835307 -system.physmem_0.totalIdleTime 465691902250 -system.physmem_0.memoryStateTime::IDLE 1184996500 -system.physmem_0.memoryStateTime::REF 5763492000 -system.physmem_0.memoryStateTime::SREF 341808238000 -system.physmem_0.memoryStateTime::PRE_PDN 44268234250 -system.physmem_0.memoryStateTime::ACT 14409717250 -system.physmem_0.memoryStateTime::ACT_PDN 79616051500 -system.physmem_1.actEnergy 507311280 -system.physmem_1.preEnergy 269615775 -system.physmem_1.readEnergy 1360634100 -system.physmem_1.writeEnergy 749325780 -system.physmem_1.refreshEnergy 13094905200.000004 -system.physmem_1.actBackEnergy 8819547870 -system.physmem_1.preBackEnergy 717418080 -system.physmem_1.actPowerDownEnergy 34208424030 -system.physmem_1.prePowerDownEnergy 16648938720 -system.physmem_1.selfRefreshEnergy 85396744800 -system.physmem_1.totalEnergy 161777173725 -system.physmem_1.averagePower 332.156722 -system.physmem_1.totalIdleTime 465831856000 -system.physmem_1.memoryStateTime::IDLE 1145526000 -system.physmem_1.memoryStateTime::REF 5561926000 -system.physmem_1.memoryStateTime::SREF 347456670000 -system.physmem_1.memoryStateTime::PRE_PDN 43356567250 -system.physmem_1.memoryStateTime::ACT 14511269750 -system.physmem_1.memoryStateTime::ACT_PDN 75018770500 -system.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.branchPred.lookups 299198029 -system.cpu.branchPred.condPredicted 299198029 -system.cpu.branchPred.condIncorrect 24258277 -system.cpu.branchPred.BTBLookups 226066805 -system.cpu.branchPred.BTBHits 0 -system.cpu.branchPred.BTBCorrect 0 -system.cpu.branchPred.BTBHitPct 0.000000 -system.cpu.branchPred.usedRAS 40193400 -system.cpu.branchPred.RASInCorrect 4437789 -system.cpu.branchPred.indirectLookups 226066805 -system.cpu.branchPred.indirectHits 118144411 -system.cpu.branchPred.indirectMisses 107922394 -system.cpu.branchPredindirectMispredicted 11883156 -system.cpu_clk_domain.clock 500 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.apic_clk_domain.clock 8000 -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.workload.numSyscalls 551 -system.cpu.pwrStateResidencyTicks::ON 487050729500 -system.cpu.numCycles 974101460 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.fetch.icacheStallCycles 230169557 -system.cpu.fetch.Insts 1594277830 -system.cpu.fetch.Branches 299198029 -system.cpu.fetch.predictedBranches 158337811 -system.cpu.fetch.Cycles 718471067 -system.cpu.fetch.SquashCycles 49469998 -system.cpu.fetch.TlbCycles 2698 -system.cpu.fetch.MiscStallCycles 34945 -system.cpu.fetch.PendingTrapStallCycles 480096 -system.cpu.fetch.PendingQuiesceStallCycles 4714 -system.cpu.fetch.IcacheWaitRetryStallCycles 69 -system.cpu.fetch.CacheLines 216546560 -system.cpu.fetch.IcacheSquashes 6526632 -system.cpu.fetch.ItlbSquashes 8 -system.cpu.fetch.rateDist::samples 973898145 -system.cpu.fetch.rateDist::mean 3.063667 -system.cpu.fetch.rateDist::stdev 3.497102 -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% -system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% -system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% -system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% -system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% -system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% -system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% -system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% -system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% -system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% -system.cpu.fetch.rateDist::min_value 0 -system.cpu.fetch.rateDist::max_value 8 -system.cpu.fetch.rateDist::total 973898145 -system.cpu.fetch.branchRate 0.307153 -system.cpu.fetch.rate 1.636665 -system.cpu.decode.IdleCycles 166490369 -system.cpu.decode.BlockedCycles 388298779 -system.cpu.decode.RunCycles 313723542 -system.cpu.decode.UnblockCycles 80650456 -system.cpu.decode.SquashCycles 24734999 -system.cpu.decode.DecodedInsts 2751923456 -system.cpu.rename.SquashCycles 24734999 -system.cpu.rename.IdleCycles 202899221 -system.cpu.rename.BlockCycles 199700520 -system.cpu.rename.serializeStallCycles 14210 -system.cpu.rename.RunCycles 351959746 -system.cpu.rename.UnblockCycles 194589449 -system.cpu.rename.RenamedInsts 2631585273 -system.cpu.rename.ROBFullEvents 503822 -system.cpu.rename.IQFullEvents 119585114 -system.cpu.rename.LQFullEvents 21729790 -system.cpu.rename.SQFullEvents 44646970 -system.cpu.rename.RenamedOperands 2710512651 -system.cpu.rename.RenameLookups 6600728549 -system.cpu.rename.int_rename_lookups 4213051781 -system.cpu.rename.fp_rename_lookups 1976674 -system.cpu.rename.CommittedMaps 1616961572 -system.cpu.rename.UndoneMaps 1093551079 -system.cpu.rename.serializingInsts 884 -system.cpu.rename.tempSerializingInsts 794 -system.cpu.rename.skidInsts 367177164 -system.cpu.memDep0.insertedLoads 608809294 -system.cpu.memDep0.insertedStores 243550763 -system.cpu.memDep0.conflictingLoads 252688912 -system.cpu.memDep0.conflictingStores 75518257 -system.cpu.iq.iqInstsAdded 2418516015 -system.cpu.iq.iqNonSpecInstsAdded 104540 -system.cpu.iq.iqInstsIssued 1999668107 -system.cpu.iq.iqSquashedInstsIssued 3656750 -system.cpu.iq.iqSquashedInstsExamined 888538034 -system.cpu.iq.iqSquashedOperandsExamined 1505526254 -system.cpu.iq.iqSquashedNonSpecRemoved 103988 -system.cpu.iq.issued_per_cycle::samples 973898145 -system.cpu.iq.issued_per_cycle::mean 2.053262 -system.cpu.iq.issued_per_cycle::stdev 2.107501 -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% -system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% -system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% -system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% -system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% -system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% -system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% -system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% -system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% -system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% -system.cpu.iq.issued_per_cycle::min_value 0 -system.cpu.iq.issued_per_cycle::max_value 8 -system.cpu.iq.issued_per_cycle::total 973898145 -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% -system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% -system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% -system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% -system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% -system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% -system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% -system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% -system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% -system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% -system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% -system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% -system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% -system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% -system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% -system.cpu.iq.FU_type_0::total 1999668107 -system.cpu.iq.rate 2.052833 -system.cpu.iq.fu_busy_cnt 25900174 -system.cpu.iq.fu_busy_rate 0.012952 -system.cpu.iq.int_inst_queue_reads 5001578236 -system.cpu.iq.int_inst_queue_writes 3304560216 -system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 -system.cpu.iq.fp_inst_queue_reads 1213047 -system.cpu.iq.fp_inst_queue_writes 3212370 -system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 -system.cpu.iq.int_alu_accesses 2022120560 -system.cpu.iq.fp_alu_accesses 547346 -system.cpu.iew.lsq.thread0.forwLoads 180407023 -system.cpu.iew.lsq.thread0.invAddrLoads 0 -system.cpu.iew.lsq.thread0.squashedLoads 224726218 -system.cpu.iew.lsq.thread0.ignoredResponses 356451 -system.cpu.iew.lsq.thread0.memOrderViolation 693943 -system.cpu.iew.lsq.thread0.squashedStores 94392568 -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 -system.cpu.iew.lsq.thread0.blockedLoads 0 -system.cpu.iew.lsq.thread0.rescheduledLoads 33314 -system.cpu.iew.lsq.thread0.cacheBlocked 814 -system.cpu.iew.iewIdleCycles 0 -system.cpu.iew.iewSquashCycles 24734999 -system.cpu.iew.iewBlockCycles 149663879 -system.cpu.iew.iewUnblockCycles 6607902 -system.cpu.iew.iewDispatchedInsts 2418620555 -system.cpu.iew.iewDispSquashedInsts 1417513 -system.cpu.iew.iewDispLoadInsts 608809531 -system.cpu.iew.iewDispStoreInsts 243550763 -system.cpu.iew.iewDispNonSpecInsts 36150 -system.cpu.iew.iewIQFullEvents 1478128 -system.cpu.iew.iewLSQFullEvents 4302509 -system.cpu.iew.memOrderViolationEvents 693943 -system.cpu.iew.predictedTakenIncorrect 8551096 -system.cpu.iew.predictedNotTakenIncorrect 21778410 -system.cpu.iew.branchMispredicts 30329506 -system.cpu.iew.iewExecutedInsts 1944942401 -system.cpu.iew.iewExecLoadInsts 457167604 -system.cpu.iew.iewExecSquashedInsts 54725706 -system.cpu.iew.exec_swp 0 -system.cpu.iew.exec_nop 0 -system.cpu.iew.exec_refs 635670117 -system.cpu.iew.exec_branches 185387955 -system.cpu.iew.exec_stores 178502513 -system.cpu.iew.exec_rate 1.996653 -system.cpu.iew.wb_sent 1933639401 -system.cpu.iew.wb_count 1923005119 -system.cpu.iew.wb_producers 1456045504 -system.cpu.iew.wb_consumers 2200626785 -system.cpu.iew.wb_rate 1.974132 -system.cpu.iew.wb_fanout 0.661650 -system.cpu.commit.commitSquashedInsts 888612801 -system.cpu.commit.commitNonSpecStalls 552 -system.cpu.commit.branchMispredicts 24293835 -system.cpu.commit.committed_per_cycle::samples 840170564 -system.cpu.commit.committed_per_cycle::mean 1.821157 -system.cpu.commit.committed_per_cycle::stdev 2.461954 -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% -system.cpu.commit.committed_per_cycle::0 361187526 42.99% 42.99% -system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% -system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% -system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% -system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% -system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% -system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% -system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% -system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% -system.cpu.commit.committed_per_cycle::min_value 0 -system.cpu.commit.committed_per_cycle::max_value 8 -system.cpu.commit.committed_per_cycle::total 840170564 -system.cpu.commit.committedInsts 826847303 -system.cpu.commit.committedOps 1530082520 -system.cpu.commit.swp_count 0 -system.cpu.commit.refs 533241508 -system.cpu.commit.loads 384083313 -system.cpu.commit.membars 0 -system.cpu.commit.branches 149981740 -system.cpu.commit.fp_insts 0 -system.cpu.commit.int_insts 1527470225 -system.cpu.commit.function_calls 17673145 -system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% -system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% -system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% -system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% -system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% -system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% -system.cpu.commit.op_class_0::total 1530082520 -system.cpu.commit.bw_lim_events 73594059 -system.cpu.rob.rob_reads 3185271826 -system.cpu.rob.rob_writes 4972894885 -system.cpu.timesIdled 2025 -system.cpu.idleCycles 203315 -system.cpu.committedInsts 826847303 -system.cpu.committedOps 1530082520 -system.cpu.cpi 1.178091 -system.cpu.cpi_total 1.178091 -system.cpu.ipc 0.848831 -system.cpu.ipc_total 0.848831 -system.cpu.int_regfile_reads 2927263565 -system.cpu.int_regfile_writes 1575987355 -system.cpu.fp_regfile_reads 281295 -system.cpu.fp_regfile_writes 5 -system.cpu.cc_regfile_reads 617980900 -system.cpu.cc_regfile_writes 419571241 -system.cpu.misc_regfile_reads 1064489388 -system.cpu.misc_regfile_writes 1 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.dcache.tags.replacements 2545571 -system.cpu.dcache.tags.tagsinuse 4088.077195 -system.cpu.dcache.tags.total_refs 420813077 -system.cpu.dcache.tags.sampled_refs 2549667 -system.cpu.dcache.tags.avg_refs 165.046289 -system.cpu.dcache.tags.warmup_cycle 1863239500 -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 -system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 -system.cpu.dcache.tags.occ_percent::total 0.998066 -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 -system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 -system.cpu.dcache.tags.occ_task_id_percent::1024 1 -system.cpu.dcache.tags.tag_accesses 850870799 -system.cpu.dcache.tags.data_accesses 850870799 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.dcache.ReadReq_hits::cpu.data 272443625 -system.cpu.dcache.ReadReq_hits::total 272443625 -system.cpu.dcache.WriteReq_hits::cpu.data 148366897 -system.cpu.dcache.WriteReq_hits::total 148366897 -system.cpu.dcache.demand_hits::cpu.data 420810522 -system.cpu.dcache.demand_hits::total 420810522 -system.cpu.dcache.overall_hits::cpu.data 420810522 -system.cpu.dcache.overall_hits::total 420810522 -system.cpu.dcache.ReadReq_misses::cpu.data 2558730 -system.cpu.dcache.ReadReq_misses::total 2558730 -system.cpu.dcache.WriteReq_misses::cpu.data 791314 -system.cpu.dcache.WriteReq_misses::total 791314 -system.cpu.dcache.demand_misses::cpu.data 3350044 -system.cpu.dcache.demand_misses::total 3350044 -system.cpu.dcache.overall_misses::cpu.data 3350044 -system.cpu.dcache.overall_misses::total 3350044 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 -system.cpu.dcache.ReadReq_miss_latency::total 62817542000 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 -system.cpu.dcache.WriteReq_miss_latency::total 26367570500 -system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 -system.cpu.dcache.demand_miss_latency::total 89185112500 -system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 -system.cpu.dcache.overall_miss_latency::total 89185112500 -system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 -system.cpu.dcache.ReadReq_accesses::total 275002355 -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 -system.cpu.dcache.WriteReq_accesses::total 149158211 -system.cpu.dcache.demand_accesses::cpu.data 424160566 -system.cpu.dcache.demand_accesses::total 424160566 -system.cpu.dcache.overall_accesses::cpu.data 424160566 -system.cpu.dcache.overall_accesses::total 424160566 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 -system.cpu.dcache.ReadReq_miss_rate::total 0.009304 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 -system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 -system.cpu.dcache.demand_miss_rate::total 0.007898 -system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 -system.cpu.dcache.overall_miss_rate::total 0.007898 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 -system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 -system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 -system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 -system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 -system.cpu.dcache.blocked_cycles::no_mshrs 9991 -system.cpu.dcache.blocked_cycles::no_targets 13057 -system.cpu.dcache.blocked::no_mshrs 901 -system.cpu.dcache.blocked::no_targets 13 -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 -system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 -system.cpu.dcache.writebacks::writebacks 2337865 -system.cpu.dcache.writebacks::total 2337865 -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 -system.cpu.dcache.ReadReq_mshr_hits::total 792851 -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 -system.cpu.dcache.WriteReq_mshr_hits::total 5950 -system.cpu.dcache.demand_mshr_hits::cpu.data 798801 -system.cpu.dcache.demand_mshr_hits::total 798801 -system.cpu.dcache.overall_mshr_hits::cpu.data 798801 -system.cpu.dcache.overall_mshr_hits::total 798801 -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 -system.cpu.dcache.ReadReq_mshr_misses::total 1765879 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 -system.cpu.dcache.WriteReq_mshr_misses::total 785364 -system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 -system.cpu.dcache.demand_mshr_misses::total 2551243 -system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 -system.cpu.dcache.overall_mshr_misses::total 2551243 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 -system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 -system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.icache.tags.replacements 3942 -system.cpu.icache.tags.tagsinuse 1083.391017 -system.cpu.icache.tags.total_refs 216536709 -system.cpu.icache.tags.sampled_refs 5668 -system.cpu.icache.tags.avg_refs 38203.371383 -system.cpu.icache.tags.warmup_cycle 0 -system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 -system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 -system.cpu.icache.tags.occ_percent::total 0.529000 -system.cpu.icache.tags.occ_task_id_blocks::1024 1726 -system.cpu.icache.tags.age_task_id_blocks_1024::0 39 -system.cpu.icache.tags.age_task_id_blocks_1024::1 10 -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 -system.cpu.icache.tags.age_task_id_blocks_1024::3 80 -system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 -system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 -system.cpu.icache.tags.tag_accesses 433100363 -system.cpu.icache.tags.data_accesses 433100363 -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.icache.ReadReq_hits::cpu.inst 216536917 -system.cpu.icache.ReadReq_hits::total 216536917 -system.cpu.icache.demand_hits::cpu.inst 216536917 -system.cpu.icache.demand_hits::total 216536917 -system.cpu.icache.overall_hits::cpu.inst 216536917 -system.cpu.icache.overall_hits::total 216536917 -system.cpu.icache.ReadReq_misses::cpu.inst 9643 -system.cpu.icache.ReadReq_misses::total 9643 -system.cpu.icache.demand_misses::cpu.inst 9643 -system.cpu.icache.demand_misses::total 9643 -system.cpu.icache.overall_misses::cpu.inst 9643 -system.cpu.icache.overall_misses::total 9643 -system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 -system.cpu.icache.ReadReq_miss_latency::total 597021000 -system.cpu.icache.demand_miss_latency::cpu.inst 597021000 -system.cpu.icache.demand_miss_latency::total 597021000 -system.cpu.icache.overall_miss_latency::cpu.inst 597021000 -system.cpu.icache.overall_miss_latency::total 597021000 -system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 -system.cpu.icache.ReadReq_accesses::total 216546560 -system.cpu.icache.demand_accesses::cpu.inst 216546560 -system.cpu.icache.demand_accesses::total 216546560 -system.cpu.icache.overall_accesses::cpu.inst 216546560 -system.cpu.icache.overall_accesses::total 216546560 -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 -system.cpu.icache.ReadReq_miss_rate::total 0.000045 -system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 -system.cpu.icache.demand_miss_rate::total 0.000045 -system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 -system.cpu.icache.overall_miss_rate::total 0.000045 -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 -system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 -system.cpu.icache.demand_avg_miss_latency::total 61912.371669 -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669 -system.cpu.icache.overall_avg_miss_latency::total 61912.371669 -system.cpu.icache.blocked_cycles::no_mshrs 1205 -system.cpu.icache.blocked_cycles::no_targets 0 -system.cpu.icache.blocked::no_mshrs 12 -system.cpu.icache.blocked::no_targets 0 -system.cpu.icache.avg_blocked_cycles::no_mshrs 100.416667 -system.cpu.icache.avg_blocked_cycles::no_targets nan -system.cpu.icache.writebacks::writebacks 3942 -system.cpu.icache.writebacks::total 3942 -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2400 -system.cpu.icache.ReadReq_mshr_hits::total 2400 -system.cpu.icache.demand_mshr_hits::cpu.inst 2400 -system.cpu.icache.demand_mshr_hits::total 2400 -system.cpu.icache.overall_mshr_hits::cpu.inst 2400 -system.cpu.icache.overall_mshr_hits::total 2400 -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7243 -system.cpu.icache.ReadReq_mshr_misses::total 7243 -system.cpu.icache.demand_mshr_misses::cpu.inst 7243 -system.cpu.icache.demand_mshr_misses::total 7243 -system.cpu.icache.overall_mshr_misses::cpu.inst 7243 -system.cpu.icache.overall_mshr_misses::total 7243 -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 398397500 -system.cpu.icache.ReadReq_mshr_miss_latency::total 398397500 -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 398397500 -system.cpu.icache.demand_mshr_miss_latency::total 398397500 -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 398397500 -system.cpu.icache.overall_mshr_miss_latency::total 398397500 -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091 -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091 -system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091 -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091 -system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091 -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.l2cache.tags.replacements 356141 -system.cpu.l2cache.tags.tagsinuse 30645.512705 -system.cpu.l2cache.tags.total_refs 4711567 -system.cpu.l2cache.tags.sampled_refs 388909 -system.cpu.l2cache.tags.avg_refs 12.114831 -system.cpu.l2cache.tags.warmup_cycle 82679985000 -system.cpu.l2cache.tags.occ_blocks::writebacks 70.320646 -system.cpu.l2cache.tags.occ_blocks::cpu.inst 194.041770 -system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290 -system.cpu.l2cache.tags.occ_percent::writebacks 0.002146 -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005922 -system.cpu.l2cache.tags.occ_percent::cpu.data 0.927159 -system.cpu.l2cache.tags.occ_percent::total 0.935227 -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 176 -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1392 -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31134 -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 -system.cpu.l2cache.tags.tag_accesses 41192837 -system.cpu.l2cache.tags.data_accesses 41192837 -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337865 -system.cpu.l2cache.WritebackDirty_hits::total 2337865 -system.cpu.l2cache.WritebackClean_hits::writebacks 3849 -system.cpu.l2cache.WritebackClean_hits::total 3849 -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1570 -system.cpu.l2cache.UpgradeReq_hits::total 1570 -system.cpu.l2cache.ReadExReq_hits::cpu.data 577208 -system.cpu.l2cache.ReadExReq_hits::total 577208 -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3147 -system.cpu.l2cache.ReadCleanReq_hits::total 3147 -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587166 -system.cpu.l2cache.ReadSharedReq_hits::total 1587166 -system.cpu.l2cache.demand_hits::cpu.inst 3147 -system.cpu.l2cache.demand_hits::cpu.data 2164374 -system.cpu.l2cache.demand_hits::total 2167521 -system.cpu.l2cache.overall_hits::cpu.inst 3147 -system.cpu.l2cache.overall_hits::cpu.data 2164374 -system.cpu.l2cache.overall_hits::total 2167521 -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 -system.cpu.l2cache.UpgradeReq_misses::total 6 -system.cpu.l2cache.ReadExReq_misses::cpu.data 206826 -system.cpu.l2cache.ReadExReq_misses::total 206826 -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2443 -system.cpu.l2cache.ReadCleanReq_misses::total 2443 -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178467 -system.cpu.l2cache.ReadSharedReq_misses::total 178467 -system.cpu.l2cache.demand_misses::cpu.inst 2443 -system.cpu.l2cache.demand_misses::cpu.data 385293 -system.cpu.l2cache.demand_misses::total 387736 -system.cpu.l2cache.overall_misses::cpu.inst 2443 -system.cpu.l2cache.overall_misses::cpu.data 385293 -system.cpu.l2cache.overall_misses::total 387736 -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 -system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18217457500 -system.cpu.l2cache.ReadExReq_miss_latency::total 18217457500 -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351826000 -system.cpu.l2cache.ReadCleanReq_miss_latency::total 351826000 -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18259810000 -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18259810000 -system.cpu.l2cache.demand_miss_latency::cpu.inst 351826000 -system.cpu.l2cache.demand_miss_latency::cpu.data 36477267500 -system.cpu.l2cache.demand_miss_latency::total 36829093500 -system.cpu.l2cache.overall_miss_latency::cpu.inst 351826000 -system.cpu.l2cache.overall_miss_latency::cpu.data 36477267500 -system.cpu.l2cache.overall_miss_latency::total 36829093500 -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337865 -system.cpu.l2cache.WritebackDirty_accesses::total 2337865 -system.cpu.l2cache.WritebackClean_accesses::writebacks 3849 -system.cpu.l2cache.WritebackClean_accesses::total 3849 -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1576 -system.cpu.l2cache.UpgradeReq_accesses::total 1576 -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784034 -system.cpu.l2cache.ReadExReq_accesses::total 784034 -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5590 -system.cpu.l2cache.ReadCleanReq_accesses::total 5590 -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765633 -system.cpu.l2cache.ReadSharedReq_accesses::total 1765633 -system.cpu.l2cache.demand_accesses::cpu.inst 5590 -system.cpu.l2cache.demand_accesses::cpu.data 2549667 -system.cpu.l2cache.demand_accesses::total 2555257 -system.cpu.l2cache.overall_accesses::cpu.inst 5590 -system.cpu.l2cache.overall_accesses::cpu.data 2549667 -system.cpu.l2cache.overall_accesses::total 2555257 -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003807 -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003807 -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263797 -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263797 -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.437030 -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101078 -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101078 -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151115 -system.cpu.l2cache.demand_miss_rate::total 0.151741 -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151115 -system.cpu.l2cache.overall_miss_rate::total 0.151741 -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5083.333333 -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5083.333333 -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232 -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677 -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315 -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673 -system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023 -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315 -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673 -system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023 -system.cpu.l2cache.blocked_cycles::no_mshrs 0 -system.cpu.l2cache.blocked_cycles::no_targets 0 -system.cpu.l2cache.blocked::no_mshrs 0 -system.cpu.l2cache.blocked::no_targets 0 -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan -system.cpu.l2cache.avg_blocked_cycles::no_targets nan -system.cpu.l2cache.writebacks::writebacks 295491 -system.cpu.l2cache.writebacks::total 295491 -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 -system.cpu.l2cache.CleanEvict_mshr_misses::total 10 -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 -system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 -system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 -system.cpu.l2cache.demand_mshr_misses::total 387736 -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 -system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 -system.cpu.l2cache.overall_mshr_misses::total 387736 -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 -system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 -system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 -system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 -system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.cpu.toL2Bus.trans_dist::ReadResp 1772876 -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 -system.cpu.toL2Bus.trans_dist::WritebackClean 3942 -system.cpu.toL2Bus.trans_dist::CleanEvict 268356 -system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 -system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 -system.cpu.toL2Bus.trans_dist::ReadExReq 784034 -system.cpu.toL2Bus.trans_dist::ReadExResp 784034 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 -system.cpu.toL2Bus.pkt_count::total 7664832 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 -system.cpu.toL2Bus.pkt_size::total 313412096 -system.cpu.toL2Bus.snoops 357794 -system.cpu.toL2Bus.snoopTraffic 19017216 -system.cpu.toL2Bus.snoop_fanout::samples 2914627 -system.cpu.toL2Bus.snoop_fanout::mean 0.008154 -system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% -system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 2 -system.cpu.toL2Bus.snoop_fanout::total 2914627 -system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 -system.cpu.toL2Bus.reqLayer0.utilization 1.0 -system.cpu.toL2Bus.respLayer0.occupancy 10867494 -system.cpu.toL2Bus.respLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer1.occupancy 3825288599 -system.cpu.toL2Bus.respLayer1.utilization 0.8 -system.membus.snoop_filter.tot_requests 740964 -system.membus.snoop_filter.hit_single_requests 353722 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 -system.membus.trans_dist::ReadResp 180910 -system.membus.trans_dist::WritebackDirty 295491 -system.membus.trans_dist::CleanEvict 57731 -system.membus.trans_dist::UpgradeReq 9 -system.membus.trans_dist::ReadExReq 206823 -system.membus.trans_dist::ReadExResp 206823 -system.membus.trans_dist::ReadSharedReq 180910 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 -system.membus.pkt_count::total 1128697 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 -system.membus.pkt_size::total 43726336 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 387742 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 387742 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 387742 -system.membus.reqLayer0.occupancy 1998138500 -system.membus.reqLayer0.utilization 0.4 -system.membus.respLayer1.occupancy 2051606500 -system.membus.respLayer1.utilization 0.4 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini deleted file mode 100644 index dd85c448b..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ /dev/null @@ -1,263 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kvm_vm=Null -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=apic_clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_latency=1000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -power_model=Null -system=system -int_master=system.membus.slave[5] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr deleted file mode 100755 index 43d70058a..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout deleted file mode 100755 index 227ee869b..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ /dev/null @@ -1,71 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 19:05:53 -gem5 started Apr 3 2017 19:06:22 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - 58924 words stored in 3784810 bytes - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 885772926000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt deleted file mode 100644 index 5fc9dc6b8..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,145 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.885773 -sim_ticks 885772926000 -final_tick 885772926000 -sim_freq 1000000000000 -host_inst_rate 728826 -host_op_rate 1348694 -host_tick_rate 780766307 -host_mem_usage 284536 -host_seconds 1134.49 -sim_insts 826847304 -sim_ops 1530082521 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.physmem.bytes_read::cpu.inst 8546485088 -system.physmem.bytes_read::cpu.data 2285527276 -system.physmem.bytes_read::total 10832012364 -system.physmem.bytes_inst_read::cpu.inst 8546485088 -system.physmem.bytes_inst_read::total 8546485088 -system.physmem.bytes_written::cpu.data 991837474 -system.physmem.bytes_written::total 991837474 -system.physmem.num_reads::cpu.inst 1068310636 -system.physmem.num_reads::cpu.data 384083342 -system.physmem.num_reads::total 1452393978 -system.physmem.num_writes::cpu.data 149158211 -system.physmem.num_writes::total 149158211 -system.physmem.bw_read::cpu.inst 9648618554 -system.physmem.bw_read::cpu.data 2580263190 -system.physmem.bw_read::total 12228881744 -system.physmem.bw_inst_read::cpu.inst 9648618554 -system.physmem.bw_inst_read::total 9648618554 -system.physmem.bw_write::cpu.data 1119742368 -system.physmem.bw_write::total 1119742368 -system.physmem.bw_total::cpu.inst 9648618554 -system.physmem.bw_total::cpu.data 3700005559 -system.physmem.bw_total::total 13348624112 -system.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.cpu_clk_domain.clock 500 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.cpu.apic_clk_domain.clock 8000 -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.cpu.workload.numSyscalls 551 -system.cpu.pwrStateResidencyTicks::ON 885772926000 -system.cpu.numCycles 1771545853 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 826847304 -system.cpu.committedOps 1530082521 -system.cpu.num_int_alu_accesses 1527470226 -system.cpu.num_fp_alu_accesses 0 -system.cpu.num_func_calls 35346287 -system.cpu.num_conditional_control_insts 92881952 -system.cpu.num_int_insts 1527470226 -system.cpu.num_fp_insts 0 -system.cpu.num_int_register_reads 3298246119 -system.cpu.num_int_register_writes 1240060586 -system.cpu.num_fp_register_reads 0 -system.cpu.num_fp_register_writes 0 -system.cpu.num_cc_register_reads 562449682 -system.cpu.num_cc_register_writes 376900986 -system.cpu.num_mem_refs 533241508 -system.cpu.num_load_insts 384083313 -system.cpu.num_store_insts 149158195 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 1771545853 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 149981740 -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% -system.cpu.op_class::IntMult 306834 0.02% 64.84% -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% -system.cpu.op_class::FloatAdd 0 0.00% 65.15% -system.cpu.op_class::FloatCmp 0 0.00% 65.15% -system.cpu.op_class::FloatCvt 0 0.00% 65.15% -system.cpu.op_class::FloatMult 0 0.00% 65.15% -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% -system.cpu.op_class::FloatDiv 0 0.00% 65.15% -system.cpu.op_class::FloatMisc 0 0.00% 65.15% -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% -system.cpu.op_class::SimdAdd 0 0.00% 65.15% -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% -system.cpu.op_class::SimdAlu 0 0.00% 65.15% -system.cpu.op_class::SimdCmp 0 0.00% 65.15% -system.cpu.op_class::SimdCvt 0 0.00% 65.15% -system.cpu.op_class::SimdMisc 0 0.00% 65.15% -system.cpu.op_class::SimdMult 0 0.00% 65.15% -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% -system.cpu.op_class::SimdShift 0 0.00% 65.15% -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% -system.cpu.op_class::MemRead 384083313 25.10% 90.25% -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 1530082521 -system.membus.snoop_filter.tot_requests 0 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 -system.membus.trans_dist::ReadReq 1452393978 -system.membus.trans_dist::ReadResp 1452393978 -system.membus.trans_dist::WriteReq 149158211 -system.membus.trans_dist::WriteResp 149158211 -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 -system.membus.pkt_count_system.cpu.icache_port::total 2136621272 -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 -system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 -system.membus.pkt_count::total 3203104378 -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 -system.membus.pkt_size_system.cpu.icache_port::total 8546485088 -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 -system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 -system.membus.pkt_size::total 11823849838 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 1601552189 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 1601552189 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 1601552189 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini deleted file mode 100644 index 6ea332421..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ /dev/null @@ -1,432 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kvm_vm=Null -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_latency=1000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -power_model=Null -system=system -int_master=system.membus.slave[2] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser -gid=100 -input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr deleted file mode 100755 index 43d70058a..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout deleted file mode 100755 index 5231f3e17..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ /dev/null @@ -1,71 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 19:05:53 -gem5 started Apr 3 2017 19:06:22 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing - -Global frequency set at 1000000000000 ticks per second - - Reading the dictionary files: ************************************************* - 58924 words stored in 3784810 bytes - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 1650923912500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt deleted file mode 100644 index 48f9b108e..000000000 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ /dev/null @@ -1,546 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.650924 -sim_ticks 1650923912500 -final_tick 1650923912500 -sim_freq 1000000000000 -host_inst_rate 500428 -host_op_rate 926043 -host_tick_rate 999178622 -host_mem_usage 295552 -host_seconds 1652.28 -sim_insts 826847304 -sim_ops 1530082521 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.physmem.bytes_read::cpu.inst 115968 -system.physmem.bytes_read::cpu.data 24312256 -system.physmem.bytes_read::total 24428224 -system.physmem.bytes_inst_read::cpu.inst 115968 -system.physmem.bytes_inst_read::total 115968 -system.physmem.bytes_written::writebacks 18812864 -system.physmem.bytes_written::total 18812864 -system.physmem.num_reads::cpu.inst 1812 -system.physmem.num_reads::cpu.data 379879 -system.physmem.num_reads::total 381691 -system.physmem.num_writes::writebacks 293951 -system.physmem.num_writes::total 293951 -system.physmem.bw_read::cpu.inst 70244 -system.physmem.bw_read::cpu.data 14726455 -system.physmem.bw_read::total 14796699 -system.physmem.bw_inst_read::cpu.inst 70244 -system.physmem.bw_inst_read::total 70244 -system.physmem.bw_write::writebacks 11395355 -system.physmem.bw_write::total 11395355 -system.physmem.bw_total::writebacks 11395355 -system.physmem.bw_total::cpu.inst 70244 -system.physmem.bw_total::cpu.data 14726455 -system.physmem.bw_total::total 26192054 -system.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu_clk_domain.clock 500 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.apic_clk_domain.clock 8000 -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.workload.numSyscalls 551 -system.cpu.pwrStateResidencyTicks::ON 1650923912500 -system.cpu.numCycles 3301847825 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 826847304 -system.cpu.committedOps 1530082521 -system.cpu.num_int_alu_accesses 1527470226 -system.cpu.num_fp_alu_accesses 0 -system.cpu.num_func_calls 35346287 -system.cpu.num_conditional_control_insts 92881952 -system.cpu.num_int_insts 1527470226 -system.cpu.num_fp_insts 0 -system.cpu.num_int_register_reads 3298246119 -system.cpu.num_int_register_writes 1240060586 -system.cpu.num_fp_register_reads 0 -system.cpu.num_fp_register_writes 0 -system.cpu.num_cc_register_reads 562449682 -system.cpu.num_cc_register_writes 376900986 -system.cpu.num_mem_refs 533241508 -system.cpu.num_load_insts 384083313 -system.cpu.num_store_insts 149158195 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 3301847825 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 149981740 -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% -system.cpu.op_class::IntMult 306834 0.02% 64.84% -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% -system.cpu.op_class::FloatAdd 0 0.00% 65.15% -system.cpu.op_class::FloatCmp 0 0.00% 65.15% -system.cpu.op_class::FloatCvt 0 0.00% 65.15% -system.cpu.op_class::FloatMult 0 0.00% 65.15% -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% -system.cpu.op_class::FloatDiv 0 0.00% 65.15% -system.cpu.op_class::FloatMisc 0 0.00% 65.15% -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% -system.cpu.op_class::SimdAdd 0 0.00% 65.15% -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% -system.cpu.op_class::SimdAlu 0 0.00% 65.15% -system.cpu.op_class::SimdCmp 0 0.00% 65.15% -system.cpu.op_class::SimdCvt 0 0.00% 65.15% -system.cpu.op_class::SimdMisc 0 0.00% 65.15% -system.cpu.op_class::SimdMult 0 0.00% 65.15% -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% -system.cpu.op_class::SimdShift 0 0.00% 65.15% -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% -system.cpu.op_class::MemRead 384083313 25.10% 90.25% -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 1530082521 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.dcache.tags.replacements 2517016 -system.cpu.dcache.tags.tagsinuse 4086.382570 -system.cpu.dcache.tags.total_refs 530720441 -system.cpu.dcache.tags.sampled_refs 2521112 -system.cpu.dcache.tags.avg_refs 210.510458 -system.cpu.dcache.tags.warmup_cycle 8250925500 -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 -system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 -system.cpu.dcache.tags.occ_percent::total 0.997652 -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 -system.cpu.dcache.tags.occ_task_id_percent::1024 1 -system.cpu.dcache.tags.tag_accesses 1069004218 -system.cpu.dcache.tags.data_accesses 1069004218 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.dcache.ReadReq_hits::cpu.data 382353600 -system.cpu.dcache.ReadReq_hits::total 382353600 -system.cpu.dcache.WriteReq_hits::cpu.data 148366841 -system.cpu.dcache.WriteReq_hits::total 148366841 -system.cpu.dcache.demand_hits::cpu.data 530720441 -system.cpu.dcache.demand_hits::total 530720441 -system.cpu.dcache.overall_hits::cpu.data 530720441 -system.cpu.dcache.overall_hits::total 530720441 -system.cpu.dcache.ReadReq_misses::cpu.data 1729742 -system.cpu.dcache.ReadReq_misses::total 1729742 -system.cpu.dcache.WriteReq_misses::cpu.data 791370 -system.cpu.dcache.WriteReq_misses::total 791370 -system.cpu.dcache.demand_misses::cpu.data 2521112 -system.cpu.dcache.demand_misses::total 2521112 -system.cpu.dcache.overall_misses::cpu.data 2521112 -system.cpu.dcache.overall_misses::total 2521112 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 -system.cpu.dcache.ReadReq_miss_latency::total 31154171500 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 -system.cpu.dcache.WriteReq_miss_latency::total 20614263500 -system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 -system.cpu.dcache.demand_miss_latency::total 51768435000 -system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 -system.cpu.dcache.overall_miss_latency::total 51768435000 -system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 -system.cpu.dcache.ReadReq_accesses::total 384083342 -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 -system.cpu.dcache.WriteReq_accesses::total 149158211 -system.cpu.dcache.demand_accesses::cpu.data 533241553 -system.cpu.dcache.demand_accesses::total 533241553 -system.cpu.dcache.overall_accesses::cpu.data 533241553 -system.cpu.dcache.overall_accesses::total 533241553 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 -system.cpu.dcache.ReadReq_miss_rate::total 0.004504 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 -system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 -system.cpu.dcache.demand_miss_rate::total 0.004728 -system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 -system.cpu.dcache.overall_miss_rate::total 0.004728 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 -system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 -system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 -system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 -system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 -system.cpu.dcache.blocked_cycles::no_mshrs 0 -system.cpu.dcache.blocked_cycles::no_targets 0 -system.cpu.dcache.blocked::no_mshrs 0 -system.cpu.dcache.blocked::no_targets 0 -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan -system.cpu.dcache.avg_blocked_cycles::no_targets nan -system.cpu.dcache.writebacks::writebacks 2324919 -system.cpu.dcache.writebacks::total 2324919 -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 -system.cpu.dcache.ReadReq_mshr_misses::total 1729742 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 -system.cpu.dcache.WriteReq_mshr_misses::total 791370 -system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 -system.cpu.dcache.demand_mshr_misses::total 2521112 -system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 -system.cpu.dcache.overall_mshr_misses::total 2521112 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 -system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 -system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 -system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 -system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.icache.tags.replacements 1253 -system.cpu.icache.tags.tagsinuse 881.361666 -system.cpu.icache.tags.total_refs 1068307823 -system.cpu.icache.tags.sampled_refs 2814 -system.cpu.icache.tags.avg_refs 379640.306681 -system.cpu.icache.tags.warmup_cycle 0 -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 -system.cpu.icache.tags.occ_percent::total 0.430352 -system.cpu.icache.tags.occ_task_id_blocks::1024 1561 -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 -system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 -system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 -system.cpu.icache.tags.tag_accesses 2136624088 -system.cpu.icache.tags.data_accesses 2136624088 -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.icache.ReadReq_hits::cpu.inst 1068307823 -system.cpu.icache.ReadReq_hits::total 1068307823 -system.cpu.icache.demand_hits::cpu.inst 1068307823 -system.cpu.icache.demand_hits::total 1068307823 -system.cpu.icache.overall_hits::cpu.inst 1068307823 -system.cpu.icache.overall_hits::total 1068307823 -system.cpu.icache.ReadReq_misses::cpu.inst 2814 -system.cpu.icache.ReadReq_misses::total 2814 -system.cpu.icache.demand_misses::cpu.inst 2814 -system.cpu.icache.demand_misses::total 2814 -system.cpu.icache.overall_misses::cpu.inst 2814 -system.cpu.icache.overall_misses::total 2814 -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 -system.cpu.icache.ReadReq_miss_latency::total 127237000 -system.cpu.icache.demand_miss_latency::cpu.inst 127237000 -system.cpu.icache.demand_miss_latency::total 127237000 -system.cpu.icache.overall_miss_latency::cpu.inst 127237000 -system.cpu.icache.overall_miss_latency::total 127237000 -system.cpu.icache.ReadReq_accesses::cpu.inst 1068310637 -system.cpu.icache.ReadReq_accesses::total 1068310637 -system.cpu.icache.demand_accesses::cpu.inst 1068310637 -system.cpu.icache.demand_accesses::total 1068310637 -system.cpu.icache.overall_accesses::cpu.inst 1068310637 -system.cpu.icache.overall_accesses::total 1068310637 -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 -system.cpu.icache.ReadReq_miss_rate::total 0.000003 -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 -system.cpu.icache.demand_miss_rate::total 0.000003 -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 -system.cpu.icache.overall_miss_rate::total 0.000003 -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 -system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 -system.cpu.icache.demand_avg_miss_latency::total 45215.707178 -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 -system.cpu.icache.overall_avg_miss_latency::total 45215.707178 -system.cpu.icache.blocked_cycles::no_mshrs 0 -system.cpu.icache.blocked_cycles::no_targets 0 -system.cpu.icache.blocked::no_mshrs 0 -system.cpu.icache.blocked::no_targets 0 -system.cpu.icache.avg_blocked_cycles::no_mshrs nan -system.cpu.icache.avg_blocked_cycles::no_targets nan -system.cpu.icache.writebacks::writebacks 1253 -system.cpu.icache.writebacks::total 1253 -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 -system.cpu.icache.ReadReq_mshr_misses::total 2814 -system.cpu.icache.demand_mshr_misses::cpu.inst 2814 -system.cpu.icache.demand_mshr_misses::total 2814 -system.cpu.icache.overall_mshr_misses::cpu.inst 2814 -system.cpu.icache.overall_mshr_misses::total 2814 -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 -system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 -system.cpu.icache.demand_mshr_miss_latency::total 124423000 -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 -system.cpu.icache.overall_mshr_miss_latency::total 124423000 -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 -system.cpu.icache.demand_mshr_miss_rate::total 0.000003 -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 -system.cpu.icache.overall_mshr_miss_rate::total 0.000003 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 -system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 -system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.l2cache.tags.replacements 349420 -system.cpu.l2cache.tags.tagsinuse 30439.047290 -system.cpu.l2cache.tags.total_refs 4660001 -system.cpu.l2cache.tags.sampled_refs 382188 -system.cpu.l2cache.tags.avg_refs 12.192955 -system.cpu.l2cache.tags.warmup_cycle 287867097000 -system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 -system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 -system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 -system.cpu.l2cache.tags.occ_percent::total 0.928926 -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 -system.cpu.l2cache.tags.tag_accesses 40719748 -system.cpu.l2cache.tags.data_accesses 40719748 -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 -system.cpu.l2cache.WritebackDirty_hits::total 2324919 -system.cpu.l2cache.WritebackClean_hits::writebacks 1253 -system.cpu.l2cache.WritebackClean_hits::total 1253 -system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 -system.cpu.l2cache.ReadExReq_hits::total 584841 -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 -system.cpu.l2cache.ReadCleanReq_hits::total 1002 -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 -system.cpu.l2cache.ReadSharedReq_hits::total 1556392 -system.cpu.l2cache.demand_hits::cpu.inst 1002 -system.cpu.l2cache.demand_hits::cpu.data 2141233 -system.cpu.l2cache.demand_hits::total 2142235 -system.cpu.l2cache.overall_hits::cpu.inst 1002 -system.cpu.l2cache.overall_hits::cpu.data 2141233 -system.cpu.l2cache.overall_hits::total 2142235 -system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 -system.cpu.l2cache.ReadExReq_misses::total 206529 -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 -system.cpu.l2cache.ReadCleanReq_misses::total 1812 -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 -system.cpu.l2cache.ReadSharedReq_misses::total 173350 -system.cpu.l2cache.demand_misses::cpu.inst 1812 -system.cpu.l2cache.demand_misses::cpu.data 379879 -system.cpu.l2cache.demand_misses::total 381691 -system.cpu.l2cache.overall_misses::cpu.inst 1812 -system.cpu.l2cache.overall_misses::cpu.data 379879 -system.cpu.l2cache.overall_misses::total 381691 -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 -system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 -system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 -system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 -system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 -system.cpu.l2cache.demand_miss_latency::total 23092375000 -system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 -system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 -system.cpu.l2cache.overall_miss_latency::total 23092375000 -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 -system.cpu.l2cache.WritebackDirty_accesses::total 2324919 -system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 -system.cpu.l2cache.WritebackClean_accesses::total 1253 -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 -system.cpu.l2cache.ReadExReq_accesses::total 791370 -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 -system.cpu.l2cache.ReadCleanReq_accesses::total 2814 -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 -system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 -system.cpu.l2cache.demand_accesses::cpu.inst 2814 -system.cpu.l2cache.demand_accesses::cpu.data 2521112 -system.cpu.l2cache.demand_accesses::total 2523926 -system.cpu.l2cache.overall_accesses::cpu.inst 2814 -system.cpu.l2cache.overall_accesses::cpu.data 2521112 -system.cpu.l2cache.overall_accesses::total 2523926 -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 -system.cpu.l2cache.demand_miss_rate::total 0.151229 -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 -system.cpu.l2cache.overall_miss_rate::total 0.151229 -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 -system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 -system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 -system.cpu.l2cache.blocked_cycles::no_mshrs 0 -system.cpu.l2cache.blocked_cycles::no_targets 0 -system.cpu.l2cache.blocked::no_mshrs 0 -system.cpu.l2cache.blocked::no_targets 0 -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan -system.cpu.l2cache.avg_blocked_cycles::no_targets nan -system.cpu.l2cache.writebacks::writebacks 293952 -system.cpu.l2cache.writebacks::total 293952 -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 -system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 -system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 -system.cpu.l2cache.demand_mshr_misses::total 381691 -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 -system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 -system.cpu.l2cache.overall_mshr_misses::total 381691 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 -system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 -system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 -system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 -system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.cpu.toL2Bus.trans_dist::ReadResp 1732556 -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 -system.cpu.toL2Bus.trans_dist::WritebackClean 1253 -system.cpu.toL2Bus.trans_dist::CleanEvict 247565 -system.cpu.toL2Bus.trans_dist::ReadExReq 791370 -system.cpu.toL2Bus.trans_dist::ReadExResp 791370 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 -system.cpu.toL2Bus.pkt_count::total 7566121 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 -system.cpu.toL2Bus.pkt_size::total 310406272 -system.cpu.toL2Bus.snoops 349420 -system.cpu.toL2Bus.snoopTraffic 18812928 -system.cpu.toL2Bus.snoop_fanout::samples 2873346 -system.cpu.toL2Bus.snoop_fanout::mean 0.000649 -system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% -system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 1 -system.cpu.toL2Bus.snoop_fanout::total 2873346 -system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 -system.cpu.toL2Bus.reqLayer0.utilization 0.3 -system.cpu.toL2Bus.respLayer0.occupancy 4221000 -system.cpu.toL2Bus.respLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer1.occupancy 3781668000 -system.cpu.toL2Bus.respLayer1.utilization 0.2 -system.membus.snoop_filter.tot_requests 729250 -system.membus.snoop_filter.hit_single_requests 347559 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 -system.membus.trans_dist::ReadResp 175162 -system.membus.trans_dist::WritebackDirty 293951 -system.membus.trans_dist::CleanEvict 53608 -system.membus.trans_dist::ReadExReq 206529 -system.membus.trans_dist::ReadExResp 206529 -system.membus.trans_dist::ReadSharedReq 175162 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 -system.membus.pkt_count::total 1110941 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 -system.membus.pkt_size::total 43241088 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 381691 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 381691 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 381691 -system.membus.reqLayer0.occupancy 1905079500 -system.membus.reqLayer0.utilization 0.1 -system.membus.respLayer1.occupancy 1908455000 -system.membus.respLayer1.utilization 0.1 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/test.py b/tests/long/se/20.parser/test.py deleted file mode 100644 index d15b341ac..000000000 --- a/tests/long/se/20.parser/test.py +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Korey Sewell - -m5.util.addToPath('../configs/common') -from cpu2000 import parser - -workload = parser(isa, opsys, 'mdred') -root.system.cpu[0].workload = workload.makeProcess() |