diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-23 15:56:32 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 34f1b771ed911ac8dc9f02ded63add7de3c263ed (patch) | |
| tree | 3c504926f9c8253c47a3af43d7c84f3a14193c45 | |
| parent | 22273000d0cd8b695c4dea9613c649f764ed94ea (diff) | |
| download | gem5-34f1b771ed911ac8dc9f02ded63add7de3c263ed.tar.xz | |
arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/miscregs.cc | 8 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 45 |
2 files changed, 40 insertions, 13 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 5f45916b6..81bc3efae 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4533,7 +4533,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP0R3); InitReg(MISCREG_ICC_AP1R0_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R0); InitReg(MISCREG_ICC_AP1R0_EL1_NS) .bankedChild() @@ -4544,7 +4544,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R0_S); InitReg(MISCREG_ICC_AP1R1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R1); InitReg(MISCREG_ICC_AP1R1_EL1_NS) .bankedChild() @@ -4555,7 +4555,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R1_S); InitReg(MISCREG_ICC_AP1R2_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R2); InitReg(MISCREG_ICC_AP1R2_EL1_NS) .bankedChild() @@ -4566,7 +4566,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R2_S); InitReg(MISCREG_ICC_AP1R3_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R3); InitReg(MISCREG_ICC_AP1R3_EL1_NS) .bankedChild() diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 786f1abd7..0d444f165 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -128,7 +128,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg) return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); } - break; + return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1); } case MISCREG_ICC_AP1R1: @@ -740,7 +740,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); } - break; + setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val); + return; case MISCREG_ICC_AP1R1: case MISCREG_ICC_AP1R1_EL1: @@ -1719,11 +1720,23 @@ Gicv3CPUInterface::getHPPIR1() const void Gicv3CPUInterface::dropPriority(Gicv3::GroupId group) { - int apr_misc_reg; - RegVal apr; - apr_misc_reg = group == Gicv3::G0S ? - MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; - apr = isa->readMiscRegNoEffect(apr_misc_reg); + int apr_misc_reg = 0; + + switch (group) { + case Gicv3::G0S: + apr_misc_reg = MISCREG_ICC_AP0R0_EL1; + break; + case Gicv3::G1S: + apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S; + break; + case Gicv3::G1NS: + apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS; + break; + default: + panic("Invalid Gicv3::GroupId"); + } + + RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg); if (apr) { apr &= apr - 1; @@ -1814,8 +1827,22 @@ Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) uint32_t prio = hppi.prio & 0xf8; int apr_bit = prio >> (8 - PRIORITY_BITS); int reg_bit = apr_bit % 32; - int apr_idx = group == Gicv3::G0S ? - MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; + + int apr_idx = 0; + switch (group) { + case Gicv3::G0S: + apr_idx = MISCREG_ICC_AP0R0_EL1; + break; + case Gicv3::G1S: + apr_idx = MISCREG_ICC_AP1R0_EL1_S; + break; + case Gicv3::G1NS: + apr_idx = MISCREG_ICC_AP1R0_EL1_NS; + break; + default: + panic("Invalid Gicv3::GroupId"); + } + RegVal apr = isa->readMiscRegNoEffect(apr_idx); apr |= (1 << reg_bit); isa->setMiscRegNoEffect(apr_idx, apr); |