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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-26 22:01:34 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-26 22:01:34 -0700 |
| commit | 38d8bc64baab5ef17958d84e9d5fe6d62c31fca3 (patch) | |
| tree | 58ae32fe8f4d61fbe87b1750207bd375dcb918a4 | |
| parent | 7b5386d390a114784fe65efe3884c670c1a9ced8 (diff) | |
| download | gem5-38d8bc64baab5ef17958d84e9d5fe6d62c31fca3.tar.xz | |
ARM: Fill out the printReg function.
| -rw-r--r-- | src/arch/arm/insts/static_inst.cc | 25 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 10 |
2 files changed, 31 insertions, 4 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index aa60b57be..1a7853f2c 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -219,10 +219,29 @@ void ArmStaticInst::printReg(std::ostream &os, int reg) const { if (reg < FP_Base_DepTag) { - ccprintf(os, "r%d", reg); - } - else { + switch (reg) { + case PCReg: + ccprintf(os, "pc"); + break; + case StackPointerReg: + ccprintf(os, "sp"); + break; + case FramePointerReg: + ccprintf(os, "fp"); + break; + case ReturnAddressReg: + ccprintf(os, "lr"); + break; + default: + ccprintf(os, "r%d", reg); + break; + } + } else if (reg < Ctrl_Base_DepTag) { ccprintf(os, "f%d", reg - FP_Base_DepTag); + } else { + reg -= Ctrl_Base_DepTag; + assert(reg < NUM_MISCREGS); + ccprintf(os, "%s", ArmISA::miscRegName[reg]); } } diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index d939fabcf..42065b0fd 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -55,12 +55,20 @@ namespace ArmISA enum MiscRegIndex { MISCREG_CPSR = 0, + MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, MISCREG_SPSR_SVC, MISCREG_SPSR_UND, MISCREG_SPSR_ABT, - MISCREG_FPSR + MISCREG_FPSR, + NUM_MISCREGS + }; + + const char * const miscRegName[NUM_MISCREGS] = { + "cpsr", + "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt", + "fpsr" }; BitUnion32(CPSR) |