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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-02-23 13:50:38 +0000 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-05-31 08:05:42 +0000 |
| commit | 3b04ba58b81f5bee45c7c5111c93605eac850f9c (patch) | |
| tree | 2018c002e0a8165090302125d49a9afa598c2390 | |
| parent | 3cf4a04fceef321b5cd6ece9a4ff1814787a236d (diff) | |
| download | gem5-3b04ba58b81f5bee45c7c5111c93605eac850f9c.tar.xz | |
arch-arm: Treat SVE prefetch instructions as no-ops
Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/isa/formats/sve_2nd_level.isa | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index 7b2d3af49..d4e75285b 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -2930,11 +2930,11 @@ namespace Aarch64 uint8_t b14_13 = bits(machInst, 14, 13); if (b14_13 == 0x2 && bits(machInst, 4) == 0) { // TODO: SVE contiguous prefetch (scalar plus scalar) - return new Unknown64(machInst); + return new WarnUnimplemented("prf[bhwd]", machInst); } else if (b14_13 == 0x3 && bits(machInst, 4) == 0) { // TODO: SVE 32-bit gather prefetch (vector plus // immediate) - return new Unknown64(machInst); + return new WarnUnimplemented("prf[bhwd]", machInst); } } } @@ -2963,7 +2963,7 @@ namespace Aarch64 case 0x0: if (bits(machInst, 21) && bits(machInst, 4) == 0) { // TODO: SVE 32-bit gather prefetch (vector plus immediate) - break; + return new WarnUnimplemented("prf[bhwd]", machInst); } break; case 0x1: @@ -3040,6 +3040,10 @@ namespace Aarch64 uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) | bits(machInst, 12, 10)); return new SveLdrVec(machInst, zt, rn, imm); + } else if (bits(machInst, 22) == 1 && + bits(machInst, 4) == 0) { + // TODO: SVE contiguous prefetch (scalar plus immediate) + return new WarnUnimplemented("prf[bhwd]", machInst); } break; } @@ -3210,7 +3214,7 @@ namespace Aarch64 } else { if (bits(machInst, 14, 13) == 0x3 && bits(machInst, 4) == 0) { // TODO: SVE 64-bit gather prefetch (vector plus immediate) - break; + return new WarnUnimplemented("prf[bhwd]", machInst); } } break; @@ -3237,7 +3241,7 @@ namespace Aarch64 } else if (bits(machInst, 4) == 0) { // TODO: SVE 64-bit gather prefetch (scalar plus unpacked // 32-bit scaled offsets) - return new Unknown64(machInst); + return new WarnUnimplemented("prf[bhwd]", machInst); } break; case 0x3: @@ -3280,7 +3284,7 @@ namespace Aarch64 } else if (bits(machInst, 4) == 0) { // TODO: SVE 64-bit gather prefetch (scalar plus 64-bit // scaled offsets) - break; + return new WarnUnimplemented("prf[bhwd]", machInst); } } break; |