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authorNikos Nikoleris <nikos.nikoleris@arm.com>2017-09-13 12:23:25 +0100
committerNikos Nikoleris <nikos.nikoleris@arm.com>2017-12-05 11:47:01 +0000
commit3deff78fe40b9aa3d4e3a8571f13f29072efe4e4 (patch)
tree519849252d5562d62fb6f7f1a9c75118df58b473
parenteb2722609a11c992b55bf20dec1823b4118382c6 (diff)
downloadgem5-3deff78fe40b9aa3d4e3a8571f13f29072efe4e4.tar.xz
mem: Ignore clean requests in the abstract memory
Systems with atomic cores and the fastmem option enabled bypass the whole memory system and access the abstract memory directly. Cache maintenance operations which would be normally handled before the point of unification/coherence should be ignored by the abstract memory. Change-Id: I696cdd158222e5fd67f670cddbcf2efbbfd5eca4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5054 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
-rw-r--r--src/mem/abstract_mem.cc13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 13a0873cb..b41c82b0d 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -399,13 +399,12 @@ AbstractMemory::access(PacketPtr pkt)
bytesRead[pkt->req->masterId()] += pkt->getSize();
if (pkt->req->isInstFetch())
bytesInstRead[pkt->req->masterId()] += pkt->getSize();
- } else if (pkt->isInvalidate()) {
+ } else if (pkt->isInvalidate() || pkt->isClean()) {
+ assert(!pkt->isWrite());
+ // in a fastmem system invalidating and/or cleaning packets
+ // can be seen due to cache maintenance requests
+
// no need to do anything
- // this clause is intentionally before the write clause: the only
- // transaction that is both a write and an invalidate is
- // WriteInvalidate, and for the sake of consistency, it does not
- // write to memory. in a cacheless system, there are no WriteInv's
- // because the Write -> WriteInvalidate rewrite happens in the cache.
} else if (pkt->isWrite()) {
if (writeOK(pkt)) {
if (pmemAddr) {
@@ -419,7 +418,7 @@ AbstractMemory::access(PacketPtr pkt)
bytesWritten[pkt->req->masterId()] += pkt->getSize();
}
} else {
- panic("unimplemented");
+ panic("Unexpected packet %s", pkt->print());
}
if (pkt->needsResponse()) {