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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-16 14:48:10 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-25 12:48:41 +0000 |
| commit | 40018b14a608b066a52c4baf86b4160820402c9c (patch) | |
| tree | 4ad3fa351a80626f32afee95a28186b4a2f15d6e | |
| parent | ed48d740e85c167aa48a2c4fe82ca632e4c3cbb7 (diff) | |
| download | gem5-40018b14a608b066a52c4baf86b4160820402c9c.tar.xz | |
dev-arm: Move GICv3 (Re)Ditributor address in Realview.py
Base addresses for GICv3's Distributor and Redistributors are
implementation defined: they depend on the platform rather than the
model. This patch is then moving dist_addr and redist_addr
initialization in Realview.py
Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/dev/arm/Gic.py | 4 | ||||
| -rw-r--r-- | src/dev/arm/RealView.py | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 63ecc923b..011e238cc 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -166,9 +166,9 @@ class Gicv3(BaseGic): type = 'Gicv3' cxx_header = "dev/arm/gic_v3.hh" - dist_addr = Param.Addr(0x2c000000, "Address for distributor") + dist_addr = Param.Addr("Address for distributor") dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") - redist_addr = Param.Addr(0x2c010000, "Address for redistributors") + redist_addr = Param.Addr("Address for redistributors") redist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to redistributors") it_lines = Param.UInt32(1020, diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index f83f075f6..186d6df41 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1083,7 +1083,8 @@ class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): ] class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): - gic = Gicv3(maint_int=ArmPPI(num=25)) + gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000, + maint_int=ArmPPI(num=25)) # Limiting to 128 since it will otherwise overlap with PCI space gic.cpu_max = 128 |