diff options
| author | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-14 12:22:53 -0800 |
|---|---|---|
| committer | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-24 05:48:14 +0000 |
| commit | 43ea4e01a0443fde405794a5b914c59caa13688a (patch) | |
| tree | a0935ab90fb0e1509ae74aabd33a5789fc7b59df | |
| parent | 6a87e1ff0476d1f1ee0211ac1d61bd3448b9c7d2 (diff) | |
| download | gem5-43ea4e01a0443fde405794a5b914c59caa13688a.tar.xz | |
tests: Removed 30.eon tests
In an effort to cleanup the old tests, and migrate useful tests to be
executed via `test/main.py`, it has been decided that the
`test/long/se/30.eon` tests should be removed.
Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Ieb32196a5f0ed3b3375ede5aec6f8fb8d162a865
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24386
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
17 files changed, 0 insertions, 6196 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini deleted file mode 100644 index 3e9f2ae1c..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ /dev/null @@ -1,997 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr deleted file mode 100755 index 497b78d8e..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr +++ /dev/null @@ -1,59 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -warn: User mode does not have SPSR -warn: User mode does not have SPSR -col 0. . . -col 1. . . -col 2. . . -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout deleted file mode 100755 index feeb32deb..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ /dev/null @@ -1,19 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:47:28 -gem5 executing on e108600-lin, pid 17426 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -OO-style eon Time= 0.220000 -Exiting @ tick 225206521000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt deleted file mode 100644 index 2d9609855..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ /dev/null @@ -1,917 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.225185 # Number of seconds simulated -sim_ticks 225184887000 # Number of ticks simulated -final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 292846 # Simulator instruction rate (inst/s) -host_op_rate 351594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 241521552 # Simulator tick rate (ticks/s) -host_mem_usage 280036 # Number of bytes of host memory used -host_seconds 932.36 # Real time elapsed on the host -sim_insts 273037855 # Number of instructions simulated -sim_ops 327812212 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory -system.physmem.bytes_read::total 485504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7586 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 630 # Per bank write bursts -system.physmem.perBankRdBursts::1 846 # Per bank write bursts -system.physmem.perBankRdBursts::2 628 # Per bank write bursts -system.physmem.perBankRdBursts::3 541 # Per bank write bursts -system.physmem.perBankRdBursts::4 466 # Per bank write bursts -system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 171 # Per bank write bursts -system.physmem.perBankRdBursts::7 228 # Per bank write bursts -system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 309 # Per bank write bursts -system.physmem.perBankRdBursts::10 343 # Per bank write bursts -system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 553 # Per bank write bursts -system.physmem.perBankRdBursts::13 705 # Per bank write bursts -system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 542 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225184633000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7586 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation -system.physmem.totQLat 232077250 # Total ticks spent queuing -system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6074 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29684238.47 # Average gap between requests -system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071899 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states -system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states -system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.505612 # Core power per rank (mW) -system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states -system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32421416 # Number of BP lookups -system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450369774 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037855 # Number of instructions committed -system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.649477 # CPI: cycles per instruction -system.cpu.ipc 0.606253 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction -system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction -system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits -system.cpu.dcache.overall_hits::total 168625687 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses -system.cpu.dcache.overall_misses::total 6945 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks -system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 38251 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits -system.cpu.icache.overall_hits::total 69805458 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses -system.cpu.icache.overall_misses::total 40189 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 38251 # number of writebacks -system.cpu.icache.writebacks::total 38251 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23333 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36764 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36764 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36764 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 37072 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36764 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits -system.cpu.l2cache.overall_hits::total 37072 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7629 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses -system.cpu.l2cache.overall_misses::total 7629 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 280789500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 280789500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317508500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 317508500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166371500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 447161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 764669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 317508500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40189 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 40189 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 40189 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.170667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 41 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 41 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252249500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283130000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283130000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150320500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4732 # Transaction distribution -system.membus.trans_dist::ReadExReq 2854 # Transaction distribution -system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7586 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7586 # Request fanout histogram -system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini deleted file mode 100644 index 2c21341f7..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ /dev/null @@ -1,962 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=16 -LSQCheckLoads=true -LSQDepCheckShift=0 -SQEntries=16 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cacheStorePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=2 -decodeWidth=3 -default_p_state=UNDEFINED -dispatchWidth=6 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=16 -fetchQueueSize=32 -fetchToDecodeDelay=3 -fetchTrapLatency=1 -fetchWidth=3 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=32 -numPhysCCRegs=640 -numPhysFloatRegs=192 -numPhysIntRegs=128 -numROBEntries=40 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=1 -renameToROBDelay=1 -renameWidth=3 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BiModeBP -BTBEntries=2048 -BTBTagSize=18 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=8 -write_buffers=16 -writeback_clean=true -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 opList2 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList1.opList2] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 - -[system.cpu.fuPool.FUList4.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList20] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList21] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList22] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList23] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=9 -pipelined=false - -[system.cpu.fuPool.FUList4.opList24] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=33 -pipelined=false - -[system.cpu.fuPool.FUList4.opList25] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList26] -type=OpDesc -eventq_index=0 -opClass=FloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList27] -type=OpDesc -eventq_index=0 -opClass=FloatMisc -opLat=3 -pipelined=true - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=1 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=1 -sequential_access=false -size=32768 -system=system -tag_latency=1 -tags=system.cpu.icache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=1 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=1 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=prefetcher tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=16 -clk_domain=system.cpu_clk_domain -clusivity=mostly_excl -data_latency=12 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=true -prefetcher=system.cpu.l2cache.prefetcher -response_latency=12 -sequential_access=false -size=1048576 -system=system -tag_latency=12 -tags=system.cpu.l2cache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.prefetcher] -type=StridePrefetcher -cache_snoop=false -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -degree=8 -eventq_index=0 -latency=1 -max_conf=7 -min_conf=0 -on_data=true -on_inst=true -on_miss=false -on_read=true -on_write=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -queue_filter=true -queue_size=32 -queue_squash=true -start_conf=4 -sys=system -table_assoc=4 -table_sets=16 -tag_prefetch=true -thresh_conf=4 -use_master_id=true - -[system.cpu.l2cache.tags] -type=RandomRepl -assoc=16 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=12 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1048576 -tag_latency=12 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr deleted file mode 100755 index 2f8aeb16c..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ /dev/null @@ -1,54 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -info: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -info: Increasing stack size by one page. -info: Increasing stack size by one page. -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout deleted file mode 100755 index 2e95c35f3..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 18:05:52 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55337 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing - -Global frequency set at 1000000000000 ticks per second -Eon, Version 1.1 -OO-style eon Time= 0.120000 -Exiting @ tick 124340889500 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt deleted file mode 100644 index f1f3dd777..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ /dev/null @@ -1,1241 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.124341 -sim_ticks 124340889500 -final_tick 124340889500 -sim_freq 1000000000000 -host_inst_rate 97563 -host_op_rate 117136 -host_tick_rate 44430232 -host_mem_usage 304636 -host_seconds 2798.57 -sim_insts 273037218 -sim_ops 327811600 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.physmem.bytes_read::cpu.inst 1894400 -system.physmem.bytes_read::cpu.data 14645312 -system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 -system.physmem.bytes_read::total 16708928 -system.physmem.bytes_inst_read::cpu.inst 1894400 -system.physmem.bytes_inst_read::total 1894400 -system.physmem.num_reads::cpu.inst 29600 -system.physmem.num_reads::cpu.data 228833 -system.physmem.num_reads::cpu.l2cache.prefetcher 2644 -system.physmem.num_reads::total 261077 -system.physmem.bw_read::cpu.inst 15235535 -system.physmem.bw_read::cpu.data 117783555 -system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 -system.physmem.bw_read::total 134379994 -system.physmem.bw_inst_read::cpu.inst 15235535 -system.physmem.bw_inst_read::total 15235535 -system.physmem.bw_total::cpu.inst 15235535 -system.physmem.bw_total::cpu.data 117783555 -system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 -system.physmem.bw_total::total 134379994 -system.physmem.readReqs 261078 -system.physmem.writeReqs 0 -system.physmem.readBursts 261078 -system.physmem.writeBursts 0 -system.physmem.bytesReadDRAM 16708992 -system.physmem.bytesReadWrQ 0 -system.physmem.bytesWritten 0 -system.physmem.bytesReadSys 16708992 -system.physmem.bytesWrittenSys 0 -system.physmem.servicedByWrQ 0 -system.physmem.mergedWrBursts 0 -system.physmem.neitherReadNorWriteReqs 0 -system.physmem.perBankRdBursts::0 1259 -system.physmem.perBankRdBursts::1 69989 -system.physmem.perBankRdBursts::2 1294 -system.physmem.perBankRdBursts::3 10805 -system.physmem.perBankRdBursts::4 42847 -system.physmem.perBankRdBursts::5 121814 -system.physmem.perBankRdBursts::6 160 -system.physmem.perBankRdBursts::7 259 -system.physmem.perBankRdBursts::8 225 -system.physmem.perBankRdBursts::9 562 -system.physmem.perBankRdBursts::10 7823 -system.physmem.perBankRdBursts::11 812 -system.physmem.perBankRdBursts::12 1216 -system.physmem.perBankRdBursts::13 747 -system.physmem.perBankRdBursts::14 656 -system.physmem.perBankRdBursts::15 610 -system.physmem.perBankWrBursts::0 0 -system.physmem.perBankWrBursts::1 0 -system.physmem.perBankWrBursts::2 0 -system.physmem.perBankWrBursts::3 0 -system.physmem.perBankWrBursts::4 0 -system.physmem.perBankWrBursts::5 0 -system.physmem.perBankWrBursts::6 0 -system.physmem.perBankWrBursts::7 0 -system.physmem.perBankWrBursts::8 0 -system.physmem.perBankWrBursts::9 0 -system.physmem.perBankWrBursts::10 0 -system.physmem.perBankWrBursts::11 0 -system.physmem.perBankWrBursts::12 0 -system.physmem.perBankWrBursts::13 0 -system.physmem.perBankWrBursts::14 0 -system.physmem.perBankWrBursts::15 0 -system.physmem.numRdRetry 0 -system.physmem.numWrRetry 0 -system.physmem.totGap 124340880000 -system.physmem.readPktSize::0 0 -system.physmem.readPktSize::1 0 -system.physmem.readPktSize::2 0 -system.physmem.readPktSize::3 0 -system.physmem.readPktSize::4 0 -system.physmem.readPktSize::5 0 -system.physmem.readPktSize::6 261078 -system.physmem.writePktSize::0 0 -system.physmem.writePktSize::1 0 -system.physmem.writePktSize::2 0 -system.physmem.writePktSize::3 0 -system.physmem.writePktSize::4 0 -system.physmem.writePktSize::5 0 -system.physmem.writePktSize::6 0 -system.physmem.rdQLenPdf::0 204158 -system.physmem.rdQLenPdf::1 43358 -system.physmem.rdQLenPdf::2 12121 -system.physmem.rdQLenPdf::3 308 -system.physmem.rdQLenPdf::4 247 -system.physmem.rdQLenPdf::5 209 -system.physmem.rdQLenPdf::6 181 -system.physmem.rdQLenPdf::7 231 -system.physmem.rdQLenPdf::8 123 -system.physmem.rdQLenPdf::9 61 -system.physmem.rdQLenPdf::10 27 -system.physmem.rdQLenPdf::11 20 -system.physmem.rdQLenPdf::12 17 -system.physmem.rdQLenPdf::13 17 -system.physmem.rdQLenPdf::14 0 -system.physmem.rdQLenPdf::15 0 -system.physmem.rdQLenPdf::16 0 -system.physmem.rdQLenPdf::17 0 -system.physmem.rdQLenPdf::18 0 -system.physmem.rdQLenPdf::19 0 -system.physmem.rdQLenPdf::20 0 -system.physmem.rdQLenPdf::21 0 -system.physmem.rdQLenPdf::22 0 -system.physmem.rdQLenPdf::23 0 -system.physmem.rdQLenPdf::24 0 -system.physmem.rdQLenPdf::25 0 -system.physmem.rdQLenPdf::26 0 -system.physmem.rdQLenPdf::27 0 -system.physmem.rdQLenPdf::28 0 -system.physmem.rdQLenPdf::29 0 -system.physmem.rdQLenPdf::30 0 -system.physmem.rdQLenPdf::31 0 -system.physmem.wrQLenPdf::0 0 -system.physmem.wrQLenPdf::1 0 -system.physmem.wrQLenPdf::2 0 -system.physmem.wrQLenPdf::3 0 -system.physmem.wrQLenPdf::4 0 -system.physmem.wrQLenPdf::5 0 -system.physmem.wrQLenPdf::6 0 -system.physmem.wrQLenPdf::7 0 -system.physmem.wrQLenPdf::8 0 -system.physmem.wrQLenPdf::9 0 -system.physmem.wrQLenPdf::10 0 -system.physmem.wrQLenPdf::11 0 -system.physmem.wrQLenPdf::12 0 -system.physmem.wrQLenPdf::13 0 -system.physmem.wrQLenPdf::14 0 -system.physmem.wrQLenPdf::15 0 -system.physmem.wrQLenPdf::16 0 -system.physmem.wrQLenPdf::17 0 -system.physmem.wrQLenPdf::18 0 -system.physmem.wrQLenPdf::19 0 -system.physmem.wrQLenPdf::20 0 -system.physmem.wrQLenPdf::21 0 -system.physmem.wrQLenPdf::22 0 -system.physmem.wrQLenPdf::23 0 -system.physmem.wrQLenPdf::24 0 -system.physmem.wrQLenPdf::25 0 -system.physmem.wrQLenPdf::26 0 -system.physmem.wrQLenPdf::27 0 -system.physmem.wrQLenPdf::28 0 -system.physmem.wrQLenPdf::29 0 -system.physmem.wrQLenPdf::30 0 -system.physmem.wrQLenPdf::31 0 -system.physmem.wrQLenPdf::32 0 -system.physmem.wrQLenPdf::33 0 -system.physmem.wrQLenPdf::34 0 -system.physmem.wrQLenPdf::35 0 -system.physmem.wrQLenPdf::36 0 -system.physmem.wrQLenPdf::37 0 -system.physmem.wrQLenPdf::38 0 -system.physmem.wrQLenPdf::39 0 -system.physmem.wrQLenPdf::40 0 -system.physmem.wrQLenPdf::41 0 -system.physmem.wrQLenPdf::42 0 -system.physmem.wrQLenPdf::43 0 -system.physmem.wrQLenPdf::44 0 -system.physmem.wrQLenPdf::45 0 -system.physmem.wrQLenPdf::46 0 -system.physmem.wrQLenPdf::47 0 -system.physmem.wrQLenPdf::48 0 -system.physmem.wrQLenPdf::49 0 -system.physmem.wrQLenPdf::50 0 -system.physmem.wrQLenPdf::51 0 -system.physmem.wrQLenPdf::52 0 -system.physmem.wrQLenPdf::53 0 -system.physmem.wrQLenPdf::54 0 -system.physmem.wrQLenPdf::55 0 -system.physmem.wrQLenPdf::56 0 -system.physmem.wrQLenPdf::57 0 -system.physmem.wrQLenPdf::58 0 -system.physmem.wrQLenPdf::59 0 -system.physmem.wrQLenPdf::60 0 -system.physmem.wrQLenPdf::61 0 -system.physmem.wrQLenPdf::62 0 -system.physmem.wrQLenPdf::63 0 -system.physmem.bytesPerActivate::samples 67983 -system.physmem.bytesPerActivate::mean 245.745201 -system.physmem.bytesPerActivate::gmean 180.705876 -system.physmem.bytesPerActivate::stdev 200.483366 -system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% -system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% -system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% -system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% -system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% -system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% -system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% -system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% -system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% -system.physmem.bytesPerActivate::total 67983 -system.physmem.totQLat 4612072505 -system.physmem.totMemAccLat 9507285005 -system.physmem.totBusLat 1305390000 -system.physmem.avgQLat 17665.50 -system.physmem.avgBusLat 5000.00 -system.physmem.avgMemAccLat 36415.50 -system.physmem.avgRdBW 134.38 -system.physmem.avgWrBW 0.00 -system.physmem.avgRdBWSys 134.38 -system.physmem.avgWrBWSys 0.00 -system.physmem.peakBW 12800.00 -system.physmem.busUtil 1.05 -system.physmem.busUtilRead 1.05 -system.physmem.busUtilWrite 0.00 -system.physmem.avgRdQLen 1.60 -system.physmem.avgWrQLen 0.00 -system.physmem.readRowHits 193085 -system.physmem.writeRowHits 0 -system.physmem.readRowHitRate 73.96 -system.physmem.writeRowHitRate nan -system.physmem.avgGap 476259.51 -system.physmem.pageHitRate 73.96 -system.physmem_0.actEnergy 450291240 -system.physmem_0.preEnergy 239324085 -system.physmem_0.readEnergy 1773768780 -system.physmem_0.writeEnergy 0 -system.physmem_0.refreshEnergy 9681809280.000002 -system.physmem_0.actBackEnergy 4644193560 -system.physmem_0.preBackEnergy 227236800 -system.physmem_0.actPowerDownEnergy 45907805700 -system.physmem_0.prePowerDownEnergy 3604922400 -system.physmem_0.selfRefreshEnergy 978458700 -system.physmem_0.totalEnergy 67507810545 -system.physmem_0.averagePower 542.925264 -system.physmem_0.totalIdleTime 113563299646 -system.physmem_0.memoryStateTime::IDLE 155533000 -system.physmem_0.memoryStateTime::REF 4097020000 -system.physmem_0.memoryStateTime::SREF 3501663750 -system.physmem_0.memoryStateTime::PRE_PDN 9387944632 -system.physmem_0.memoryStateTime::ACT 6524904104 -system.physmem_0.memoryStateTime::ACT_PDN 100673824014 -system.physmem_1.actEnergy 35171640 -system.physmem_1.preEnergy 18667605 -system.physmem_1.readEnergy 90321000 -system.physmem_1.writeEnergy 0 -system.physmem_1.refreshEnergy 3119298000.000000 -system.physmem_1.actBackEnergy 731861760 -system.physmem_1.preBackEnergy 127236960 -system.physmem_1.actPowerDownEnergy 10304428080 -system.physmem_1.prePowerDownEnergy 3803073120 -system.physmem_1.selfRefreshEnergy 21964091670 -system.physmem_1.totalEnergy 40194673995 -system.physmem_1.averagePower 323.261913 -system.physmem_1.totalIdleTime 122403387505 -system.physmem_1.memoryStateTime::IDLE 207240000 -system.physmem_1.memoryStateTime::REF 1323736000 -system.physmem_1.memoryStateTime::SREF 89902145500 -system.physmem_1.memoryStateTime::PRE_PDN 9903979079 -system.physmem_1.memoryStateTime::ACT 406525995 -system.physmem_1.memoryStateTime::ACT_PDN 22597262926 -system.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.cpu.branchPred.lookups 36038003 -system.cpu.branchPred.condPredicted 19334387 -system.cpu.branchPred.condIncorrect 996297 -system.cpu.branchPred.BTBLookups 17830996 -system.cpu.branchPred.BTBHits 13933502 -system.cpu.branchPred.BTBCorrect 0 -system.cpu.branchPred.BTBHitPct 78.142029 -system.cpu.branchPred.usedRAS 6950609 -system.cpu.branchPred.RASInCorrect 4465 -system.cpu.branchPred.indirectLookups 2515874 -system.cpu.branchPred.indirectHits 2470358 -system.cpu.branchPred.indirectMisses 45516 -system.cpu.branchPredindirectMispredicted 129389 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.cpu.dtb.walker.walks 0 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-system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 -system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 -system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.cpu.toL2Bus.trans_dist::ReadResp 2052102 -system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 -system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 -system.cpu.toL2Bus.trans_dist::HardPFReq 55467 -system.cpu.toL2Bus.trans_dist::UpgradeReq 19 -system.cpu.toL2Bus.trans_dist::UpgradeResp 19 -system.cpu.toL2Bus.trans_dist::ReadExReq 220698 -system.cpu.toL2Bus.trans_dist::ReadExResp 220698 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 727972 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324131 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2183308 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4634013 -system.cpu.toL2Bus.pkt_count::total 6817321 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344 -system.cpu.toL2Bus.pkt_size::total 290846848 -system.cpu.toL2Bus.snoops 55544 -system.cpu.toL2Bus.snoopTraffic 4928 -system.cpu.toL2Bus.snoop_fanout::samples 2328287 -system.cpu.toL2Bus.snoop_fanout::mean 0.131576 -system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84% -system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00% -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 2 -system.cpu.toL2Bus.snoop_fanout::total 2328287 -system.cpu.toL2Bus.reqLayer0.occupancy 4544048500 -system.cpu.toL2Bus.reqLayer0.utilization 3.7 -system.cpu.toL2Bus.respLayer0.occupancy 1092026360 -system.cpu.toL2Bus.respLayer0.utilization 0.9 -system.cpu.toL2Bus.respLayer1.occupancy 2317274956 -system.cpu.toL2Bus.respLayer1.utilization 1.9 -system.membus.snoop_filter.tot_requests 261096 -system.membus.snoop_filter.hit_single_requests 253777 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500 -system.membus.trans_dist::ReadResp 260342 -system.membus.trans_dist::UpgradeReq 18 -system.membus.trans_dist::ReadExReq 735 -system.membus.trans_dist::ReadExResp 735 -system.membus.trans_dist::ReadSharedReq 260343 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173 -system.membus.pkt_count::total 522173 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928 -system.membus.pkt_size::total 16708928 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 261096 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 261096 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 261096 -system.membus.reqLayer0.occupancy 316188421 -system.membus.reqLayer0.utilization 0.3 -system.membus.respLayer1.occupancy 1389693354 -system.membus.respLayer1.utilization 1.1 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index 89604511e..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,330 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index a91025695..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1,53 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -info: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -info: Increasing stack size by one page. -info: Increasing stack size by one page. -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index 728509d4f..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 17:56:13 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54231 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic - -Global frequency set at 1000000000000 ticks per second -Eon, Version 1.1 -OO-style eon Time= 0.200000 -Exiting @ tick 201717314000 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index 2e5c48f3e..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,262 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.201717 -sim_ticks 201717314000 -final_tick 201717314000 -sim_freq 1000000000000 -host_inst_rate 634159 -host_op_rate 761378 -host_tick_rate 468510100 -host_mem_usage 279924 -host_seconds 430.55 -sim_insts 273037595 -sim_ops 327811950 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.physmem.bytes_read::cpu.inst 1394641096 -system.physmem.bytes_read::cpu.data 480709216 -system.physmem.bytes_read::total 1875350312 -system.physmem.bytes_inst_read::cpu.inst 1394641096 -system.physmem.bytes_inst_read::total 1394641096 -system.physmem.bytes_written::cpu.data 400047763 -system.physmem.bytes_written::total 400047763 -system.physmem.num_reads::cpu.inst 348660274 -system.physmem.num_reads::cpu.data 86300511 -system.physmem.num_reads::total 434960785 -system.physmem.num_writes::cpu.data 82063567 -system.physmem.num_writes::total 82063567 -system.physmem.bw_read::cpu.inst 6913839315 -system.physmem.bw_read::cpu.data 2383083566 -system.physmem.bw_read::total 9296922881 -system.physmem.bw_inst_read::cpu.inst 6913839315 -system.physmem.bw_inst_read::total 6913839315 -system.physmem.bw_write::cpu.data 1983209845 -system.physmem.bw_write::total 1983209845 -system.physmem.bw_total::cpu.inst 6913839315 -system.physmem.bw_total::cpu.data 4366293411 -system.physmem.bw_total::total 11280132726 -system.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.hits 0 -system.cpu.istage2_mmu.stage2_tlb.misses 0 -system.cpu.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.cpu.itb.walker.walks 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.itb.walker.walkRequestOrigin::total 0 -system.cpu.itb.inst_hits 0 -system.cpu.itb.inst_misses 0 -system.cpu.itb.read_hits 0 -system.cpu.itb.read_misses 0 -system.cpu.itb.write_hits 0 -system.cpu.itb.write_misses 0 -system.cpu.itb.flush_tlb 0 -system.cpu.itb.flush_tlb_mva 0 -system.cpu.itb.flush_tlb_mva_asid 0 -system.cpu.itb.flush_tlb_asid 0 -system.cpu.itb.flush_entries 0 -system.cpu.itb.align_faults 0 -system.cpu.itb.prefetch_faults 0 -system.cpu.itb.domain_faults 0 -system.cpu.itb.perms_faults 0 -system.cpu.itb.read_accesses 0 -system.cpu.itb.write_accesses 0 -system.cpu.itb.inst_accesses 0 -system.cpu.itb.hits 0 -system.cpu.itb.misses 0 -system.cpu.itb.accesses 0 -system.cpu.workload.numSyscalls 191 -system.cpu.pwrStateResidencyTicks::ON 201717314000 -system.cpu.numCycles 403434629 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 273037595 -system.cpu.committedOps 327811950 -system.cpu.num_int_alu_accesses 258331481 -system.cpu.num_fp_alu_accesses 114216705 -system.cpu.num_func_calls 12448615 -system.cpu.num_conditional_control_insts 15799338 -system.cpu.num_int_insts 258331481 -system.cpu.num_fp_insts 114216705 -system.cpu.num_int_register_reads 938030601 -system.cpu.num_int_register_writes 162499657 -system.cpu.num_fp_register_reads 180262959 -system.cpu.num_fp_register_writes 126152315 -system.cpu.num_cc_register_reads 985884626 -system.cpu.num_cc_register_writes 76361749 -system.cpu.num_mem_refs 168107829 -system.cpu.num_load_insts 85732235 -system.cpu.num_store_insts 82375594 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 403434629 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 30563491 -system.cpu.op_class::No_OpClass 0 0.00% 0.00% -system.cpu.op_class::IntAlu 104312493 31.82% 31.82% -system.cpu.op_class::IntMult 2145905 0.65% 32.48% -system.cpu.op_class::IntDiv 0 0.00% 32.48% -system.cpu.op_class::FloatAdd 0 0.00% 32.48% -system.cpu.op_class::FloatCmp 0 0.00% 32.48% -system.cpu.op_class::FloatCvt 0 0.00% 32.48% -system.cpu.op_class::FloatMult 0 0.00% 32.48% -system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% -system.cpu.op_class::FloatDiv 0 0.00% 32.48% -system.cpu.op_class::FloatMisc 0 0.00% 32.48% -system.cpu.op_class::FloatSqrt 0 0.00% 32.48% -system.cpu.op_class::SimdAdd 0 0.00% 32.48% -system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% -system.cpu.op_class::SimdAlu 0 0.00% 32.48% -system.cpu.op_class::SimdCmp 0 0.00% 32.48% -system.cpu.op_class::SimdCvt 0 0.00% 32.48% -system.cpu.op_class::SimdMisc 0 0.00% 32.48% -system.cpu.op_class::SimdMult 0 0.00% 32.48% -system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% -system.cpu.op_class::SimdShift 0 0.00% 32.48% -system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% -system.cpu.op_class::SimdSqrt 0 0.00% 32.48% -system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% -system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% -system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% -system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% -system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% -system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% -system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% -system.cpu.op_class::MemRead 44185161 13.48% 62.20% -system.cpu.op_class::MemWrite 55008376 16.78% 78.98% -system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% -system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 327812145 -system.membus.snoop_filter.tot_requests 0 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 -system.membus.trans_dist::ReadReq 434895828 -system.membus.trans_dist::ReadResp 434906723 -system.membus.trans_dist::WriteReq 82052672 -system.membus.trans_dist::WriteResp 82052672 -system.membus.trans_dist::SoftPFReq 54062 -system.membus.trans_dist::SoftPFResp 54062 -system.membus.trans_dist::LoadLockedReq 10895 -system.membus.trans_dist::StoreCondReq 10895 -system.membus.trans_dist::StoreCondResp 10895 -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 -system.membus.pkt_count::total 1034048704 -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 -system.membus.pkt_size::total 2275398075 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 517024352 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 517024352 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 517024352 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index e57f29bfa..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,499 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index a91025695..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1,53 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -info: Increasing stack size by one page. -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -info: Increasing stack size by one page. -info: Increasing stack size by one page. -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout deleted file mode 100755 index 7aa5c7a76..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 17:56:13 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54216 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing - -Global frequency set at 1000000000000 ticks per second -Eon, Version 1.1 -OO-style eon Time= 0.510000 -Exiting @ tick 517297855500 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index c9e238fff..000000000 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,675 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.517298 -sim_ticks 517297855500 -final_tick 517297855500 -sim_freq 1000000000000 -host_inst_rate 473413 -host_op_rate 568350 -host_tick_rate 897909978 -host_mem_usage 288888 -host_seconds 576.11 -sim_insts 272739286 -sim_ops 327433744 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 -system.physmem.bytes_read::cpu.inst 166912 -system.physmem.bytes_read::cpu.data 270336 -system.physmem.bytes_read::total 437248 -system.physmem.bytes_inst_read::cpu.inst 166912 -system.physmem.bytes_inst_read::total 166912 -system.physmem.num_reads::cpu.inst 2608 -system.physmem.num_reads::cpu.data 4224 -system.physmem.num_reads::total 6832 -system.physmem.bw_read::cpu.inst 322661 -system.physmem.bw_read::cpu.data 522593 -system.physmem.bw_read::total 845254 -system.physmem.bw_inst_read::cpu.inst 322661 -system.physmem.bw_inst_read::total 322661 -system.physmem.bw_total::cpu.inst 322661 -system.physmem.bw_total::cpu.data 522593 -system.physmem.bw_total::total 845254 -system.pwrStateResidencyTicks::UNDEFINED 517297855500 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 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-system.membus.respLayer1.occupancy 34160000 -system.membus.respLayer1.utilization 0.0 - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/test.py b/tests/long/se/30.eon/test.py deleted file mode 100644 index c610c1699..000000000 --- a/tests/long/se/30.eon/test.py +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Korey Sewell - -m5.util.addToPath('../configs/common') -from cpu2000 import eon_cook - -workload = eon_cook(isa, opsys, 'mdred') -root.system.cpu[0].workload = workload.makeProcess() |