diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:29:27 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:29:27 -0500 |
| commit | 44e599a1a4843db07cb77cfedc136e8e994016cf (patch) | |
| tree | 53636c25ce8a6854fdf11c62ec12c15fdd47223e | |
| parent | b5160ba2c349cb3d913cfdce01f7b11aa13df8ed (diff) | |
| download | gem5-44e599a1a4843db07cb77cfedc136e8e994016cf.tar.xz | |
ARM: Fix up stats for previous changes to condition codes
40 files changed, 4181 insertions, 4163 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 408898e50..df78a3a5d 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:06:31 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 13:57:03 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -42,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 196513140500 because target called exit() +Exiting @ tick 189747670000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index cd3ca8de5..b2bd08a2b 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 169360 # Simulator instruction rate (inst/s) -host_mem_usage 217476 # Number of bytes of host memory used -host_seconds 3556.69 # Real time elapsed on the host -host_tick_rate 55251704 # Simulator tick rate (ticks/s) +host_inst_rate 210962 # Simulator instruction rate (inst/s) +host_mem_usage 262196 # Number of bytes of host memory used +host_seconds 2855.31 # Real time elapsed on the host +host_tick_rate 66454392 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359865 # Number of instructions simulated -sim_seconds 0.196513 # Number of seconds simulated -sim_ticks 196513140500 # Number of ticks simulated +sim_insts 602359850 # Number of instructions simulated +sim_seconds 0.189748 # Number of seconds simulated +sim_ticks 189747670000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 75744427 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 81879675 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1640 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3832102 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted -system.cpu.commit.branches 70828614 # Number of branches committed -system.cpu.commit.bw_lim_events 7897771 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 74615208 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 80130233 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1670 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3884107 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 80516162 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 86913734 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1397693 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 3943213 # The number of times a branch was mispredicted +system.cpu.commit.branches 70828611 # Number of branches committed +system.cpu.commit.bw_lim_events 15126616 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 379244728 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.588315 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359901 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 6307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 75686006 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 366955970 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.641505 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.022822 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118814632 32.38% 32.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 123407521 33.63% 66.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52313499 14.26% 80.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12481991 3.40% 83.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20938472 5.71% 89.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13691845 3.73% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7616390 2.08% 95.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2565004 0.70% 95.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15126616 4.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 379244728 # Number of insts commited each cycle -system.cpu.commit.count 602359916 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 366955970 # Number of insts commited each cycle +system.cpu.commit.count 602359901 # Number of instructions committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.int_insts 533522691 # Number of committed integer instructions. -system.cpu.commit.loads 148952607 # Number of loads committed +system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. +system.cpu.commit.loads 148952604 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.refs 219173633 # Number of memory references committed +system.cpu.commit.refs 219173627 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 602359865 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated -system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.652478 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1356 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 148500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 139395234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 139153026 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3158848000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001738 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 242208 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 46247 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195961 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 1340 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 1340 # number of StoreCondReq hits +system.cpu.committedInsts 602359850 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359850 # Number of Instructions Simulated +system.cpu.cpi 0.630014 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.630014 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1349 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.011119 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 138720806 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13339.905680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8226.668223 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 138476956 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3252936000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001758 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 243850 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 46844 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1620703000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 197006 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1337 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1337 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 67926304 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26708191996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.021482 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1491227 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1243368 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247859 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17857.107875 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.095668 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 67921343 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 26717590518 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1496188 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1248875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2561939027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247313 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 466.592209 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2191 # number of cycles access was blocked +system.cpu.dcache.avg_refs 464.535408 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9589506 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 208812765 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17229.974009 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency -system.cpu.dcache.demand_hits 207079330 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29867039996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008301 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1733435 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1289615 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4114516505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 443820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 208138337 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 17224.064370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency +system.cpu.dcache.demand_hits 206398299 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29970526518 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1740038 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1295719 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4182642027 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 444319 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4094.816119 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 208138337 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 17224.064370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 207079330 # number of overall hits -system.cpu.dcache.overall_miss_latency 29867039996 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008301 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1733435 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1289615 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4114516505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 443820 # number of overall MSHR misses +system.cpu.dcache.overall_hits 206398299 # number of overall hits +system.cpu.dcache.overall_miss_latency 29970526518 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1740038 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1295719 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4182642027 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 444319 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439722 # number of replacements -system.cpu.dcache.sampled_refs 443818 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 440221 # number of replacements +system.cpu.dcache.sampled_refs 444317 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.849519 # Cycle average of tags in use -system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394264 # number of writebacks -system.cpu.decode.BlockedCycles 64227537 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 1274 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 5983982 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 722350979 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 163737957 # Number of cycles decode is idle -system.cpu.decode.RunCycles 138388023 # Number of cycles decode is running -system.cpu.decode.SquashCycles 12871984 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 4747 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 12891210 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.816119 # Cycle average of tags in use +system.cpu.dcache.total_refs 206400979 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88948000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 394697 # number of writebacks +system.cpu.decode.BlockedCycles 57854165 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1286 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 5859491 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 711052352 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 160285716 # Number of cycles decode is idle +system.cpu.decode.RunCycles 140722772 # Number of cycles decode is running +system.cpu.decode.SquashCycles 11629973 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4744 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 8093316 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 88398894 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 71395519 # Number of cache lines fetched -system.cpu.fetch.Cycles 153789076 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 942755 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 689805737 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4451587 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.224919 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 71395519 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 77137437 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.755114 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 392116711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.872365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.899483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 86913734 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 70195415 # Number of cache lines fetched +system.cpu.fetch.Cycles 151344798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 922649 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 678928974 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4471477 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.229025 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 70195415 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 76012901 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.789031 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 378585942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.910009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.919514 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 238327790 60.78% 60.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25111973 6.40% 67.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18227974 4.65% 71.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22524916 5.74% 77.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11352449 2.90% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12221762 3.12% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4491606 1.15% 84.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7291145 1.86% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52567096 13.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 227241307 60.02% 60.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25123172 6.64% 66.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17643544 4.66% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 21901113 5.78% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11234102 2.97% 80.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11763660 3.11% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4451384 1.18% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7295384 1.93% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 51932276 13.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392116711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 378585942 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 71395519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35429.359823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34341.412742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 71394613 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32099000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 70195415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35447.995666 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34312.158470 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 70194492 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32718500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 906 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 24794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 923 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 191 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 25116500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 732 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 99159.184722 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 96156.838356 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 71395519 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35429.359823 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency -system.cpu.icache.demand_hits 71394613 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32099000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 70195415 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35447.995666 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency +system.cpu.icache.demand_hits 70194492 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32718500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 906 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 184 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 24794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 923 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 191 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 25116500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 732 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.307172 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 626.402984 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.305861 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 70195415 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35447.995666 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 71394613 # number of overall hits -system.cpu.icache.overall_miss_latency 32099000 # number of overall miss cycles +system.cpu.icache.overall_hits 70194492 # number of overall hits +system.cpu.icache.overall_miss_latency 32718500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 906 # number of overall misses -system.cpu.icache.overall_mshr_hits 184 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 24794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 923 # number of overall misses +system.cpu.icache.overall_mshr_hits 191 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 25116500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 732 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 31 # number of replacements -system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks. +system.cpu.icache.replacements 43 # number of replacements +system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 629.087764 # Cycle average of tags in use -system.cpu.icache.total_refs 71394613 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 626.402984 # Cycle average of tags in use +system.cpu.icache.total_refs 70194492 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 73704412 # Number of branches executed -system.cpu.iew.exec_nop 61098 # number of nop insts executed -system.cpu.iew.exec_rate 1.622472 # Inst execution rate -system.cpu.iew.exec_refs 239165331 # number of memory reference insts executed -system.cpu.iew.exec_stores 73423365 # Number of stores executed +system.cpu.idleCycles 909399 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4390377 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 74630961 # Number of branches executed +system.cpu.iew.exec_nop 61033 # number of nop insts executed +system.cpu.iew.exec_rate 1.692381 # Inst execution rate +system.cpu.iew.exec_refs 240248450 # number of memory reference insts executed +system.cpu.iew.exec_stores 74641760 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2956217 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 82187861 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 689217371 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 165741966 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6134058 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 637674087 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25252 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 692845 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 172870468 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5721 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3255991 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 80793372 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 678046798 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 165606690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6567715 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 642250536 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7466 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3846 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 11629973 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 38806 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 25082678 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 12320 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 25624582 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 272347 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 611520 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 15892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 27153747 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 11966835 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 736448308 # num instructions consuming a value -system.cpu.iew.wb_count 631945179 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.594878 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 522665 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 15873 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 23917863 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 10572349 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 522665 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 636797 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3753580 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 620419783 # num instructions consuming a value +system.cpu.iew.wb_count 636524370 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.661688 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 438096934 # num instructions producing a value -system.cpu.iew.wb_rate 1.607895 # insts written-back per cycle -system.cpu.iew.wb_sent 632881856 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads -system.cpu.int_regfile_writes 495432851 # number of integer regfile writes -system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 410524106 # num instructions producing a value +system.cpu.iew.wb_rate 1.677292 # insts written-back per cycle +system.cpu.iew.wb_sent 637578270 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 3205843747 # number of integer regfile reads +system.cpu.int_regfile_writes 660980878 # number of integer regfile writes +system.cpu.ipc 1.587265 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.587265 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 404976250 62.42% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6544 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 167780307 25.86% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76055147 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 643808145 # Type of FU issued +system.cpu.iq.FU_type_0::total 648818251 # Type of FU issued system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 3945011 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt 3420971 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005273 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164650 4.81% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2528736 73.92% 78.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 727585 21.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 776263645 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 689149113 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 643808145 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7160 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 86496318 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 392116711 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.641879 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 652239202 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1679971887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 636524354 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 753225503 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 677978706 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 648818251 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7059 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 74717328 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 328508 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 752 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 185330852 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 378585942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.713794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.641678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99098284 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107923682 28.51% 54.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72401438 19.12% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48461841 12.80% 86.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21953161 5.80% 92.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16842853 4.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6368110 1.68% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3821983 1.01% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1714590 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392116711 # Number of insts issued each cycle -system.cpu.iq.rate 1.638079 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 378585942 # Number of insts issued each cycle +system.cpu.iq.rate 1.709687 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -415,114 +415,116 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247858 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.577877 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.064273 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 189420 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2006502500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235772 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58438 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825490000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235772 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58438 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 196680 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34348.019439 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.694669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 163962 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1123798500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.166351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1017300500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166321 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32712 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_accesses 247312 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.062545 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.030776 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 188954 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2003142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235969 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58358 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822989000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58358 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 197735 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34360.710576 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.859290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 165001 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1124763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32734 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 1018296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32727 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394264 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394264 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6213.636364 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 394697 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 394697 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.739861 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 330 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 4.758732 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 2050500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444538 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34340.043442 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353382 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3130301000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.205058 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91156 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2842790500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.205044 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 445047 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34337.872700 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 353955 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3127905500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.204680 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91092 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 2841285000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.204664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487109 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1908.878881 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15928.587231 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058254 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486102 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 445047 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34337.872700 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353382 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3130301000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.205058 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91156 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2842790500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.205044 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 353955 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3127905500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.204680 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91092 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 2841285000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.204664 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72953 # number of replacements -system.cpu.l2cache.sampled_refs 88472 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 72893 # number of replacements +system.cpu.l2cache.sampled_refs 88408 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17837.885854 # Cycle average of tags in use -system.cpu.l2cache.total_refs 419345 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17837.466112 # Cycle average of tags in use +system.cpu.l2cache.total_refs 420710 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58134 # number of writebacks -system.cpu.memDep0.conflictingLoads 25914382 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23086559 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 176106355 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82187861 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 922126402 # number of misc regfile reads -system.cpu.misc_regfile_writes 2682 # number of misc regfile writes -system.cpu.numCycles 393026282 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58103 # number of writebacks +system.cpu.memDep0.conflictingLoads 15581715 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 22335111 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 172870468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80793372 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 912454826 # number of misc regfile reads +system.cpu.misc_regfile_writes 2676 # number of misc regfile writes +system.cpu.numCycles 379495341 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 9628088 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 471021820 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 50048668 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 176696020 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 2034394520 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 711291370 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 553214444 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 138291459 # Number of cycles rename is running -system.cpu.rename.SquashCycles 12871984 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 54521168 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 82192621 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 2034394424 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 107992 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 6480 # count of serializing insts renamed -system.cpu.rename.skidInsts 91409775 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6477 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1060565987 # The number of ROB reads -system.cpu.rob.rob_writes 1391311417 # The number of ROB writes -system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 7724801 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 44461884 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 169816321 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 4814649 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3254253647 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 699315987 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 723227895 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 139243664 # Number of cycles rename is running +system.cpu.rename.SquashCycles 11629973 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 50068276 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 95810424 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3254253519 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 102907 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 6090 # count of serializing insts renamed +system.cpu.rename.skidInsts 82758432 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 6087 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1029874649 # The number of ROB reads +system.cpu.rob.rob_writes 1367730511 # The number of ROB writes +system.cpu.timesIdled 36653 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 3089a85c4..2dd995d75 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4079554 # Simulator instruction rate (inst/s) -host_mem_usage 206080 # Number of bytes of host memory used -host_seconds 147.65 # Real time elapsed on the host -host_tick_rate 2039852029 # Simulator tick rate (ticks/s) +host_inst_rate 2791643 # Simulator instruction rate (inst/s) +host_mem_usage 253504 # Number of bytes of host memory used +host_seconds 215.77 # Real time elapsed on the host +host_tick_rate 1395873441 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359851 # Number of instructions simulated sim_seconds 0.301191 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 602359851 # Number of instructions executed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_int_insts 533522639 # number of integer instructions -system.cpu.num_int_register_reads 1694262461 # number of times the integer registers were read -system.cpu.num_int_register_writes 458076290 # number of times the integer registers were written +system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index e356c348b..ba03a3195 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2132031 # Simulator instruction rate (inst/s) -host_mem_usage 213820 # Number of bytes of host memory used -host_seconds 281.61 # Real time elapsed on the host -host_tick_rate 2829324901 # Simulator tick rate (ticks/s) +host_inst_rate 1298278 # Simulator instruction rate (inst/s) +host_mem_usage 260992 # Number of bytes of host memory used +host_seconds 462.46 # Real time elapsed on the host +host_tick_rate 1722888732 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600398281 # Number of instructions simulated sim_seconds 0.796763 # Number of seconds simulated @@ -259,8 +259,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 600398281 # Number of instructions executed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_int_insts 533522639 # number of integer instructions -system.cpu.num_int_register_reads 1840897552 # number of times the integer registers were read -system.cpu.num_int_register_writes 458076290 # number of times the integer registers were written +system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written system.cpu.num_load_insts 148952594 # Number of load instructions system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 932becd1c..c9bf50a5d 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2011 15:06:32 -M5 started May 2 2011 15:06:36 -M5 executing on u200439-lin.austin.arm.com +M5 compiled May 4 2011 15:43:04 +M5 started May 4 2011 15:43:52 +M5 executing on nadc-0364 command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 82662703500 because m5_exit instruction encountered +Exiting @ tick 82034111500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 7f4d01ec7..48678b994 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,491 +1,491 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 157394 # Simulator instruction rate (inst/s) -host_mem_usage 389256 # Number of bytes of host memory used -host_seconds 329.61 # Real time elapsed on the host -host_tick_rate 250791706 # Simulator tick rate (ticks/s) +host_inst_rate 134958 # Simulator instruction rate (inst/s) +host_mem_usage 390376 # Number of bytes of host memory used +host_seconds 384.42 # Real time elapsed on the host +host_tick_rate 213396272 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51877985 # Number of instructions simulated -sim_seconds 0.082663 # Number of seconds simulated -sim_ticks 82662703500 # Number of ticks simulated +sim_insts 51880909 # Number of instructions simulated +sim_seconds 0.082034 # Number of seconds simulated +sim_ticks 82034111500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9219891 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 11725604 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 157156 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 663969 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11218057 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 13199466 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 789166 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 640286 # The number of times a branch was mispredicted -system.cpu.commit.branches 8429112 # Number of branches committed -system.cpu.commit.bw_lim_events 798153 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9102571 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11540733 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 156710 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 673757 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10989170 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 12912764 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 784193 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 650030 # The number of times a branch was mispredicted +system.cpu.commit.branches 8429925 # Number of branches committed +system.cpu.commit.bw_lim_events 1000240 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 52001215 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2962888 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 16092788 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 93510390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.556101 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.349439 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52004139 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2962847 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14909049 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 92471034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.562383 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.400559 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71869411 76.86% 76.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10616143 11.35% 88.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3483966 3.73% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1643130 1.76% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3524025 3.77% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 741321 0.79% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 539866 0.58% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 294375 0.31% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 798153 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71745851 77.59% 77.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10051673 10.87% 88.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3131233 3.39% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1338201 1.45% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3541768 3.83% 97.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 776921 0.84% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 574229 0.62% 98.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 310918 0.34% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1000240 1.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 93510390 # Number of insts commited each cycle -system.cpu.commit.count 52001215 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 92471034 # Number of insts commited each cycle +system.cpu.commit.count 52004139 # Number of instructions committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.function_calls 530196 # Number of function calls committed. -system.cpu.commit.int_insts 42424846 # Number of committed integer instructions. -system.cpu.commit.loads 9179779 # Number of loads committed +system.cpu.commit.function_calls 530212 # Number of function calls committed. +system.cpu.commit.int_insts 42426831 # Number of committed integer instructions. +system.cpu.commit.loads 9179406 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.refs 16257314 # Number of memory references committed +system.cpu.commit.refs 16257275 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 51877985 # Number of Instructions Simulated -system.cpu.committedInsts_total 51877985 # Number of Instructions Simulated -system.cpu.cpi 3.186812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.186812 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 111585 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 111585 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.470534 # average LoadLockedReq miss latency +system.cpu.committedInsts 51880909 # Number of Instructions Simulated +system.cpu.committedInsts_total 51880909 # Number of Instructions Simulated +system.cpu.cpi 3.162401 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.162401 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 111119 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 111119 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14959.662577 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.665522 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 105103 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 105103 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 97071000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058090 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6482 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6482 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 951 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65540500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049568 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11867.723914 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 104599 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 104599 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 97537000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058676 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6520 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6520 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 971 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65854000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049937 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5531 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9397671 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9397671 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14774.624992 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5549 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9452855 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9452855 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14680.380096 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13259.657075 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13336.103253 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 8908615 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8908615 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7225619000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.052040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 489056 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 489056 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 240430 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3296695500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026456 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 8917516 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8917516 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7858980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.056633 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 535339 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 535339 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 286475 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3318876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026327 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248626 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199517000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 105030 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 105030 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 105030 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 105030 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6663090 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6663090 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 39945.828494 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 248864 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199227500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 105008 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 105008 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 105008 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 105008 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6663158 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6663158 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 39939.228652 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38492.934326 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.801730 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4618865 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4618865 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81658261253 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.306798 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2044225 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2044225 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1873609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6567510483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_hits::0 4619008 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4619008 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 81641774250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.306784 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2044150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2044150 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1873534 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6569876484 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025606 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 170616 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 943852693 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7367.210748 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25538.461538 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.477815 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 949 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 6991483 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 664000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 944300187 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7573.849650 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26206.896552 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.474872 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 1144 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 8664484 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 760000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 16060761 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 16116013 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16060761 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 35086.467018 # average overall miss latency +system.cpu.dcache.demand_accesses::total 16116013 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 34697.087001 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13527480 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23573.835425 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13536524 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13527480 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88883880253 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.157731 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13536524 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 89500754250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.160058 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2533281 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2579489 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2533281 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2114039 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9864205983 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.026103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 2579489 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2160009 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9888752484 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.026029 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 419242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 419480 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.750766 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 16060761 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.748800 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999509 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses::0 16116013 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16060761 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 35086.467018 # average overall miss latency +system.cpu.dcache.overall_accesses::total 16116013 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 34697.087001 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23573.835425 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13527480 # number of overall hits +system.cpu.dcache.overall_hits::0 13536524 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13527480 # number of overall hits -system.cpu.dcache.overall_miss_latency 88883880253 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.157731 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13536524 # number of overall hits +system.cpu.dcache.overall_miss_latency 89500754250 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.160058 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2533281 # number of overall misses +system.cpu.dcache.overall_misses::0 2579489 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2533281 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2114039 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9864205983 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.026103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 2579489 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2160009 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9888752484 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.026029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 419242 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39143369693 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 419480 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39143527687 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 422530 # number of replacements -system.cpu.dcache.sampled_refs 423042 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 422827 # number of replacements +system.cpu.dcache.sampled_refs 423339 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.750766 # Cycle average of tags in use -system.cpu.dcache.total_refs 13739480 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 390905 # number of writebacks -system.cpu.decode.BlockedCycles 53935385 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 70801 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 1222673 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 76253610 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 23916717 # Number of cycles decode is idle -system.cpu.decode.RunCycles 14472094 # Number of cycles decode is running -system.cpu.decode.SquashCycles 2561252 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 234958 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 1186166 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 35208809 # DTB accesses -system.cpu.dtb.align_faults 1597 # Number of TLB faults due to alignment restrictions +system.cpu.dcache.tagsinuse 511.748800 # Cycle average of tags in use +system.cpu.dcache.total_refs 13747880 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48233000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 391156 # number of writebacks +system.cpu.decode.BlockedCycles 53430670 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 71225 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 1206438 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 75318678 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23535399 # Number of cycles decode is idle +system.cpu.decode.RunCycles 14503134 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2432206 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 234974 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1001803 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 35326890 # DTB accesses +system.cpu.dtb.align_faults 1798 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2756 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2918 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 35136197 # DTB hits +system.cpu.dtb.hits 35252902 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 72612 # DTB misses -system.cpu.dtb.perms_faults 1160 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 1027 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 27716932 # DTB read accesses -system.cpu.dtb.read_hits 27655119 # DTB read hits -system.cpu.dtb.read_misses 61813 # DTB read misses -system.cpu.dtb.write_accesses 7491877 # DTB write accesses -system.cpu.dtb.write_hits 7481078 # DTB write hits -system.cpu.dtb.write_misses 10799 # DTB write misses -system.cpu.fetch.Branches 13199466 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6541408 # Number of cache lines fetched -system.cpu.fetch.Cycles 16046672 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 257127 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 63922910 # Number of instructions fetch has processed -system.cpu.fetch.ItlbSquashes 4120 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.MiscStallCycles 17774 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1040401 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7293 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.branchRate 0.079839 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6539916 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 10009057 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.386649 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 96071614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.819308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.074078 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.misses 73988 # DTB misses +system.cpu.dtb.perms_faults 1167 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 1080 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 27838344 # DTB read accesses +system.cpu.dtb.read_hits 27775801 # DTB read hits +system.cpu.dtb.read_misses 62543 # DTB read misses +system.cpu.dtb.write_accesses 7488546 # DTB write accesses +system.cpu.dtb.write_hits 7477101 # DTB write hits +system.cpu.dtb.write_misses 11445 # DTB write misses +system.cpu.fetch.Branches 12912764 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6451359 # Number of cache lines fetched +system.cpu.fetch.Cycles 15867747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 266743 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 62809765 # Number of instructions fetch has processed +system.cpu.fetch.ItlbSquashes 3974 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.MiscStallCycles 15287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1056460 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7130 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.branchRate 0.078704 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6449881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9886764 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.382827 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 94903212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.817121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.069432 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80041495 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1277020 1.33% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1747355 1.82% 86.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1275318 1.33% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4729503 4.92% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 796752 0.83% 93.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 838393 0.87% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743786 0.77% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4621992 4.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79052742 83.30% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1297873 1.37% 84.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713716 1.81% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1275370 1.34% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4689358 4.94% 92.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 820409 0.86% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 791742 0.83% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 709911 0.75% 95.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4552091 4.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 96071614 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 5589 # number of floating regfile reads -system.cpu.fp_regfile_writes 1920 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 6541316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6541316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14764.035941 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 94903212 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 5507 # number of floating regfile reads +system.cpu.fp_regfile_writes 1900 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses::0 6451264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6451264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14776.807600 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12016.810358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12031.141929 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 5995343 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5995343 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8060764995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.083465 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 545973 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 545973 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43426 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6039011995 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076827 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 5903994 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5903994 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8086903495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.084831 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 547270 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 547270 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 44668 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6046875996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.077908 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 502547 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs 7482.701149 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 502602 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable_latency 5118000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 9184.960000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11.930746 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked +system.cpu.icache.avg_refs 11.746927 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 100 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 650995 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 918496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 6541316 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 6451264 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6541316 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14764.035941 # average overall miss latency +system.cpu.icache.demand_accesses::total 6451264 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14776.807600 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 5995343 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 12031.141929 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 5903994 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5995343 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8060764995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.083465 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 5903994 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8086903495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.084831 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 545973 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 547270 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 545973 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43426 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6039011995 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.076827 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 547270 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 44668 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6046875996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.077908 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 502547 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 502602 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 496.616847 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.969955 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 6541316 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 496.931894 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.970570 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses::0 6451264 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6541316 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14764.035941 # average overall miss latency +system.cpu.icache.overall_accesses::total 6451264 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14776.807600 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12031.141929 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 5995343 # number of overall hits +system.cpu.icache.overall_hits::0 5903994 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 5995343 # number of overall hits -system.cpu.icache.overall_miss_latency 8060764995 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.083465 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 5903994 # number of overall hits +system.cpu.icache.overall_miss_latency 8086903495 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.084831 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 545973 # number of overall misses +system.cpu.icache.overall_misses::0 547270 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 545973 # number of overall misses -system.cpu.icache.overall_mshr_hits 43426 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6039011995 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.076827 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 547270 # number of overall misses +system.cpu.icache.overall_mshr_hits 44668 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6046875996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.077908 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 502547 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_misses 502602 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 5118000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 502000 # number of replacements -system.cpu.icache.sampled_refs 502512 # Sample count of references to valid blocks. +system.cpu.icache.replacements 502087 # number of replacements +system.cpu.icache.sampled_refs 502599 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 496.616847 # Cycle average of tags in use -system.cpu.icache.total_refs 5995343 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 6206760000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 41552 # number of writebacks -system.cpu.idleCycles 69253794 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 710007 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 10210898 # Number of branches executed -system.cpu.iew.exec_nop 166890 # number of nop insts executed -system.cpu.iew.exec_rate 0.475154 # Inst execution rate -system.cpu.iew.exec_refs 35938773 # number of memory reference insts executed -system.cpu.iew.exec_stores 7790783 # Number of stores executed +system.cpu.icache.tagsinuse 496.931894 # Cycle average of tags in use +system.cpu.icache.total_refs 5903994 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 6080140000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 41635 # number of writebacks +system.cpu.idleCycles 69165012 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 732544 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 10340571 # Number of branches executed +system.cpu.iew.exec_nop 166091 # number of nop insts executed +system.cpu.iew.exec_rate 0.481516 # Inst execution rate +system.cpu.iew.exec_refs 36056816 # number of memory reference insts executed +system.cpu.iew.exec_stores 7788477 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 21412394 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 12805909 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4002276 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 355591 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 8720984 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 70347510 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28147990 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1057037 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 78555101 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28690 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 21357228 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 12530635 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 3998139 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 368991 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8665122 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 69169972 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28268339 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1213523 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 79001525 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 20798 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2561252 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 263680 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45676 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2432206 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 253616 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 8400 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 328416 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 7668 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 9528 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 361126 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 20031 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 280189 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 17001194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 3626130 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1643449 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 280189 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 185530 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 524477 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 62170053 # num instructions consuming a value -system.cpu.iew.wb_count 60762788 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.510007 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 319619 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 17031579 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3351229 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1587253 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 319619 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 190941 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 541603 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 56089369 # num instructions consuming a value +system.cpu.iew.wb_count 61177944 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.565288 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 31707186 # num instructions producing a value -system.cpu.iew.wb_rate 0.367534 # insts written-back per cycle -system.cpu.iew.wb_sent 78030912 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 182505983 # number of integer regfile reads -system.cpu.int_regfile_writes 43793404 # number of integer regfile writes -system.cpu.ipc 0.313793 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.313793 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 2393223 3.01% 3.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40692276 51.11% 54.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 71186 0.09% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 15 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 881 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28499876 35.80% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7954659 9.99% 100.00% # Type of FU issued +system.cpu.iew.wb_producers 31706672 # num instructions producing a value +system.cpu.iew.wb_rate 0.372881 # insts written-back per cycle +system.cpu.iew.wb_sent 78478869 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 348371686 # number of integer regfile reads +system.cpu.int_regfile_writes 63138434 # number of integer regfile writes +system.cpu.ipc 0.316215 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.316215 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 2393223 2.98% 2.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 41072292 51.20% 54.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 70482 0.09% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 10 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 884 0.00% 54.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 54.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28695689 35.77% 90.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7982456 9.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 79612138 # Type of FU issued -system.cpu.iq.fp_alu_accesses 8660 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 16534 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6417 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9494 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 4821134 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.060558 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 80215048 # Type of FU issued +system.cpu.iq.fp_alu_accesses 8599 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 16423 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6406 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9332 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 4845478 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.060406 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5360 0.11% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4502804 93.40% 93.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 312970 6.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27460 0.57% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4510772 93.09% 93.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 307245 6.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 82031389 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 260297363 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 60756371 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 88040036 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 66148270 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 79612138 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4032350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 17603379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 124488 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1069462 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 22177627 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 96071614 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.828675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378358 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 82658704 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 260393825 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 61171538 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 85667061 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 64975740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 80215048 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4028141 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 16400358 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 157721 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1065294 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29302343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 94903212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.845230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.416160 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 59906627 62.36% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 16708495 17.39% 79.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7171843 7.47% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4115905 4.28% 91.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5939256 6.18% 97.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1302334 1.36% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 619107 0.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 235470 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 72577 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 59674120 62.88% 62.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15813070 16.66% 79.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6357188 6.70% 86.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4447704 4.69% 90.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6195201 6.53% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1359588 1.43% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 707137 0.75% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 270708 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 78496 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 96071614 # Number of insts issued each cycle -system.cpu.iq.rate 0.481548 # Inst issue rate -system.cpu.itb.accesses 6554572 # DTB accesses +system.cpu.iq.issued_per_cycle::total 94903212 # Number of insts issued each cycle +system.cpu.iq.rate 0.488913 # Inst issue rate +system.cpu.itb.accesses 6464349 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1626 # Number of entries that have been flushed from TLB @@ -493,12 +493,12 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 6547279 # DTB hits -system.cpu.itb.inst_accesses 6554572 # ITB inst accesses -system.cpu.itb.inst_hits 6547279 # ITB inst hits -system.cpu.itb.inst_misses 7293 # ITB inst misses -system.cpu.itb.misses 7293 # DTB misses -system.cpu.itb.perms_faults 5323 # Number of TLB faults due to permissions restrictions +system.cpu.itb.hits 6457219 # DTB hits +system.cpu.itb.inst_accesses 6464349 # ITB inst accesses +system.cpu.itb.inst_hits 6457219 # ITB inst hits +system.cpu.itb.inst_misses 7130 # ITB inst misses +system.cpu.itb.misses 7130 # DTB misses +system.cpu.itb.perms_faults 5291 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits @@ -508,37 +508,38 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.memDep0.conflictingLoads 527 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1505 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 12805909 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8720984 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 84139545 # number of misc regfile reads -system.cpu.misc_regfile_writes 512625 # number of misc regfile writes -system.cpu.numCycles 165325408 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 2897 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8478 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 12530635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8665122 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 83057686 # number of misc regfile reads +system.cpu.misc_regfile_writes 512562 # number of misc regfile writes +system.cpu.numCycles 164068224 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 33120031 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 36654067 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 775523 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 25553608 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2458566 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 439444 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 190069366 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 73481256 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 53179946 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 13052599 # Number of cycles rename is running -system.cpu.rename.SquashCycles 2561252 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 5439754 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 16525878 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 50199 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 190019167 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 16344370 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 812158 # count of serializing insts renamed -system.cpu.rename.skidInsts 14266692 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 663049 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 159865147 # The number of ROB reads -system.cpu.rob.rob_writes 138793846 # The number of ROB writes -system.cpu.timesIdled 1093874 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 33437707 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 51892623 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 80 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 112778 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 25099116 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2516814 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 458049 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 315223829 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 72505198 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 74411101 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 12919645 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2432206 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 4910329 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 22518477 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 65605 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 315158224 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 16104209 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 806801 # count of serializing insts renamed +system.cpu.rename.skidInsts 13643103 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 658966 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 157442889 # The number of ROB reads +system.cpu.rob.rob_writes 136308798 # The number of ROB writes +system.cpu.timesIdled 1088030 # Number of times that the entire CPU went into an idle state and unscheduled itself system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -606,141 +607,141 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 168913 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168913 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52452.525224 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 168958 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168958 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52452.169082 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40011.488822 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 60982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60982 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5661253500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.638974 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107931 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107931 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4318480000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.638974 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40012.241307 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 60963 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60963 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5664572000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.639183 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107995 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107995 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4321122000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.639183 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107931 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 754170 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 103109 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 857279 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52487.372499 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12162755.681818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12215243.054317 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40042.547465 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 107995 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 754554 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 104775 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 859329 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52478.338642 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12451401.162791 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12503879.501433 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40044.278096 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 733778 # number of ReadReq hits -system.l2c.ReadReq_hits::1 103021 # number of ReadReq hits -system.l2c.ReadReq_hits::total 836799 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1070322500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.027039 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000853 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027892 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 20392 # number of ReadReq misses -system.l2c.ReadReq_misses::1 88 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 818309500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027097 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.198198 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.225295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 20436 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 28946013500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1731 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1731 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 430.514488 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 734149 # number of ReadReq hits +system.l2c.ReadReq_hits::1 104689 # number of ReadReq hits +system.l2c.ReadReq_hits::total 838838 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1070820500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027042 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000821 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027863 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 20405 # number of ReadReq misses +system.l2c.ReadReq_misses::1 86 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20491 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 818465000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027088 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.195075 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.222163 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 20439 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 28946123000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1690 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1690 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 404.548175 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.591366 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 40 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.976892 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1691 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1691 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 67641000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.976892 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.988757 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1671 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1671 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 66840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.988757 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1691 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1671 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 748185950 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 432457 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432457 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 432457 # number of Writeback hits -system.l2c.Writeback_hits::total 432457 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 748306939 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 432791 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 432791 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 432791 # number of Writeback hits +system.l2c.Writeback_hits::total 432791 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 8.161920 # Average number of references to valid blocks. +system.l2c.avg_refs 8.132274 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 923083 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 103109 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1026192 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52458.062857 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 76495181.818182 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 76547639.881039 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency -system.l2c.demand_hits::0 794760 # number of demand (read+write) hits -system.l2c.demand_hits::1 103021 # number of demand (read+write) hits -system.l2c.demand_hits::total 897781 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6731576000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.139016 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000853 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.139869 # miss rate for demand accesses -system.l2c.demand_misses::0 128323 # number of demand (read+write) misses -system.l2c.demand_misses::1 88 # number of demand (read+write) misses -system.l2c.demand_misses::total 128411 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 44 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5136789500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.139063 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.244964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.384027 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 128367 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 923512 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 104775 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1028287 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52456.327882 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 78318517.441860 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78370973.769742 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40017.339645 # average overall mshr miss latency +system.l2c.demand_hits::0 795112 # number of demand (read+write) hits +system.l2c.demand_hits::1 104689 # number of demand (read+write) hits +system.l2c.demand_hits::total 899801 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6735392500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.139034 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000821 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.139855 # miss rate for demand accesses +system.l2c.demand_misses::0 128400 # number of demand (read+write) misses +system.l2c.demand_misses::1 86 # number of demand (read+write) misses +system.l2c.demand_misses::total 128486 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5139587000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.139071 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.225808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.364879 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 128434 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 6522.284105 # Average occupied blocks per context -system.l2c.occ_blocks::1 31526.690965 # Average occupied blocks per context -system.l2c.occ_percent::0 0.099522 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.481059 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 923083 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 103109 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1026192 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52458.062857 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 76495181.818182 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 76547639.881039 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency +system.l2c.occ_blocks::0 6549.473309 # Average occupied blocks per context +system.l2c.occ_blocks::1 31510.112837 # Average occupied blocks per context +system.l2c.occ_percent::0 0.099937 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.480806 # Average percentage of cache occupancy +system.l2c.overall_accesses::0 923512 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 104775 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1028287 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52456.327882 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 78318517.441860 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78370973.769742 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40017.339645 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 794760 # number of overall hits -system.l2c.overall_hits::1 103021 # number of overall hits -system.l2c.overall_hits::total 897781 # number of overall hits -system.l2c.overall_miss_latency 6731576000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.139016 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000853 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.139869 # miss rate for overall accesses -system.l2c.overall_misses::0 128323 # number of overall misses -system.l2c.overall_misses::1 88 # number of overall misses -system.l2c.overall_misses::total 128411 # number of overall misses -system.l2c.overall_mshr_hits 44 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5136789500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.139063 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.244964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.384027 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 128367 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29694199450 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 795112 # number of overall hits +system.l2c.overall_hits::1 104689 # number of overall hits +system.l2c.overall_hits::total 899801 # number of overall hits +system.l2c.overall_miss_latency 6735392500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.139034 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000821 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.139855 # miss rate for overall accesses +system.l2c.overall_misses::0 128400 # number of overall misses +system.l2c.overall_misses::1 86 # number of overall misses +system.l2c.overall_misses::total 128486 # number of overall misses +system.l2c.overall_mshr_hits 52 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5139587000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.139071 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.225808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.364879 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 128434 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29694429939 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94647 # number of replacements -system.l2c.sampled_refs 126884 # Sample count of references to valid blocks. +system.l2c.replacements 94693 # number of replacements +system.l2c.sampled_refs 126949 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 38048.975070 # Cycle average of tags in use -system.l2c.total_refs 1035617 # Total number of references to valid blocks. +system.l2c.tagsinuse 38059.586146 # Cycle average of tags in use +system.l2c.total_refs 1032384 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87762 # number of writebacks +system.l2c.writebacks 87781 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 7af784c72..127859fda 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:14:26 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 15:10:15 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 44794736000 because target called exit() +Exiting @ tick 38285728000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 24af2a2eb..49f882c53 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 115565 # Simulator instruction rate (inst/s) -host_mem_usage 395544 # Number of bytes of host memory used -host_seconds 789.60 # Real time elapsed on the host -host_tick_rate 56730912 # Simulator tick rate (ticks/s) +host_inst_rate 204577 # Simulator instruction rate (inst/s) +host_mem_usage 394692 # Number of bytes of host memory used +host_seconds 446.04 # Real time elapsed on the host +host_tick_rate 85834347 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91249905 # Number of instructions simulated -sim_seconds 0.044795 # Number of seconds simulated -sim_ticks 44794736000 # Number of ticks simulated +sim_seconds 0.038286 # Number of seconds simulated +sim_ticks 38285728000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 24857865 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 26546272 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 12880 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1596208 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted +system.cpu.BPredUnit.BTBHits 23530821 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 24877982 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 12905 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1726717 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 22205827 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 27600817 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 100979 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 1707487 # The number of times a branch was mispredicted system.cpu.commit.branches 18722470 # Number of branches committed -system.cpu.commit.bw_lim_events 671558 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3914130 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 84101876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.085142 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27309497 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 72214525 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.263769 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025482 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36127600 50.03% 50.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18090116 25.05% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6155866 8.52% 83.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4484410 6.21% 89.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2045917 2.83% 92.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 550531 0.76% 93.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 763612 1.06% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 82343 0.11% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3914130 5.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 84101876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 72214525 # Number of insts commited each cycle system.cpu.commit.count 91262514 # Number of instructions committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. @@ -50,93 +50,93 @@ system.cpu.commit.refs 27322629 # Nu system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 91249905 # Number of Instructions Simulated system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated -system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.981803 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6763 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 6756 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001035 # miss rate for LoadLockedReq accesses +system.cpu.cpi 0.839140 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.839140 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6778 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 6771 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001033 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 24496209 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5358.863391 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2291.343120 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23475471 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5469995500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.041669 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1020738 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 105235 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2097731500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037373 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 915503 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 25525235 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5595.134205 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2527.282218 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 24493235 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5774178500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.040431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1032000 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 119171 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2306976500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 912829 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26966.230972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29153.525857 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4581642 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4134974891 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.032384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 153339 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 118609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1012501953 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007335 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 34730 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.334667 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 27661.201792 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30532.344047 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4581531 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4244611415 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032408 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 153450 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 118821 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1057304542 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007313 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 34629 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2864.324268 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 29.539803 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 7497 # number of cycles access was blocked +system.cpu.dcache.avg_refs 30.700427 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 8126 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 21653845 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 23275499 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29231190 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 8180.869220 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency -system.cpu.dcache.demand_hits 28057113 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9604970391 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.040165 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1174077 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 223844 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3110233453 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.032508 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 30260216 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 8451.465616 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3550.849792 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29074766 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10018789915 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.039175 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1185450 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 237992 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3364281042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031310 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 947458 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.852828 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 3486.280912 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.851143 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 30260216 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 8451.465616 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3550.849792 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 28057113 # number of overall hits -system.cpu.dcache.overall_miss_latency 9604970391 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.040165 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1174077 # number of overall misses -system.cpu.dcache.overall_mshr_hits 223844 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3110233453 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.032508 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29074766 # number of overall hits +system.cpu.dcache.overall_miss_latency 10018789915 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.039175 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1185450 # number of overall misses +system.cpu.dcache.overall_mshr_hits 237992 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3364281042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031310 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 947458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 946136 # number of replacements -system.cpu.dcache.sampled_refs 950232 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 943361 # number of replacements +system.cpu.dcache.sampled_refs 947457 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3493.184851 # Cycle average of tags in use -system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 943153 # number of writebacks -system.cpu.decode.BlockedCycles 17588781 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 9537 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 4762375 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 139874563 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 32956661 # Number of cycles decode is idle -system.cpu.decode.RunCycles 32742845 # Number of cycles decode is running -system.cpu.decode.SquashCycles 5457924 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 30438 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 813588 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 3486.280912 # Cycle average of tags in use +system.cpu.dcache.total_refs 29087334 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 16275855000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 942852 # number of writebacks +system.cpu.decode.BlockedCycles 10213263 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 32161 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4330029 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 129908076 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 30506430 # Number of cycles decode is idle +system.cpu.decode.RunCycles 31240805 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4327396 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 33218 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 254026 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 29586235 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 15336543 # Number of cache lines fetched -system.cpu.fetch.Cycles 34444061 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 252596 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 142085293 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1618878 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.330242 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 15336543 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 24920897 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.585960 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 89559799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.598579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.586276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 27600817 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 14528959 # Number of cache lines fetched +system.cpu.fetch.Cycles 32560436 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 362446 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 132910862 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1860393 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.360458 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 14528959 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 23631800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.735776 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 76541920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.751769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.650338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 55181021 61.61% 61.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6379280 7.12% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6413392 7.16% 75.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4415439 4.93% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3489859 3.90% 84.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1871095 2.09% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1928131 2.15% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3220363 3.60% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6661219 7.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 44039302 57.54% 57.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6026139 7.87% 65.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6234278 8.14% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4503549 5.88% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3291793 4.30% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1400372 1.83% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1662749 2.17% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3136974 4.10% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6246764 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 89559799 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 96 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 15336543 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35886.138614 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34397.626113 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 15335735 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 28996000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 134 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23184000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 674 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 76541920 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 46 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 14528959 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36006.674757 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34472.834068 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 14528135 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29669500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 824 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 23476000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 681 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 22787.124814 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21364.904412 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 15336543 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35886.138614 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency -system.cpu.icache.demand_hits 15335735 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 28996000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_misses 808 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 134 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23184000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 674 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 14528959 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36006.674757 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34472.834068 # average overall mshr miss latency +system.cpu.icache.demand_hits 14528135 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 29669500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses +system.cpu.icache.demand_misses 824 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 23476000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 681 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.277518 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 570.381562 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.278507 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 14528959 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36006.674757 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34472.834068 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 15335735 # number of overall hits -system.cpu.icache.overall_miss_latency 28996000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_misses 808 # number of overall misses -system.cpu.icache.overall_mshr_hits 134 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23184000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 674 # number of overall MSHR misses +system.cpu.icache.overall_hits 14528135 # number of overall hits +system.cpu.icache.overall_miss_latency 29669500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses +system.cpu.icache.overall_misses 824 # number of overall misses +system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 23476000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 681 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 680 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 568.356083 # Cycle average of tags in use -system.cpu.icache.total_refs 15335735 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 570.381562 # Cycle average of tags in use +system.cpu.icache.total_refs 14528135 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 20951910 # Number of branches executed -system.cpu.iew.exec_nop 39919 # number of nop insts executed -system.cpu.iew.exec_rate 1.157669 # Inst execution rate -system.cpu.iew.exec_refs 30258239 # number of memory reference insts executed -system.cpu.iew.exec_stores 5196792 # Number of stores executed +system.cpu.idleCycles 29537 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1811010 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 21021161 # Number of branches executed +system.cpu.iew.exec_nop 38671 # number of nop insts executed +system.cpu.iew.exec_rate 1.370820 # Inst execution rate +system.cpu.iew.exec_refs 31258880 # number of memory reference insts executed +system.cpu.iew.exec_stores 5296884 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 358280 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6614347 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 129035403 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25061447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2046229 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 103714956 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 173808 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 92844 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29388831 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 647702 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 633555 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6085547 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 118572043 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 25961996 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2334217 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 104965675 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 21340 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 187 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5457924 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 196064 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 243 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4327396 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 27063 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 398676 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 30520 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 260518 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 7496 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 14224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 117715 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 8920401 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1867594 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 127150055 # num instructions consuming a value -system.cpu.iew.wb_count 102173263 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.489247 # average fanout of values written-back +system.cpu.iew.lsq.thread0.squashedLoads 6812954 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1338794 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117715 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 241876 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1569134 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 95054189 # num instructions consuming a value +system.cpu.iew.wb_count 102978657 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.626333 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 62207806 # num instructions producing a value -system.cpu.iew.wb_rate 1.140461 # insts written-back per cycle -system.cpu.iew.wb_sent 102563540 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 259728905 # number of integer regfile reads -system.cpu.int_regfile_writes 80595212 # number of integer regfile writes -system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 59535555 # num instructions producing a value +system.cpu.iew.wb_rate 1.344870 # insts written-back per cycle +system.cpu.iew.wb_sent 103397813 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 499543161 # number of integer regfile reads +system.cpu.int_regfile_writes 121465311 # number of integer regfile writes +system.cpu.ipc 1.191696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.191696 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75293930 70.17% 70.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10513 0.01% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 12 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26527925 24.72% 94.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5467485 5.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105761185 # Type of FU issued -system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 177153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 107299892 # Type of FU issued +system.cpu.iq.fp_alu_accesses 69 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 134 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 92 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 522807 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004872 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 178340 34.11% 34.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83834 16.04% 50.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 260606 49.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 166475031 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 128301553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 105761185 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 693931 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 37472339 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 89559799 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.180900 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 107822630 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 291690830 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 102978596 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 143196091 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 117880817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 107299892 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 652555 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 24550577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 26453 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 98149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 62032164 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 76541920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.401845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.609057 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30986860 40.48% 40.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 16938663 22.13% 62.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11541566 15.08% 77.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7661333 10.01% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5199199 6.79% 94.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2314331 3.02% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1500377 1.96% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273343 0.36% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126248 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 89559799 # Number of insts issued each cycle -system.cpu.iq.rate 1.180509 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 76541920 # Number of insts issued each cycle +system.cpu.iq.rate 1.401304 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,27 +416,27 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 34765 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34227.938648 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.585872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 20226 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 497640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.418208 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 34664 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.196506 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.712222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 20125 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 499228500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.419426 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451270000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418208 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451519000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419426 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 916140 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34309.334657 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.709419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 915133 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 34549500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001099 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1007 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 31042500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 913473 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34317.365269 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.911290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 912471 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34386000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001097 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1002 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 992 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses @@ -444,86 +444,87 @@ system.cpu.l2cache.UpgradeReq_misses 1 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 943153 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 943153 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 942852 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 942852 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 104.893699 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 104.767129 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 950905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34233.211115 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 935359 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 532189500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.016349 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 482312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.016339 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 15537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 948137 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34335.917895 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.429528 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 932596 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 533614500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.016391 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 15541 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 482384000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.016381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 15531 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.250026 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 401.000485 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8133.618465 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.248218 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 948137 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34335.917895 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.429528 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 935359 # number of overall hits -system.cpu.l2cache.overall_miss_latency 532189500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.016349 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 15546 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 482312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.016339 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 15537 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 932596 # number of overall hits +system.cpu.l2cache.overall_miss_latency 533614500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.016391 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 15541 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 482384000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.016381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 15531 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 702 # number of replacements -system.cpu.l2cache.sampled_refs 15522 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 703 # number of replacements +system.cpu.l2cache.sampled_refs 15515 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8598.547498 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1628160 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8534.618949 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1625462 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.memDep0.conflictingLoads 672298 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 377389 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 31496278 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6614347 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 197340644 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 929079 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 406185 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 29388831 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6085547 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 186806187 # number of misc regfile reads system.cpu.misc_regfile_writes 11602 # number of misc regfile writes -system.cpu.numCycles 89589473 # number of cpu cycles simulated +system.cpu.numCycles 76571457 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2558009 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 71576967 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 2891853 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 350271208 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 105865305 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running -system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 34288335 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 350270421 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed -system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 702184 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 212458407 # The number of ROB reads -system.cpu.rob.rob_writes 263525841 # The number of ROB writes -system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 527053 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 52081 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 31875440 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 790758 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 546541782 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 125415140 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 146085442 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 30085876 # Number of cycles rename is running +system.cpu.rename.SquashCycles 4327396 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1561693 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 38655966 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 561 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 546541221 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 8164462 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 673678 # count of serializing insts renamed +system.cpu.rename.skidInsts 5091742 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 677127 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 186866672 # The number of ROB reads +system.cpu.rob.rob_writes 241479537 # The number of ROB writes +system.cpu.timesIdled 1545 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 857cf86ba..6dfbf09ec 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3623403 # Simulator instruction rate (inst/s) -host_mem_usage 338784 # Number of bytes of host memory used -host_seconds 25.18 # Real time elapsed on the host -host_tick_rate 2153732946 # Simulator tick rate (ticks/s) +host_inst_rate 1991743 # Simulator instruction rate (inst/s) +host_mem_usage 385676 # Number of bytes of host memory used +host_seconds 45.82 # Real time elapsed on the host +host_tick_rate 1183885034 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91252969 # Number of instructions simulated sim_seconds 0.054241 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 91252969 # Number of instructions executed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_int_insts 72525682 # number of integer instructions -system.cpu.num_int_register_reads 234656737 # number of times the integer registers were read -system.cpu.num_int_register_writes 70993656 # number of times the integer registers were written +system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read +system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 6b71bf251..9c2d92308 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2007081 # Simulator instruction rate (inst/s) -host_mem_usage 346528 # Number of bytes of host memory used -host_seconds 45.45 # Real time elapsed on the host -host_tick_rate 3258049978 # Simulator tick rate (ticks/s) +host_inst_rate 1371366 # Simulator instruction rate (inst/s) +host_mem_usage 393424 # Number of bytes of host memory used +host_seconds 66.52 # Real time elapsed on the host +host_tick_rate 2226109550 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91226321 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -259,8 +259,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 91226321 # Number of instructions executed system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_int_insts 72525682 # number of integer instructions -system.cpu.num_int_register_reads 257193253 # number of times the integer registers were read -system.cpu.num_int_register_writes 70993656 # number of times the integer registers were written +system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read +system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index b82973c4c..fa8986d95 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:20:25 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 14:22:00 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -71,4 +73,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 332731219000 because target called exit() +Exiting @ tick 321578293500 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index c029212bb..8213121ce 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 95018 # Simulator instruction rate (inst/s) -host_mem_usage 268868 # Number of bytes of host memory used -host_seconds 6034.01 # Real time elapsed on the host -host_tick_rate 55142639 # Simulator tick rate (ticks/s) +host_inst_rate 152812 # Simulator instruction rate (inst/s) +host_mem_usage 267644 # Number of bytes of host memory used +host_seconds 3751.94 # Real time elapsed on the host +host_tick_rate 85709842 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 573342397 # Number of instructions simulated -sim_seconds 0.332731 # Number of seconds simulated -sim_ticks 332731219000 # Number of ticks simulated +sim_insts 573342347 # Number of instructions simulated +sim_seconds 0.321578 # Number of seconds simulated +sim_ticks 321578293500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 157170154 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 189971474 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 2546633 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 18809964 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 186338321 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 233659814 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 11860569 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 20926821 # The number of times a branch was mispredicted -system.cpu.commit.branches 120192362 # Number of branches committed -system.cpu.commit.bw_lim_events 6858146 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 148133449 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 184155292 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 2540432 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 19178163 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 179128665 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 224215048 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 11903329 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 21282283 # The number of times a branch was mispredicted +system.cpu.commit.branches 120192352 # Number of branches committed +system.cpu.commit.bw_lim_events 10124607 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 574686281 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3877893 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 381923221 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 603587786 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.952117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574686231 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 3877883 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 335224652 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 586025394 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.980651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.590909 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 312132657 53.26% 53.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 152008237 25.94% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 54725010 9.34% 88.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 24718239 4.22% 92.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 15770136 2.69% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6564583 1.12% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7700533 1.31% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2281392 0.39% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10124607 1.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 603587786 # Number of insts commited each cycle -system.cpu.commit.count 574686281 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 586025394 # Number of insts commited each cycle +system.cpu.commit.count 574686231 # Number of instructions committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.int_insts 473702185 # Number of committed integer instructions. -system.cpu.commit.loads 126773177 # Number of loads committed +system.cpu.commit.int_insts 473702145 # Number of committed integer instructions. +system.cpu.commit.loads 126773167 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.refs 184377275 # Number of memory references committed +system.cpu.commit.refs 184377255 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 573342397 # Number of Instructions Simulated -system.cpu.committedInsts_total 573342397 # Number of Instructions Simulated -system.cpu.cpi 1.160672 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.160672 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 2604457 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 7857.142857 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 2604422 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 275000 # number of LoadLockedReq miss cycles +system.cpu.committedInsts 573342347 # Number of Instructions Simulated +system.cpu.committedInsts_total 573342347 # Number of Instructions Simulated +system.cpu.cpi 1.121767 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.121767 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 2604413 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 8882.352941 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 2604379 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000013 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 35 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 143454074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10689.937494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7026.878867 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 142382969 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11450045500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007467 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1071105 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 217572 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5997673000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005950 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 853533 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 2232162 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 2232162 # number of StoreCondReq hits +system.cpu.dcache.LoadLockedReq_misses 34 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 34 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 143465196 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10833.810170 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7175.241150 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 142365589 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11912933500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1099607 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 241635 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 6156156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 857972 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 2232152 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 2232152 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15503.883790 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12993.978894 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 52863588 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21328972000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.025364 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1375718 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1033256 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 4449944000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006314 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 342462 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 15161.234737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12563.932747 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 52868553 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20782308000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.025272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1370753 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1034947 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 4219044000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006191 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 335806 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 167.338700 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 167.641865 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 197693380 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13396.562604 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency -system.cpu.dcache.demand_hits 195246557 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 32779017500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012377 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2446823 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1250828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10447617000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006050 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1195995 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 197704502 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13235.010889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8691.063162 # average overall mshr miss latency +system.cpu.dcache.demand_hits 195234142 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 32695241500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.012495 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2470360 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1276582 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10375200000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006038 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1193778 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4061.060335 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.991470 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 197693380 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13396.562604 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4060.874839 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.991425 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 197704502 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13235.010889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8691.063162 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 195246557 # number of overall hits -system.cpu.dcache.overall_miss_latency 32779017500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012377 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2446823 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1250828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10447617000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006050 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1195995 # number of overall MSHR misses +system.cpu.dcache.overall_hits 195234142 # number of overall hits +system.cpu.dcache.overall_miss_latency 32695241500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.012495 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2470360 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1276582 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10375200000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006038 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1193778 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1191585 # number of replacements -system.cpu.dcache.sampled_refs 1195681 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1189349 # number of replacements +system.cpu.dcache.sampled_refs 1193445 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4061.060335 # Cycle average of tags in use -system.cpu.dcache.total_refs 200083704 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6358781000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1064793 # number of writebacks -system.cpu.decode.BlockedCycles 85842380 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 76871 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 34367828 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 1126968144 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 277630014 # Number of cycles decode is idle -system.cpu.decode.RunCycles 236143765 # Number of cycles decode is running -system.cpu.decode.SquashCycles 57332647 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 218235 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 3971626 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4060.874839 # Cycle average of tags in use +system.cpu.dcache.total_refs 200071346 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6159353000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1065214 # number of writebacks +system.cpu.decode.BlockedCycles 81401294 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 76616 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 32098392 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1089624407 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 274509377 # Number of cycles decode is idle +system.cpu.decode.RunCycles 227139147 # Number of cycles decode is running +system.cpu.decode.SquashCycles 53022157 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 216379 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2975575 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 233659814 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 132169265 # Number of cache lines fetched -system.cpu.fetch.Cycles 250543993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4563312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1003583241 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 3753 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 21196803 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.351124 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 132169265 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 169030723 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.508099 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 660920432 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.774764 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.719580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 224215048 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 130463264 # Number of cache lines fetched +system.cpu.fetch.Cycles 241171413 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4019936 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 971569879 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3446 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 21817115 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.348617 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 130463264 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 160036778 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.510627 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 639047550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.784644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.739665 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 410388026 62.09% 62.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20297992 3.07% 65.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37708836 5.71% 70.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39874346 6.03% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40511205 6.13% 83.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16776062 2.54% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18545890 2.81% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 14106044 2.13% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 62712031 9.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 397887895 62.26% 62.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20346317 3.18% 65.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35545553 5.56% 71.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 35836074 5.61% 76.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 37423623 5.86% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17678726 2.77% 85.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18470353 2.89% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14255263 2.23% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61603746 9.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 660920432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 639047550 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 132169265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14331.781024 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10612.450522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 132154341 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 213887500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 14924 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1029 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 147460000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 13895 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 130463264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14395.336442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10664.161477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 130448254 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 216074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000115 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 15010 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1039 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 148989000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000107 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 13971 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 9748.051560 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 9587.553212 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 132169265 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14331.781024 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency -system.cpu.icache.demand_hits 132154341 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 213887500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses -system.cpu.icache.demand_misses 14924 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1029 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147460000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 13895 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 130463264 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14395.336442 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10664.161477 # average overall mshr miss latency +system.cpu.icache.demand_hits 130448254 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 216074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000115 # miss rate for demand accesses +system.cpu.icache.demand_misses 15010 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1039 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 148989000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000107 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 13971 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1053.520934 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.514415 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 132169265 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14331.781024 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1050.734375 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.513054 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 130463264 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14395.336442 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10664.161477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 132154341 # number of overall hits -system.cpu.icache.overall_miss_latency 213887500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses -system.cpu.icache.overall_misses 14924 # number of overall misses -system.cpu.icache.overall_mshr_hits 1029 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147460000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 13895 # number of overall MSHR misses +system.cpu.icache.overall_hits 130448254 # number of overall hits +system.cpu.icache.overall_miss_latency 216074000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000115 # miss rate for overall accesses +system.cpu.icache.overall_misses 15010 # number of overall misses +system.cpu.icache.overall_mshr_hits 1039 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 148989000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000107 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 13971 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 11791 # number of replacements -system.cpu.icache.sampled_refs 13557 # Sample count of references to valid blocks. +system.cpu.icache.replacements 11828 # number of replacements +system.cpu.icache.sampled_refs 13606 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1053.520934 # Cycle average of tags in use -system.cpu.icache.total_refs 132154335 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1050.734375 # Cycle average of tags in use +system.cpu.icache.total_refs 130448249 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 4 # number of writebacks -system.cpu.idleCycles 4542007 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 25100140 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 142399885 # Number of branches executed -system.cpu.iew.exec_nop 9420990 # number of nop insts executed -system.cpu.iew.exec_rate 1.051214 # Inst execution rate -system.cpu.iew.exec_refs 220838036 # number of memory reference insts executed -system.cpu.iew.exec_stores 66554903 # Number of stores executed +system.cpu.idleCycles 4109038 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 24488226 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 144045420 # Number of branches executed +system.cpu.iew.exec_nop 9196797 # number of nop insts executed +system.cpu.iew.exec_rate 1.104746 # Inst execution rate +system.cpu.iew.exec_refs 221540830 # number of memory reference insts executed +system.cpu.iew.exec_stores 67586566 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 2947924 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 196892006 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2816035 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 18822753 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 114373867 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 956606524 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 154283133 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 25300490 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 699543688 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 130928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 2832645 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 191530512 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2788377 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 21562901 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 112754072 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 909908771 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 153954264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29546426 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 710524922 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 84675 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 7156 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 57332647 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 209223 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9984 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 53022157 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 156338 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 5626597 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 13730 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5449723 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 9231 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 241250 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 24511 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 70118828 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 56769769 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 782273717 # num instructions consuming a value -system.cpu.iew.wb_count 680637923 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.486169 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 514201 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 24892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 64757344 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 55149984 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 514201 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 6539139 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 17949087 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 689691426 # num instructions consuming a value +system.cpu.iew.wb_count 693409732 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.562543 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 380317186 # num instructions producing a value -system.cpu.iew.wb_rate 1.022804 # insts written-back per cycle -system.cpu.iew.wb_sent 691183006 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 1609052037 # number of integer regfile reads -system.cpu.int_regfile_writes 524399004 # number of integer regfile writes -system.cpu.ipc 0.861570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.861570 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 387981236 # num instructions producing a value +system.cpu.iew.wb_rate 1.078135 # insts written-back per cycle +system.cpu.iew.wb_sent 702871979 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 3281708105 # number of integer regfile reads +system.cpu.int_regfile_writes 806654983 # number of integer regfile writes +system.cpu.ipc 0.891451 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.891451 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 503382481 68.02% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 366130 0.05% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 100 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163172266 22.05% 90.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 73150368 9.88% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 724844178 # Type of FU issued -system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 740071348 # Type of FU issued +system.cpu.iq.fp_alu_accesses 120 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 236 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 8619148 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst) +system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 9396552 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012697 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 121750 1.30% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5531349 58.87% 60.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3743453 39.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 733463200 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 2121563604 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 680637907 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 1319150008 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 942508573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 724844178 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4676961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 371760121 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 2335916 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 799068 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 680735331 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 660920432 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.096719 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 749467780 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2132627874 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 693409716 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1224006325 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 896062746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 740071348 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4649228 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 322821915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 4041312 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 771345 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 897570862 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 639047550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.158085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.444316 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 296540027 46.40% 46.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135125235 21.14% 67.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 102276930 16.00% 83.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53053702 8.30% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32312745 5.06% 96.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10946068 1.71% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5715024 0.89% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1662869 0.26% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1414950 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 660920432 # Number of insts issued each cycle -system.cpu.iq.rate 1.089234 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 639047550 # Number of insts issued each cycle +system.cpu.iq.rate 1.150686 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -415,117 +415,118 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 342473 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34244.416047 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.822429 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 231351 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3805308000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.324469 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 111122 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3445429000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.324469 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 111122 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 866749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34192.097787 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.522397 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 741784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 4272815500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.144177 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 124965 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 3876795000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144161 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 124951 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 298 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4635.416667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31057.291667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 202 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 445000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.322148 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 96 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2981500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.322148 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 96 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1064797 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1064797 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 335811 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.016328 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31006.007098 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 231268 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3580704000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.311315 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 104543 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3241461000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 104543 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 871234 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34198.783276 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31027.526740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 742199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4412840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.148106 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 129035 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 4003171500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 129020 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 323 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4157.258065 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 199 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 515500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.383901 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 124 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.383901 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 124 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1065218 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1065218 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 6.452091 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.556248 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1209222 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34216.723072 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 973135 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8078123500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.195239 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 236087 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7322224000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.195227 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 236073 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 1207045 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34222.161334 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.894530 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 973467 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 7993544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.193512 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 233578 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7244632500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.193500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 233563 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 7099.133966 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13800.334539 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.216648 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421153 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 1209222 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34216.723072 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 7806.839670 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13448.206347 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.238246 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.410407 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 1207045 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34222.161334 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.894530 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 973135 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8078123500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.195239 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 236087 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7322224000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.195227 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 236073 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 973467 # number of overall hits +system.cpu.l2cache.overall_miss_latency 7993544000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.193512 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 233578 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7244632500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.193500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 233563 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 217008 # number of replacements -system.cpu.l2cache.sampled_refs 237229 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 214457 # number of replacements +system.cpu.l2cache.sampled_refs 234692 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 20899.468505 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1530623 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 239794586000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 171527 # number of writebacks -system.cpu.memDep0.conflictingLoads 54793834 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61680450 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 196892006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 114373867 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1238278234 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464326 # number of misc regfile writes -system.cpu.numCycles 665462439 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21255.046017 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1538699 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 231483982000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 169715 # number of writebacks +system.cpu.memDep0.conflictingLoads 55352891 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 57957539 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 191530512 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 112754072 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1207319291 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464306 # number of misc regfile writes +system.cpu.numCycles 643156588 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 11783884 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 448493735 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 9081964 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 293899856 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 2673538381 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 1068521543 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 798521865 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 223635059 # Number of cycles rename is running -system.cpu.rename.SquashCycles 57332647 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 24492193 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 350028127 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 1141 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 2673537240 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 2837350 # count of serializing insts renamed -system.cpu.rename.skidInsts 62579735 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 2837280 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1553332004 # The number of ROB reads -system.cpu.rob.rob_writes 1970603439 # The number of ROB writes -system.cpu.timesIdled 108463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 10882615 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 672201192 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 6788504 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 289521526 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 10125485 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 314 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 4573163834 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1035060764 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1156158819 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 214798032 # Number of cycles rename is running +system.cpu.rename.SquashCycles 53022157 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 21471386 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 483957622 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1478 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 4573162356 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 49351834 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2811446 # count of serializing insts renamed +system.cpu.rename.skidInsts 56327662 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2811371 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1485804532 # The number of ROB reads +system.cpu.rob.rob_writes 1872966430 # The number of ROB writes +system.cpu.timesIdled 97371 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 548 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt index 0d8c76b6a..6d10538b7 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4059400 # Simulator instruction rate (inst/s) -host_mem_usage 209588 # Number of bytes of host memory used -host_seconds 140.65 # Real time elapsed on the host -host_tick_rate 2065351773 # Simulator tick rate (ticks/s) +host_inst_rate 3887693 # Simulator instruction rate (inst/s) +host_mem_usage 256484 # Number of bytes of host memory used +host_seconds 146.87 # Real time elapsed on the host +host_tick_rate 1977989899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 570968176 # Number of instructions simulated sim_seconds 0.290499 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 570968176 # Number of instructions executed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_int_insts 470727703 # number of integer instructions -system.cpu.num_int_register_reads 1385336079 # number of times the integer registers were read -system.cpu.num_int_register_writes 425113002 # number of times the integer registers were written +system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 218238666..9f67dc057 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2210994 # Simulator instruction rate (inst/s) -host_mem_usage 217324 # Number of bytes of host memory used -host_seconds 257.37 # Real time elapsed on the host -host_tick_rate 2806251427 # Simulator tick rate (ticks/s) +host_inst_rate 1138464 # Simulator instruction rate (inst/s) +host_mem_usage 264236 # Number of bytes of host memory used +host_seconds 499.83 # Real time elapsed on the host +host_tick_rate 1444968716 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 569034848 # Number of instructions simulated sim_seconds 0.722234 # Number of seconds simulated @@ -259,8 +259,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 569034848 # Number of instructions executed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_int_insts 470727703 # number of integer instructions -system.cpu.num_int_register_reads 1511252780 # number of times the integer registers were read -system.cpu.num_int_register_writes 425113002 # number of times the integer registers were written +system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written system.cpu.num_load_insts 126029556 # Number of load instructions system.cpu.num_mem_refs 182890035 # number of memory refs system.cpu.num_store_insts 56860479 # Number of store instructions diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 41f4f6ce7..c56e8acb0 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:25:17 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 14:39:34 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,5 +18,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.150000 -Exiting @ tick 151737379000 because target called exit() +OO-style eon Time= 0.110000 +Exiting @ tick 117809491500 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 76b5527a0..520b82c48 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153284 # Simulator instruction rate (inst/s) -host_mem_usage 226404 # Number of bytes of host memory used -host_seconds 2277.25 # Real time elapsed on the host -host_tick_rate 66631737 # Simulator tick rate (ticks/s) +host_inst_rate 211489 # Simulator instruction rate (inst/s) +host_mem_usage 270680 # Number of bytes of host memory used +host_seconds 1650.52 # Real time elapsed on the host +host_tick_rate 71377158 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 349065985 # Number of instructions simulated -sim_seconds 0.151737 # Number of seconds simulated -sim_ticks 151737379000 # Number of ticks simulated +sim_insts 349066263 # Number of instructions simulated +sim_seconds 0.117809 # Number of seconds simulated +sim_ticks 117809491500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 20189650 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 26438081 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 72569 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3421912 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 20033400 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 36581771 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 7288333 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3392850 # The number of times a branch was mispredicted -system.cpu.commit.branches 30521887 # Number of branches committed -system.cpu.commit.bw_lim_events 7594485 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 21062889 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 27322695 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 72292 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3475103 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 20805254 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 37744082 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 7419277 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 3443737 # The number of times a branch was mispredicted +system.cpu.commit.branches 30521923 # Number of branches committed +system.cpu.commit.bw_lim_events 10435258 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 349066597 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3555476 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 29812251 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 297396946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.173740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 349066875 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 3555485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 39704049 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 228514950 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.527545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.133009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102801955 44.99% 44.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 53028094 23.21% 68.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21141032 9.25% 77.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16471755 7.21% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11485651 5.03% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6931925 3.03% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3277801 1.43% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2941479 1.29% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10435258 4.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 297396946 # Number of insts commited each cycle -system.cpu.commit.count 349066597 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 228514950 # Number of insts commited each cycle +system.cpu.commit.count 349066875 # Number of instructions committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.int_insts 287529375 # Number of committed integer instructions. -system.cpu.commit.loads 94648997 # Number of loads committed +system.cpu.commit.function_calls 6225114 # Number of function calls committed. +system.cpu.commit.int_insts 279586113 # Number of committed integer instructions. +system.cpu.commit.loads 94649044 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.refs 177024839 # Number of memory references committed +system.cpu.commit.refs 177024913 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 349065985 # Number of Instructions Simulated -system.cpu.committedInsts_total 349065985 # Number of Instructions Simulated -system.cpu.cpi 0.869391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869391 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 11420 # number of LoadLockedReq accesses(hits+misses) +system.cpu.committedInsts 349066263 # Number of Instructions Simulated +system.cpu.committedInsts_total 349066263 # Number of Instructions Simulated +system.cpu.cpi 0.674998 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.674998 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11411 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 11418 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits 11409 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 95511418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33945.089582 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30823.853743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95508404 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 102310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 3014 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 53109500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 96380397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33471.948212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30902.675014 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96377153 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 108583000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 3244 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1487 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 54296000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 1757 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses 11147 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 11147 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 82052672 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32101.461896 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.632135 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 82033724 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 608258500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32597.187038 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.657728 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 82033751 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 617651500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 18948 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 16110 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 100572000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits 16114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 100478500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2838 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2834 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 38956.714348 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38865.924635 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 177564090 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32354.475913 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency -system.cpu.dcache.demand_hits 177542128 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 710569000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 178433096 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32725.058580 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33712.589850 # average overall mshr miss latency +system.cpu.dcache.demand_hits 178410904 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 726234500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses -system.cpu.dcache.demand_misses 21962 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 17401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 153681500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 22192 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 17601 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 154774500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4561 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4591 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 3085.152893 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.753211 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 177564090 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32354.475913 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 3098.465756 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.756461 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 178433096 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32725.058580 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33712.589850 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 177542128 # number of overall hits -system.cpu.dcache.overall_miss_latency 710569000 # number of overall miss cycles +system.cpu.dcache.overall_hits 178410904 # number of overall hits +system.cpu.dcache.overall_miss_latency 726234500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses -system.cpu.dcache.overall_misses 21962 # number of overall misses -system.cpu.dcache.overall_mshr_hits 17401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 153681500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 22192 # number of overall misses +system.cpu.dcache.overall_mshr_hits 17601 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 154774500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4561 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4591 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400 # number of replacements -system.cpu.dcache.sampled_refs 4558 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1403 # number of replacements +system.cpu.dcache.sampled_refs 4591 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3085.152893 # Cycle average of tags in use -system.cpu.dcache.total_refs 177564704 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3098.465756 # Cycle average of tags in use +system.cpu.dcache.total_refs 178433460 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1021 # number of writebacks -system.cpu.decode.BlockedCycles 139649394 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 71446 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 7239931 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 408881420 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 85142692 # Number of cycles decode is idle -system.cpu.decode.RunCycles 69995506 # Number of cycles decode is running -system.cpu.decode.SquashCycles 5956648 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 202337 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 2609353 # Number of cycles decode is unblocking +system.cpu.dcache.writebacks 1024 # number of writebacks +system.cpu.decode.BlockedCycles 69331294 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 73618 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 7489475 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 420268511 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 84393046 # Number of cycles decode is idle +system.cpu.decode.RunCycles 73199019 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6976526 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 216081 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1591590 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 36581771 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 38750811 # Number of cache lines fetched -system.cpu.fetch.Cycles 74679621 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 443401 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 319036670 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3525453 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.120543 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 38750811 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 27477983 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.051279 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 303353593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.373711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 37744082 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 40002335 # Number of cache lines fetched +system.cpu.fetch.Cycles 76861965 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 627285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 328341754 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3612258 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.160191 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 40002335 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 28482166 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.393528 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 235491475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.819242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.041438 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229229916 75.57% 75.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9045346 2.98% 78.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5665347 1.87% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6451006 2.13% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5318728 1.75% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4703234 1.55% 85.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3636973 1.20% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4046277 1.33% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35256766 11.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 159219706 67.61% 67.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9262838 3.93% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5962224 2.53% 74.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6640011 2.82% 76.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5459111 2.32% 79.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4841931 2.06% 81.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3740667 1.59% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4101328 1.74% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36263659 15.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 303353593 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 185399370 # number of floating regfile reads -system.cpu.fp_regfile_writes 131540962 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 38750811 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 11739.616414 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8345.912955 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 38734752 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 188526500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000414 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 16059 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 130588500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000404 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 15647 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 235491475 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 189753142 # number of floating regfile reads +system.cpu.fp_regfile_writes 134299135 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 40002335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 11799.645611 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8377.979424 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 39986251 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 189785500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 16084 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 131107000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 15649 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2476.013296 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2555.195284 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 38750811 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 11739.616414 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency -system.cpu.icache.demand_hits 38734752 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 188526500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000414 # miss rate for demand accesses -system.cpu.icache.demand_misses 16059 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 130588500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000404 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 15647 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 40002335 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 11799.645611 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8377.979424 # average overall mshr miss latency +system.cpu.icache.demand_hits 39986251 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 189785500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses +system.cpu.icache.demand_misses 16084 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 131107000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 15649 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1826.425729 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.891809 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 38750811 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 11739.616414 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1826.046295 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.891624 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 40002335 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 11799.645611 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8377.979424 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 38734752 # number of overall hits -system.cpu.icache.overall_miss_latency 188526500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000414 # miss rate for overall accesses -system.cpu.icache.overall_misses 16059 # number of overall misses -system.cpu.icache.overall_mshr_hits 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 130588500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000404 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 15647 # number of overall MSHR misses +system.cpu.icache.overall_hits 39986251 # number of overall hits +system.cpu.icache.overall_miss_latency 189785500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses +system.cpu.icache.overall_misses 16084 # number of overall misses +system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 131107000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 15649 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 13782 # number of replacements -system.cpu.icache.sampled_refs 15644 # Sample count of references to valid blocks. +system.cpu.icache.replacements 13784 # number of replacements +system.cpu.icache.sampled_refs 15649 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1826.425729 # Cycle average of tags in use -system.cpu.icache.total_refs 38734752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1826.046295 # Cycle average of tags in use +system.cpu.icache.total_refs 39986251 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 121166 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 3575174 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 31598497 # Number of branches executed -system.cpu.iew.exec_nop 47916 # number of nop insts executed -system.cpu.iew.exec_rate 1.198862 # Inst execution rate -system.cpu.iew.exec_refs 183613240 # number of memory reference insts executed -system.cpu.iew.exec_stores 84389722 # Number of stores executed +system.cpu.idleCycles 127509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3670203 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 31934668 # Number of branches executed +system.cpu.iew.exec_nop 47192 # number of nop insts executed +system.cpu.iew.exec_rate 1.564151 # Inst execution rate +system.cpu.iew.exec_refs 185570349 # number of memory reference insts executed +system.cpu.iew.exec_stores 84541959 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 6232 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 104118233 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 3634513 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5773715 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 89143121 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 378881196 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 99223518 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3473693 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 363824242 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 103 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 10926 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 106791761 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 3802356 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6858543 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 90029129 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 388774140 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 101028390 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4246307 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 368543664 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 71 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5956648 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 247 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 337 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6976526 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 499 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 3624729 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 4560961 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 25223 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 165832 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 9469235 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 6767279 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 302337892 # num instructions consuming a value -system.cpu.iew.wb_count 361679600 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.513512 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 199743 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 12142716 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 7653260 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 199743 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 359811 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3310392 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 317090964 # num instructions consuming a value +system.cpu.iew.wb_count 365218926 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.522267 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 155254133 # num instructions producing a value -system.cpu.iew.wb_rate 1.191795 # insts written-back per cycle -system.cpu.iew.wb_sent 362096434 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 845155916 # number of integer regfile reads -system.cpu.int_regfile_writes 184404886 # number of integer regfile writes -system.cpu.ipc 1.150231 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.150231 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 165606023 # num instructions producing a value +system.cpu.iew.wb_rate 1.550040 # insts written-back per cycle +system.cpu.iew.wb_sent 366001659 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1759246608 # number of integer regfile reads +system.cpu.int_regfile_writes 232102222 # number of integer regfile writes +system.cpu.ipc 1.481486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.481486 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126463418 33.92% 33.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147037 0.58% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6836747 1.83% 36.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8624018 2.31% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3527986 0.95% 39.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1580654 0.42% 40.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21035747 5.64% 45.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7283008 1.95% 47.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262175 1.95% 49.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102247784 27.43% 77.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85606108 22.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 367297935 # Type of FU issued -system.cpu.iq.fp_alu_accesses 125160042 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 243629757 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 116471069 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 124289037 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 12277552 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 372789971 # Type of FU issued +system.cpu.iq.fp_alu_accesses 127821933 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 249342196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 118185962 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 133232335 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 13475549 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036148 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2445 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 11285 0.08% 0.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 187 0.00% 0.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 1509 0.01% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 142639 1.06% 1.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 1245 0.01% 1.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.25% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7221179 53.59% 57.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5786651 42.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 254415445 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 807801978 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 245208531 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 282487868 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 375187519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 367297935 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3645761 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 27882412 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1204720 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 90285 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 56560737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 303353593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.210791 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 258443587 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 746613752 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 247032964 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 293633638 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 384913340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 372789971 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3813608 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 38043864 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1408982 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 258123 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 125676657 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 235491475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.583030 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.821450 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 95677321 40.63% 40.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47888075 20.34% 60.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27520727 11.69% 72.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20838545 8.85% 81.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22281426 9.46% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12633898 5.36% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6146913 2.61% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1868425 0.79% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 636145 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 303353593 # Number of insts issued each cycle -system.cpu.iq.rate 1.210308 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 235491475 # Number of insts issued each cycle +system.cpu.iq.rate 1.582173 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,114 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 2835 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.690451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31254.703585 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 96949000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.993651 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 2834 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.668442 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31268.903088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 96909500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.994001 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 2817 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88044500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994001 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 2817 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 17366 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34342.074861 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.898293 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 13038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 148632500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.249223 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4328 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 133249500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4277 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1021 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1021 # number of Writeback hits +system.cpu.l2cache.ReadReq_accesses 17406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34339.881224 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.877485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 13028 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 150340000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.251522 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4378 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 134776000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248535 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4326 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.526863 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.500763 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 20201 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34371.098670 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 13056 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 245581500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.353695 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7145 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 221294000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.351171 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 20240 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34364.072272 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31199.846003 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 13045 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 247249500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.355484 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7195 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 222860500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.352915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7143 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 3399.287353 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.862974 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.103738 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011318 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 20201 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34371.098670 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 3426.953059 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 371.809740 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.104582 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011347 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 20240 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34364.072272 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31199.846003 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 13056 # number of overall hits -system.cpu.l2cache.overall_miss_latency 245581500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.353695 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7145 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 221294000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.351171 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7094 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 13045 # number of overall hits +system.cpu.l2cache.overall_miss_latency 247249500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.355484 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7195 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 222860500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.352915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7143 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 53 # number of replacements -system.cpu.l2cache.sampled_refs 5193 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5244 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3770.150327 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13122 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3798.762799 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13114 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 11875967 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25086687 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 104118233 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 89143121 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 963294653 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 11716702 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21387957 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 106791761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 90029129 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 986366370 # number of misc regfile reads system.cpu.misc_regfile_writes 34422259 # number of misc regfile writes -system.cpu.numCycles 303474759 # number of cpu cycles simulated +system.cpu.numCycles 235618984 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 833030 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 340927172 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 47966 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 92085018 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 1568873073 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 396996902 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 382623172 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 66169446 # Number of cycles rename is running -system.cpu.rename.SquashCycles 5956648 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 17891726 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 41695997 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 798025803 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 770847270 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 12413036 # count of serializing insts renamed -system.cpu.rename.skidInsts 58729283 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 3692499 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 668678786 # The number of ROB reads -system.cpu.rob.rob_writes 763715026 # The number of ROB writes -system.cpu.timesIdled 2617 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 1027175 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 384568957 # Number of HB maps that are committed +system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers +system.cpu.rename.IQFullEvents 10287 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 90102617 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 5005619 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 2410888164 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 409625398 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 449508319 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 69271276 # Number of cycles rename is running +system.cpu.rename.SquashCycles 6976526 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 10236681 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 64939357 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1087176407 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1323711757 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 57877200 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3899205 # count of serializing insts renamed +system.cpu.rename.skidInsts 35615164 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 3898099 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 606848093 # The number of ROB reads +system.cpu.rob.rob_writes 784529626 # The number of ROB writes +system.cpu.timesIdled 2791 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index 20eb7fdea..01b0f0b3b 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3277679 # Simulator instruction rate (inst/s) -host_mem_usage 214524 # Number of bytes of host memory used -host_seconds 106.50 # Real time elapsed on the host -host_tick_rate 1993879698 # Simulator tick rate (ticks/s) +host_inst_rate 1939083 # Simulator instruction rate (inst/s) +host_mem_usage 261408 # Number of bytes of host memory used +host_seconds 180.02 # Real time elapsed on the host +host_tick_rate 1179584644 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065408 # Number of instructions simulated sim_seconds 0.212344 # Number of seconds simulated @@ -64,10 +64,10 @@ system.cpu.num_fp_register_writes 126152315 # nu system.cpu.num_func_calls 12433363 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 349065408 # Number of instructions executed -system.cpu.num_int_alu_accesses 287528428 # Number of integer alu accesses -system.cpu.num_int_insts 287528428 # number of integer instructions -system.cpu.num_int_register_reads 1216522338 # number of times the integer registers were read -system.cpu.num_int_register_writes 207564016 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses +system.cpu.num_int_insts 279584926 # number of integer instructions +system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index b979341f1..1ba27a33f 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1789233 # Simulator instruction rate (inst/s) -host_mem_usage 222228 # Number of bytes of host memory used -host_seconds 194.88 # Real time elapsed on the host -host_tick_rate 2698337573 # Simulator tick rate (ticks/s) +host_inst_rate 1262416 # Simulator instruction rate (inst/s) +host_mem_usage 269124 # Number of bytes of host memory used +host_seconds 276.21 # Real time elapsed on the host +host_tick_rate 1903846429 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 348687131 # Number of instructions simulated sim_seconds 0.525854 # Number of seconds simulated @@ -257,10 +257,10 @@ system.cpu.num_fp_register_writes 126152315 # nu system.cpu.num_func_calls 12433363 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 348687131 # Number of instructions executed -system.cpu.num_int_alu_accesses 287528427 # Number of integer alu accesses -system.cpu.num_int_insts 287528427 # number of integer instructions -system.cpu.num_int_register_reads 1352596558 # number of times the integer registers were read -system.cpu.num_int_register_writes 207564015 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses +system.cpu.num_int_insts 279584925 # number of integer instructions +system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written system.cpu.num_load_insts 94648758 # Number of load instructions system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 7274e4b93..40b1b56a0 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 14:31:07 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 14:08:54 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1389,4 +1391,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 869122614500 because target called exit() +Exiting @ tick 796501458500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 37174e363..1bd5ced79 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 95673 # Simulator instruction rate (inst/s) -host_mem_usage 268824 # Number of bytes of host memory used -host_seconds 19706.22 # Real time elapsed on the host -host_tick_rate 44103983 # Simulator tick rate (ticks/s) +host_inst_rate 152621 # Simulator instruction rate (inst/s) +host_mem_usage 267940 # Number of bytes of host memory used +host_seconds 12353.14 # Real time elapsed on the host +host_tick_rate 64477641 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1885343131 # Number of instructions simulated -sim_seconds 0.869123 # Number of seconds simulated -sim_ticks 869122614500 # Number of ticks simulated +sim_insts 1885343121 # Number of instructions simulated +sim_seconds 0.796501 # Number of seconds simulated +sim_ticks 796501458500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 306717434 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 430322374 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 4126641 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 38509304 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 414146262 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 547821195 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 52353944 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 44034324 # The number of times a branch was mispredicted -system.cpu.commit.branches 291352101 # Number of branches committed -system.cpu.commit.bw_lim_events 58391194 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 295401459 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 412226769 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 2841374 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 40219938 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 399767362 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 521351365 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 53524846 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 45744525 # The number of times a branch was mispredicted +system.cpu.commit.branches 291352099 # Number of branches committed +system.cpu.commit.bw_lim_events 67684151 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1159545124 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1569639960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.201138 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1885354137 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 211786 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1014250107 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1409452320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.337650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.030019 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 650998601 46.19% 46.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 389487426 27.63% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 134882374 9.57% 83.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70608044 5.01% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45598376 3.24% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18595515 1.32% 92.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23751287 1.69% 94.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7846546 0.56% 95.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67684151 4.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1569639960 # Number of insts commited each cycle -system.cpu.commit.count 1885354147 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 1409452320 # Number of insts commited each cycle +system.cpu.commit.count 1885354137 # Number of instructions committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.int_insts 1660589568 # Number of committed integer instructions. -system.cpu.commit.loads 631390738 # Number of loads committed +system.cpu.commit.int_insts 1653713091 # Number of committed integer instructions. +system.cpu.commit.loads 631390736 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.refs 908389591 # Number of memory references committed +system.cpu.commit.refs 908389587 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1885343131 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated -system.cpu.cpi 0.921978 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921978 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 16563 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 36000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 16560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 108000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.committedInsts 1885343121 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885343121 # Number of Instructions Simulated +system.cpu.cpi 0.844941 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.844941 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 16769 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 16766 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.000179 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 719743327 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34434.084402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34107.861435 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 717811546 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 66519110000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002684 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1931781 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 469020 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 49891649500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002032 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1462761 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 13541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 13541 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 708570219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34295.515999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34092.262926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 706637503 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 66283492500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1932716 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 469902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 49870639500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1462814 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 13539 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 13539 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35082.855730 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.582320 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276128872 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28305058500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002913 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 806806 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 734090 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2360840000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35038.454246 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32465.652371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 276128758 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28273229500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 806920 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 734193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2361129500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72716 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 72727 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 647.337915 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 15250 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 640.035711 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 56000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 996679005 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34625.216763 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency -system.cpu.dcache.demand_hits 993940418 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94824168500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002748 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2738587 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1203110 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 52252489500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001541 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1535477 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 985505897 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34514.337671 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency +system.cpu.dcache.demand_hits 982766261 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94556722000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002780 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2739636 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1204095 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 52231769000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001558 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1535541 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.913997 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999735 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 996679005 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34625.216763 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4094.850284 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 985505897 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34514.337671 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 993940418 # number of overall hits -system.cpu.dcache.overall_miss_latency 94824168500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002748 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2738587 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1203110 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 52252489500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001541 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1535477 # number of overall MSHR misses +system.cpu.dcache.overall_hits 982766261 # number of overall hits +system.cpu.dcache.overall_miss_latency 94556722000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002780 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2739636 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1204095 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 52231769000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001558 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1535541 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1531378 # number of replacements -system.cpu.dcache.sampled_refs 1535474 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1531438 # number of replacements +system.cpu.dcache.sampled_refs 1535534 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.913997 # Cycle average of tags in use -system.cpu.dcache.total_refs 993970537 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 333433000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106994 # number of writebacks -system.cpu.decode.BlockedCycles 146923379 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 10558 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 87779592 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 3387651447 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 772293047 # Number of cycles decode is idle -system.cpu.decode.RunCycles 647864668 # Number of cycles decode is running -system.cpu.decode.SquashCycles 162682073 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 19702 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 2558864 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.850284 # Cycle average of tags in use +system.cpu.dcache.total_refs 982796595 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 325357000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107000 # number of writebacks +system.cpu.decode.BlockedCycles 41214762 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 11076 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 76817010 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 3347910149 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 727407671 # Number of cycles decode is idle +system.cpu.decode.RunCycles 639439291 # Number of cycles decode is running +system.cpu.decode.SquashCycles 146381913 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 20384 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1390594 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 547821195 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 367105078 # Number of cache lines fetched -system.cpu.fetch.Cycles 665860659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 19277172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2595469256 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1285897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 45421845 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.315158 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 367105078 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 359071378 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.493155 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1732322031 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.998705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.975519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 521351365 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 363393229 # Number of cache lines fetched +system.cpu.fetch.Cycles 657902932 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 20866192 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2539704301 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 47134046 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.327276 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 363393229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 348926305 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.594287 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1555834231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.199016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.044014 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1066497771 61.56% 61.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40398523 2.33% 63.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108471254 6.26% 70.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62827060 3.63% 73.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 83015606 4.79% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 56381906 3.25% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 33027713 1.91% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 49177401 2.84% 86.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232524797 13.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 897966873 57.72% 57.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 37681413 2.42% 60.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 106074065 6.82% 66.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 61536348 3.96% 70.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 89725743 5.77% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53094530 3.41% 80.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35033115 2.25% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 45486191 2.92% 85.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 229235953 14.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1732322031 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 71543247 # number of floating regfile reads -system.cpu.fp_regfile_writes 49528299 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 367105078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9381.938291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6050.959331 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 367080252 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 232916000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 24826 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 434 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 147595000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 24392 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1555834231 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 69468816 # number of floating regfile reads +system.cpu.fp_regfile_writes 51556158 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 363393229 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9064.622402 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5743.022314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 363365607 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 250383000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 27622 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 464 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 155969000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 27158 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15051.057895 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 13383.138890 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 367105078 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9381.938291 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency -system.cpu.icache.demand_hits 367080252 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 232916000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000068 # miss rate for demand accesses -system.cpu.icache.demand_misses 24826 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 434 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147595000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 24392 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 363393229 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9064.622402 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency +system.cpu.icache.demand_hits 363365607 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 250383000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.demand_misses 27622 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 155969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 27158 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1541.532802 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.752702 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 367105078 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9381.938291 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1549.568849 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.756625 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 363393229 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9064.622402 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 367080252 # number of overall hits -system.cpu.icache.overall_miss_latency 232916000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000068 # miss rate for overall accesses -system.cpu.icache.overall_misses 24826 # number of overall misses -system.cpu.icache.overall_mshr_hits 434 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147595000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 24392 # number of overall MSHR misses +system.cpu.icache.overall_hits 363365607 # number of overall hits +system.cpu.icache.overall_miss_latency 250383000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.overall_misses 27622 # number of overall misses +system.cpu.icache.overall_mshr_hits 464 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 155969000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 27158 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 22805 # number of replacements -system.cpu.icache.sampled_refs 24389 # Sample count of references to valid blocks. +system.cpu.icache.replacements 25561 # number of replacements +system.cpu.icache.sampled_refs 27151 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1541.532802 # Cycle average of tags in use -system.cpu.icache.total_refs 367080251 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1549.568849 # Cycle average of tags in use +system.cpu.icache.total_refs 363365604 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 5923199 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 46494560 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 358605233 # Number of branches executed -system.cpu.iew.exec_nop 1350849 # number of nop insts executed -system.cpu.iew.exec_rate 1.388402 # Inst execution rate -system.cpu.iew.exec_refs 1176236253 # number of memory reference insts executed -system.cpu.iew.exec_stores 407328146 # Number of stores executed +system.cpu.idleCycles 37168687 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 49895765 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 348756775 # Number of branches executed +system.cpu.iew.exec_nop 65493 # number of nop insts executed +system.cpu.iew.exec_rate 1.479521 # Inst execution rate +system.cpu.iew.exec_refs 1131335426 # number of memory reference insts executed +system.cpu.iew.exec_stores 371509885 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 11036637 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 946299703 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 229756 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 7912481 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 478952600 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3044913804 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 768908107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 79753358 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2413383308 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 10292588 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 17394060 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 927609743 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 231433 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 9066267 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 465231191 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2899637757 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 759825541 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94064084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2356880983 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2638032 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 325 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 162682073 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 10344235 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 146381913 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3942741 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 36704375 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 1640 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.forwLoads 37882384 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1377639 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 2659902 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 314908964 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 201953747 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2659902 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 7823566 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 38670994 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 2464876715 # num instructions consuming a value -system.cpu.iew.wb_count 2378604713 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.531444 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 2658197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 296219006 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 188232340 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2658197 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 12410188 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37485577 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2331728093 # num instructions consuming a value +system.cpu.iew.wb_count 2317489911 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.562854 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1309943730 # num instructions producing a value -system.cpu.iew.wb_rate 1.368394 # insts written-back per cycle -system.cpu.iew.wb_sent 2386121679 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 5694776843 # number of integer regfile reads -system.cpu.int_regfile_writes 1751148886 # number of integer regfile writes -system.cpu.ipc 1.084624 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.084624 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 1312422376 # num instructions producing a value +system.cpu.iew.wb_rate 1.454793 # insts written-back per cycle +system.cpu.iew.wb_sent 2328575568 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 11595279326 # number of integer regfile reads +system.cpu.int_regfile_writes 2306970978 # number of integer regfile writes +system.cpu.ipc 1.183515 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.183515 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1196267709 48.81% 48.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11218358 0.46% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6177350 0.25% 49.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 25435994 1.04% 50.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 793496500 32.38% 83.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 410088765 16.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2493136666 # Type of FU issued -system.cpu.iq.fp_alu_accesses 66051736 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 126602345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 59166260 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 83365842 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 86890569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 2450945067 # Type of FU issued +system.cpu.iq.fp_alu_accesses 66027207 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 126553287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 57767686 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 103061655 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 75909773 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.030972 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12391 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23967 0.03% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 52380943 69.00% 69.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23492472 30.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 2513975499 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 6687198013 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 2319438453 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 4119676810 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 3043320801 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2493136666 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 242154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1158104053 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 8314426 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 30366 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1709199023 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1732322031 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.439188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 2460827633 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 6419542643 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2259722225 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3795271933 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2899328074 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2450945067 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 244190 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 997384206 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12461792 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 32404 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2708929658 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1555834231 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.575325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.655347 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 573245192 36.84% 36.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 302098178 19.42% 56.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 270294423 17.37% 73.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171510640 11.02% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 147471533 9.48% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56656397 3.64% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24168420 1.55% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7568098 0.49% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2821350 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1732322031 # Number of insts issued each cycle -system.cpu.iq.rate 1.434284 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 1555834231 # Number of insts issued each cycle +system.cpu.iq.rate 1.538569 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,115 +416,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 72713 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.933176 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.414866 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 6629 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2279827500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.908833 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 66084 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048697500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908833 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66084 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1487150 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34256.254935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.334021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 72547 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 48459001000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.951217 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1414603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 43852452500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.951202 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1414580 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72720 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.683474 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.187900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6637 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2279776500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.908732 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66083 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048651500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66083 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1489965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34238.898726 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.364741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 75240 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 48438626000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.949502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1414725 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 43856340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949488 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1414704 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 7 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106994 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106994 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.714286 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107000 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107000 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.053475 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055254 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1559863 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34267.085819 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 79176 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 50738828500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.949242 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1480687 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 45901150000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.949227 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1480664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 1562685 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34250.491961 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 81877 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 50718402500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.947605 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1480808 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 45904991500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.947591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1480787 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 28976.452018 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2993.413242 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.884291 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.091352 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 1559863 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34267.085819 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 28973.685280 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2993.152409 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.884207 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.091344 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 1562685 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34250.491961 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 79176 # number of overall hits -system.cpu.l2cache.overall_miss_latency 50738828500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.949242 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1480687 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 45901150000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.949227 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1480664 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 81877 # number of overall hits +system.cpu.l2cache.overall_miss_latency 50718402500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.947605 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1480808 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 45904991500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.947591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1480787 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1479500 # number of replacements -system.cpu.l2cache.sampled_refs 1512220 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1479625 # number of replacements +system.cpu.l2cache.sampled_refs 1512345 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31969.865261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 80866 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31966.837689 # Cycle average of tags in use +system.cpu.l2cache.total_refs 83563 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.memDep0.conflictingLoads 75887530 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 97070199 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 946299703 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 478952600 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 3932819871 # number of misc regfile reads -system.cpu.misc_regfile_writes 13780014 # number of misc regfile writes -system.cpu.numCycles 1738245230 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 97040035 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144361648 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 927609743 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 465231191 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3829379582 # number of misc regfile reads +system.cpu.misc_regfile_writes 13780010 # number of misc regfile writes +system.cpu.numCycles 1593002918 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 26815429 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1523726473 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 13358705 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 804669593 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 8858159877 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 3258876297 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 2595747725 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 616670755 # Number of cycles rename is running -system.cpu.rename.SquashCycles 162682073 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 32941123 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 1072021249 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 417025150 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 8441134727 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 8500262 # count of serializing insts renamed -system.cpu.rename.skidInsts 93807403 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 250407 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 4556129692 # The number of ROB reads -system.cpu.rob.rob_writes 6252480772 # The number of ROB writes -system.cpu.timesIdled 1346475 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 25386531 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1993168535 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3907408 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 760805018 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 7406697 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 15047193383 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 3194680592 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 3359704809 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 606032208 # Number of cycles rename is running +system.cpu.rename.SquashCycles 146381913 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 13958692 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 1366536269 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 653924872 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 14393268511 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 3269869 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 253997 # count of serializing insts renamed +system.cpu.rename.skidInsts 34813344 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 254310 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 4241354068 # The number of ROB reads +system.cpu.rob.rob_writes 5945603467 # The number of ROB writes +system.cpu.timesIdled 1344843 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index fa8e0bd4e..9d864db40 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3903299 # Simulator instruction rate (inst/s) -host_mem_usage 211416 # Number of bytes of host memory used -host_seconds 483.01 # Real time elapsed on the host -host_tick_rate 1957745790 # Simulator tick rate (ticks/s) +host_inst_rate 1799997 # Simulator instruction rate (inst/s) +host_mem_usage 258316 # Number of bytes of host memory used +host_seconds 1047.41 # Real time elapsed on the host +host_tick_rate 902810159 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885336367 # Number of instructions simulated sim_seconds 0.945613 # Number of seconds simulated @@ -64,10 +64,10 @@ system.cpu.num_fp_register_writes 46777010 # nu system.cpu.num_func_calls 80344203 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1885336367 # Number of instructions executed -system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses -system.cpu.num_int_insts 1660575345 # number of integer instructions -system.cpu.num_int_register_reads 4913858688 # number of times the integer registers were read -system.cpu.num_int_register_writes 1404936302 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 064048304..fd9599dfa 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2093812 # Simulator instruction rate (inst/s) -host_mem_usage 219156 # Number of bytes of host memory used -host_seconds 895.14 # Real time elapsed on the host -host_tick_rate 2647534553 # Simulator tick rate (ticks/s) +host_inst_rate 933614 # Simulator instruction rate (inst/s) +host_mem_usage 266072 # Number of bytes of host memory used +host_seconds 2007.52 # Real time elapsed on the host +host_tick_rate 1180515097 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1874244950 # Number of instructions simulated sim_seconds 2.369902 # Number of seconds simulated @@ -257,10 +257,10 @@ system.cpu.num_fp_register_writes 46777010 # nu system.cpu.num_func_calls 80344203 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1874244950 # Number of instructions executed -system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses -system.cpu.num_int_insts 1660575345 # number of integer instructions -system.cpu.num_int_register_reads 5538311924 # number of times the integer registers were read -system.cpu.num_int_register_writes 1404936302 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index a49d7b0da..f10c82a79 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 1 2011 19:23:04 -M5 started May 1 2011 19:48:10 -M5 executing on u200439-lin.austin.arm.com +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 15:24:46 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 39989822000 because target called exit() +Exiting @ tick 36353754500 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index cfb945d68..cef2ea6da 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,146 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123690 # Simulator instruction rate (inst/s) -host_mem_usage 271412 # Number of bytes of host memory used -host_seconds 813.59 # Real time elapsed on the host -host_tick_rate 49152177 # Simulator tick rate (ticks/s) +host_inst_rate 214709 # Simulator instruction rate (inst/s) +host_mem_usage 270620 # Number of bytes of host memory used +host_seconds 468.69 # Real time elapsed on the host +host_tick_rate 77563856 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 100633290 # Number of instructions simulated -sim_seconds 0.039990 # Number of seconds simulated -sim_ticks 39989822000 # Number of ticks simulated +sim_insts 100633040 # Number of instructions simulated +sim_seconds 0.036354 # Number of seconds simulated +sim_ticks 36353754500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9867090 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15337107 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 176470 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 829676 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11914855 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 18228284 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1851579 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 800204 # The number of times a branch was mispredicted -system.cpu.commit.branches 13669909 # Number of branches committed -system.cpu.commit.bw_lim_events 2821197 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9550734 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14928040 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 176432 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 851746 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11455775 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 17580538 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1841093 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 821012 # The number of times a branch was mispredicted +system.cpu.commit.branches 13669859 # Number of branches committed +system.cpu.commit.bw_lim_events 3808519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 100638842 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 700911 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13587653 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 76811336 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310208 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.890150 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100638592 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 700861 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 11103325 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 69924626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.439244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.122917 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34147257 44.46% 44.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22326004 29.07% 73.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6547391 8.52% 82.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4777302 6.22% 88.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3867270 5.03% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1481997 1.93% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 462917 0.60% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 380001 0.49% 96.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2821197 3.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31252926 44.70% 44.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 20119479 28.77% 73.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4663386 6.67% 80.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4133493 5.91% 86.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3064979 4.38% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1713503 2.45% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 682108 0.98% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 486233 0.70% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3808519 5.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 76811336 # Number of insts commited each cycle -system.cpu.commit.count 100638842 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 69924626 # Number of insts commited each cycle +system.cpu.commit.count 100638592 # Number of instructions committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.int_insts 91477911 # Number of committed integer instructions. -system.cpu.commit.loads 27308390 # Number of loads committed +system.cpu.commit.int_insts 91477711 # Number of committed integer instructions. +system.cpu.commit.loads 27308340 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.refs 47865409 # Number of memory references committed +system.cpu.commit.refs 47865309 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 100633290 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633290 # Number of Instructions Simulated -system.cpu.cpi 0.794763 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.794763 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 18794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13530.303030 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 18761 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 446500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001756 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 33 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 32 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.000053 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 26968856 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22747.311569 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18885.481864 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 26864892 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2364901500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 103964 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 49322 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1031940500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002026 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54642 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 17200 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 17200 # number of StoreCondReq hits +system.cpu.committedInsts 100633040 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633040 # Number of Instructions Simulated +system.cpu.cpi 0.722501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.722501 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 18710 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13233.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 18680 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 397000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001603 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 30 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 30 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 26887551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 22428.849743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18951.207188 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 26783609 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2331299500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003866 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 103942 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49518 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1031400500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 54424 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 17150 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 17150 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32625.233627 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34171.269142 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18304166 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50429965500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.077871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1545735 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1438836 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3652874500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106899 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 32635.826769 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.814138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18303641 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 50463473500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.077898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1546260 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1439342 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3651657500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 106918 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 279.850161 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 279.697951 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 166500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 46818757 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32002.727164 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency -system.cpu.dcache.demand_hits 45169058 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52794867000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035236 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1649699 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1488158 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4684815000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003450 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 161541 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 46737452 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31992.915413 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29025.659779 # average overall mshr miss latency +system.cpu.dcache.demand_hits 45087250 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 52794773000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.035308 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1650202 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1488860 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4683058000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003452 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 161342 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4075.504214 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994996 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 46818757 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32002.727164 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4074.742226 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994810 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 46737452 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31992.915413 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29025.659779 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 45169058 # number of overall hits -system.cpu.dcache.overall_miss_latency 52794867000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035236 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1649699 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1488158 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4684815000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003450 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 161541 # number of overall MSHR misses +system.cpu.dcache.overall_hits 45087250 # number of overall hits +system.cpu.dcache.overall_miss_latency 52794773000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.035308 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1650202 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1488860 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4683058000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003452 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 161342 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157437 # number of replacements -system.cpu.dcache.sampled_refs 161533 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 157232 # number of replacements +system.cpu.dcache.sampled_refs 161328 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4075.504214 # Cycle average of tags in use -system.cpu.dcache.total_refs 45205036 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 123374 # number of writebacks -system.cpu.decode.BlockedCycles 28971891 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 93075 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 3727390 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 120629333 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 25465357 # Number of cycles decode is idle -system.cpu.decode.RunCycles 21763410 # Number of cycles decode is running -system.cpu.decode.SquashCycles 2130818 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 323625 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 610677 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4074.742226 # Cycle average of tags in use +system.cpu.dcache.total_refs 45123111 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314584000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 123248 # number of writebacks +system.cpu.decode.BlockedCycles 22792287 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 94517 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3532335 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 118494504 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 25168271 # Number of cycles decode is idle +system.cpu.decode.RunCycles 21456388 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1835527 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 324840 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 507679 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -162,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 18228284 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 11769962 # Number of cache lines fetched -system.cpu.fetch.Cycles 22827336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 173608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 89202846 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 75 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 898458 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.227912 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 11769962 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 11718669 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.115319 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 78942153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.563587 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.840250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 17580538 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 11694526 # Number of cache lines fetched +system.cpu.fetch.Cycles 22441550 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 172369 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 87382256 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 923972 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.241798 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 11694526 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 11391827 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.201833 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 71760152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.691303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.918883 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56129596 71.10% 71.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2349851 2.98% 74.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2666538 3.38% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2237184 2.83% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1644999 2.08% 82.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1777059 2.25% 84.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 999675 1.27% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1522909 1.93% 87.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9614342 12.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 49333953 68.75% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2332887 3.25% 72.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2565274 3.57% 75.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2261875 3.15% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1646575 2.29% 81.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1680171 2.34% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 992700 1.38% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1397961 1.95% 86.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9548756 13.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 78942153 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 90 # number of floating regfile reads -system.cpu.fp_regfile_writes 71 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 11769962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12766.812347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9293.910530 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11744564 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 324251500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.002158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 25398 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 831 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 228323500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 24567 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 71760152 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 101 # number of floating regfile reads +system.cpu.fp_regfile_writes 77 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 11694526 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12656.148341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9158.013544 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 11668397 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 330692500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.002234 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 26129 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 878 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 231249000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.002159 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 25251 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 478.218331 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 462.334456 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11769962 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12766.812347 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency -system.cpu.icache.demand_hits 11744564 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 324251500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.002158 # miss rate for demand accesses -system.cpu.icache.demand_misses 25398 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 831 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 228323500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.002087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 24567 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 11694526 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12656.148341 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9158.013544 # average overall mshr miss latency +system.cpu.icache.demand_hits 11668397 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 330692500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.002234 # miss rate for demand accesses +system.cpu.icache.demand_misses 26129 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 878 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 231249000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.002159 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 25251 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1794.323879 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.876135 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 11769962 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12766.812347 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1791.221082 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.874620 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 11694526 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12656.148341 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9158.013544 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11744564 # number of overall hits -system.cpu.icache.overall_miss_latency 324251500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.002158 # miss rate for overall accesses -system.cpu.icache.overall_misses 25398 # number of overall misses -system.cpu.icache.overall_mshr_hits 831 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 228323500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.002087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 24567 # number of overall MSHR misses +system.cpu.icache.overall_hits 11668397 # number of overall hits +system.cpu.icache.overall_miss_latency 330692500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.002234 # miss rate for overall accesses +system.cpu.icache.overall_misses 26129 # number of overall misses +system.cpu.icache.overall_mshr_hits 878 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 231249000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.002159 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 25251 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 22528 # number of replacements -system.cpu.icache.sampled_refs 24559 # Sample count of references to valid blocks. +system.cpu.icache.replacements 23207 # number of replacements +system.cpu.icache.sampled_refs 25238 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1794.323879 # Cycle average of tags in use -system.cpu.icache.total_refs 11744564 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1791.221082 # Cycle average of tags in use +system.cpu.icache.total_refs 11668397 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1037492 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 874393 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 14730992 # Number of branches executed -system.cpu.iew.exec_nop 77229 # number of nop insts executed -system.cpu.iew.exec_rate 1.320506 # Inst execution rate -system.cpu.iew.exec_refs 49310444 # number of memory reference insts executed -system.cpu.iew.exec_stores 21021544 # Number of stores executed +system.cpu.idleCycles 947358 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 921550 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14656801 # Number of branches executed +system.cpu.iew.exec_nop 77012 # number of nop insts executed +system.cpu.iew.exec_rate 1.452788 # Inst execution rate +system.cpu.iew.exec_refs 49215024 # number of memory reference insts executed +system.cpu.iew.exec_stores 21014437 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 976883 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29736331 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 738487 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 690502 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 22216200 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 114300611 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28288900 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 942660 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 105613612 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 6120 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 1008310 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29564246 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 729945 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 860230 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 22056705 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 111818970 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28200587 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1136003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 105628608 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3950 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2130818 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 56086 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 5079 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1835527 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 47240 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 1088745 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 2833 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1083799 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2228 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 8497 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 2427929 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1659169 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 8497 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 227081 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 647312 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 107769064 # num instructions consuming a value -system.cpu.iew.wb_count 105038909 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.490744 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 9171 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2255905 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1499736 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 9171 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 239261 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 682289 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 99911986 # num instructions consuming a value +system.cpu.iew.wb_count 105081633 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.522057 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 52886985 # num instructions producing a value -system.cpu.iew.wb_rate 1.313321 # insts written-back per cycle -system.cpu.iew.wb_sent 105210613 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 252852862 # number of integer regfile reads -system.cpu.int_regfile_writes 78118633 # number of integer regfile writes -system.cpu.ipc 1.258236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.258236 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 52159787 # num instructions producing a value +system.cpu.iew.wb_rate 1.445265 # insts written-back per cycle +system.cpu.iew.wb_sent 105241173 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 508070420 # number of integer regfile reads +system.cpu.int_regfile_writes 103566970 # number of integer regfile writes +system.cpu.ipc 1.384080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.384080 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56704676 53.22% 53.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95260 0.09% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28589913 26.83% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21166411 19.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56975144 53.37% 53.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86496 0.08% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 3 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28559455 26.75% 80.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21143495 19.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106556279 # Type of FU issued -system.cpu.iq.fp_alu_accesses 81 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 158 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 142 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 1839661 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017265 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 106764611 # Type of FU issued +system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 153 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1795216 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016815 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 48521 2.64% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1487460 80.86% 83.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 303680 16.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 87233 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1425196 79.39% 84.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 282787 15.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 108395859 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 294001111 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 105038841 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 127626959 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 113467798 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 106556279 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 755584 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 13398397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 106904 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 54673 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 21906182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 78942153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.349802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.549470 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 108559749 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 287203483 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 105081566 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 122521154 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 110994950 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 106764611 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 747008 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10770592 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 119046 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 46147 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 27581574 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 71760152 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.487798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.647275 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30593123 38.75% 38.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20374659 25.81% 64.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 12756017 16.16% 80.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6534002 8.28% 89.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4851612 6.15% 95.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2240036 2.84% 97.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 902250 1.14% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476180 0.60% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 214274 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26733734 37.25% 37.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17263615 24.06% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10576325 14.74% 76.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7516482 10.47% 86.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5241170 7.30% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2631549 3.67% 97.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1101075 1.53% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 499591 0.70% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 196611 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 78942153 # Number of insts issued each cycle -system.cpu.iq.rate 1.332292 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 71760152 # Number of insts issued each cycle +system.cpu.iq.rate 1.468412 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -420,115 +416,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 106892 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.384977 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31241.713044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 4291 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3529616500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.959857 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 102601 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205431000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959857 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 102601 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 79200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34336.641481 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.469055 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 46906 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1108867500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.407753 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32294 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1002781500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.407008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32235 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 8 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.046928 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31243.735685 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 4301 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3529309000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.959768 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205763500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959768 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 79657 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34365.671873 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.753936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 47389 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1108911500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.405087 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32268 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 1001763000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32203 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 123374 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 123374 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.615385 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 8 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.615385 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 123248 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 123248 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.514918 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.517741 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 186092 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34385.885318 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 51197 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4638484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.724883 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134895 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4208212500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.724566 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134836 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 186563 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34389.540531 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.252300 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 51690 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4638220500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.722935 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 134873 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 4207526500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.722587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 134808 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2298.143473 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16005.861783 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070134 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.488460 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 186092 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34385.885318 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2299.680524 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15982.000784 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070181 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487732 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 186563 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34389.540531 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.252300 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 51197 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4638484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.724883 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 134895 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4208212500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.724566 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134836 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 51690 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4638220500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.722935 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 134873 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 4207526500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.722587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 134808 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 114587 # number of replacements -system.cpu.l2cache.sampled_refs 133431 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 114549 # number of replacements +system.cpu.l2cache.sampled_refs 133395 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18304.005255 # Cycle average of tags in use -system.cpu.l2cache.total_refs 68706 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18281.681308 # Cycle average of tags in use +system.cpu.l2cache.total_refs 69064 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 88458 # number of writebacks -system.cpu.memDep0.conflictingLoads 15829057 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13995589 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 29736331 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22216200 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 146370110 # number of misc regfile reads -system.cpu.misc_regfile_writes 34402 # number of misc regfile writes -system.cpu.numCycles 79979645 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 88456 # number of writebacks +system.cpu.memDep0.conflictingLoads 13566871 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13247079 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 29564246 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22056705 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 144417750 # number of misc regfile reads +system.cpu.misc_regfile_writes 34302 # number of misc regfile writes +system.cpu.numCycles 72707510 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2934776 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 75878602 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 208173 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 27131253 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 3054544 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 315617758 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 118187842 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 90561214 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 20595374 # Number of cycles rename is running -system.cpu.rename.SquashCycles 2130818 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 4332267 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 14682576 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 83434 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 315534324 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 21817665 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 758712 # count of serializing insts renamed -system.cpu.rename.skidInsts 12129084 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 759493 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 188191335 # The number of ROB reads -system.cpu.rob.rob_writes 230586603 # The number of ROB writes -system.cpu.timesIdled 60768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 2506668 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 99142533 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 23088 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 26680183 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2442887 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 533141286 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 115984519 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 118104117 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 20356223 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1835527 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 3532279 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 18961579 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 100234 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 533041052 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 16849272 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 756028 # count of serializing insts renamed +system.cpu.rename.skidInsts 10368336 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 756038 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 177832725 # The number of ROB reads +system.cpu.rob.rob_writes 225323365 # The number of ROB writes +system.cpu.timesIdled 61505 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index a40e03286..7bc0f9c46 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3930429 # Simulator instruction rate (inst/s) -host_mem_usage 213832 # Number of bytes of host memory used -host_seconds 25.60 # Real time elapsed on the host -host_tick_rate 2106429498 # Simulator tick rate (ticks/s) +host_inst_rate 3680206 # Simulator instruction rate (inst/s) +host_mem_usage 260724 # Number of bytes of host memory used +host_seconds 27.34 # Real time elapsed on the host +host_tick_rate 1972325214 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100632437 # Number of instructions simulated sim_seconds 0.053932 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 100632437 # Number of instructions executed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_int_insts 91472788 # number of integer instructions -system.cpu.num_int_register_reads 261951567 # number of times the integer registers were read -system.cpu.num_int_register_writes 73126599 # number of times the integer registers were written +system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 4142f5d9a..4595bb26f 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2031292 # Simulator instruction rate (inst/s) -host_mem_usage 221580 # Number of bytes of host memory used -host_seconds 49.13 # Real time elapsed on the host -host_tick_rate 2709639216 # Simulator tick rate (ticks/s) +host_inst_rate 978868 # Simulator instruction rate (inst/s) +host_mem_usage 268480 # Number of bytes of host memory used +host_seconds 101.95 # Real time elapsed on the host +host_tick_rate 1305762006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 99791663 # Number of instructions simulated sim_seconds 0.133117 # Number of seconds simulated @@ -259,8 +259,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 99791663 # Number of instructions executed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_int_insts 91472788 # number of integer instructions -system.cpu.num_int_register_reads 288972903 # number of times the integer registers were read -system.cpu.num_int_register_writes 73126599 # number of times the integer registers were written +system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 274d54dad..c62a2de39 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 15:04:28 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 15:15:49 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +30,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 642890553000 because target called exit() +Exiting @ tick 567799725500 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 599b799cb..2e13b2c1d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 154101 # Simulator instruction rate (inst/s) -host_mem_usage 217652 # Number of bytes of host memory used -host_seconds 11181.42 # Real time elapsed on the host -host_tick_rate 57496303 # Simulator tick rate (ticks/s) +host_inst_rate 218238 # Simulator instruction rate (inst/s) +host_mem_usage 262044 # Number of bytes of host memory used +host_seconds 7895.40 # Real time elapsed on the host +host_tick_rate 71915281 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1723073854 # Number of instructions simulated -sim_seconds 0.642891 # Number of seconds simulated -sim_ticks 642890553000 # Number of ticks simulated +sim_insts 1723073864 # Number of instructions simulated +sim_seconds 0.567800 # Number of seconds simulated +sim_ticks 567799725500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 223193937 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 259593204 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 340 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 18005065 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted -system.cpu.commit.branches 213462366 # Number of branches committed -system.cpu.commit.bw_lim_events 57604302 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 215471079 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 251238209 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 391 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 18325747 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 236131073 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 286913964 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 18098794 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 18325219 # The number of times a branch was mispredicted +system.cpu.commit.branches 213462368 # Number of branches committed +system.cpu.commit.bw_lim_events 71826225 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1166659925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.476929 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1723073882 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 460 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 387631176 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1070469701 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.609643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 480995228 44.93% 44.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 256180333 23.93% 68.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110567341 10.33% 79.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54815725 5.12% 84.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28914668 2.70% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29042780 2.71% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21062487 1.97% 91.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17064914 1.59% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71826225 6.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1166659925 # Number of insts commited each cycle -system.cpu.commit.count 1723073872 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 1070469701 # Number of insts commited each cycle +system.cpu.commit.count 1723073882 # Number of instructions committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. -system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.int_insts 1536941865 # Number of committed integer instructions. +system.cpu.commit.loads 485926774 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.refs 660773819 # Number of memory references committed +system.cpu.commit.refs 660773823 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1723073854 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated -system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.746214 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 27333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 82000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.committedInsts 1723073864 # Number of Instructions Simulated +system.cpu.committedInsts_total 1723073864 # Number of Instructions Simulated +system.cpu.cpi 0.659054 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.659054 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 67 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.042857 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 501584612 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15160.364798 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11507.023204 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 493452712 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 123282570500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 8131900 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 482613 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 88020523000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015250 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7649287 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 63 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 63 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 520005687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 17036.313346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11712.292709 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509774132 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 174307977000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019676 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 10231555 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 2567467 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 89764042000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014738 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7664088 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 65 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23758.689113 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20868.683162 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 168021895 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 108438268431 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.026446 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4564152 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 2672149 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 39483611148 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1892003 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3136.287441 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 69.327600 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 24979 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 78341324 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 24384.889096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22421.774164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 167960973 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 112781916549 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.026799 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4625074 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 2732851 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 42426996773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1892223 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4138.422705 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20785.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 70.920174 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 35824 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 148254855 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 145500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 674170659 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18251.409094 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 661474607 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 231720838931 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.018832 # miss rate for demand accesses -system.cpu.dcache.demand_misses 12696052 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3154762 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 127504134148 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014153 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9541290 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 692591734 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 19324.026571 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13832.852319 # average overall mshr miss latency +system.cpu.dcache.demand_hits 677735105 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 287089893549 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.021451 # miss rate for demand accesses +system.cpu.dcache.demand_misses 14856629 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5300318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 132191038773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9556311 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997826 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4083.025990 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996833 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 692591734 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 19324.026571 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13832.852319 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 661474607 # number of overall hits -system.cpu.dcache.overall_miss_latency 231720838931 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.018832 # miss rate for overall accesses -system.cpu.dcache.overall_misses 12696052 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3154762 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 127504134148 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014153 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9541290 # number of overall MSHR misses +system.cpu.dcache.overall_hits 677735105 # number of overall hits +system.cpu.dcache.overall_miss_latency 287089893549 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.021451 # miss rate for overall accesses +system.cpu.dcache.overall_misses 14856629 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5300318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 132191038773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9556311 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9537194 # number of replacements -system.cpu.dcache.sampled_refs 9541290 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9552215 # number of replacements +system.cpu.dcache.sampled_refs 9556311 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.096656 # Cycle average of tags in use -system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3122149 # number of writebacks -system.cpu.decode.BlockedCycles 127119222 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 630 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 46145837 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 2344585205 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 578307676 # Number of cycles decode is idle -system.cpu.decode.RunCycles 449658106 # Number of cycles decode is running -system.cpu.decode.SquashCycles 70439042 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 2261 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 11574920 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4083.025990 # Cycle average of tags in use +system.cpu.dcache.total_refs 677735237 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6495250000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 3126399 # number of writebacks +system.cpu.decode.BlockedCycles 74308472 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 637 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 43193928 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2255287801 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 552391486 # Number of cycles decode is idle +system.cpu.decode.RunCycles 436619657 # Number of cycles decode is running +system.cpu.decode.SquashCycles 60139906 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2271 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 7150085 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 296310364 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 276394619 # Number of cache lines fetched -system.cpu.fetch.Cycles 469857260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 5099612 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2155595751 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 18544487 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230452 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 276394619 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 240965250 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.676487 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1237098966 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.930612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.884681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 286913964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 267974440 # Number of cache lines fetched +system.cpu.fetch.Cycles 453847586 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5761362 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2078528457 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 20230062 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.252654 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 267974440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 233569873 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.830336 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1130609606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.039152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.930908 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 767241756 62.02% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33244799 2.69% 64.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 58987586 4.77% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 61314807 4.96% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46983054 3.80% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54993105 4.45% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 53020195 4.29% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18334456 1.48% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 142979208 11.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 676762075 59.86% 59.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34315412 3.04% 62.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 55733130 4.93% 67.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 58083869 5.14% 72.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 45528699 4.03% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 55300610 4.89% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 46771165 4.14% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18710110 1.65% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 139404536 12.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1237098966 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 39 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 276394619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34658.288770 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34406.030856 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 276393684 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32405500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1130609606 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 48 # number of floating regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 267974440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35169.574700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34452.712100 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 267973523 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32250500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 935 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 24531500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 917 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 198 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 24771500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 713 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 719 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 387648.925666 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 372703.091794 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 276394619 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34658.288770 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency -system.cpu.icache.demand_hits 276393684 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32405500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 267974440 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35169.574700 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34452.712100 # average overall mshr miss latency +system.cpu.icache.demand_hits 267973523 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32250500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 935 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 24531500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 917 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 198 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 24771500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 713 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 719 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.281945 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 573.603161 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.280080 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 267974440 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35169.574700 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34452.712100 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 276393684 # number of overall hits -system.cpu.icache.overall_miss_latency 32405500 # number of overall miss cycles +system.cpu.icache.overall_hits 267973523 # number of overall hits +system.cpu.icache.overall_miss_latency 32250500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 935 # number of overall misses -system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 24531500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 917 # number of overall misses +system.cpu.icache.overall_mshr_hits 198 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 24771500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 713 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 719 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8 # number of replacements -system.cpu.icache.sampled_refs 713 # Sample count of references to valid blocks. +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.sampled_refs 719 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.423416 # Cycle average of tags in use -system.cpu.icache.total_refs 276393684 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 573.603161 # Cycle average of tags in use +system.cpu.icache.total_refs 267973523 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 233410057 # Number of branches executed -system.cpu.iew.exec_nop 371 # number of nop insts executed -system.cpu.iew.exec_rate 1.517006 # Inst execution rate -system.cpu.iew.exec_refs 747857641 # number of memory reference insts executed -system.cpu.iew.exec_stores 187754946 # Number of stores executed +system.cpu.idleCycles 4989846 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 20125806 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 235514393 # Number of branches executed +system.cpu.iew.exec_nop 296 # number of nop insts executed +system.cpu.iew.exec_rate 1.713630 # Inst execution rate +system.cpu.iew.exec_refs 742460046 # number of memory reference insts executed +system.cpu.iew.exec_stores 185795418 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5945884 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 225252424 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2211114719 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 560102695 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21129397 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1950537549 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1433857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 18248815 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 598179019 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 540 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6117477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 212168948 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2110540592 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 556664628 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 28602946 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1945996752 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 245772 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 55469 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 60139906 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1077846 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 54506765 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.cacheBlocked 273714 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 32169435 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 459248 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 734835 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 140151655 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 50405377 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 2256424150 # num instructions consuming a value -system.cpu.iew.wb_count 1928710637 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.551017 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 1853009 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 112252244 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 37321899 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1853009 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3267376 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 16858430 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1884646665 # num instructions consuming a value +system.cpu.iew.wb_count 1921636859 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.642567 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1243327288 # num instructions producing a value -system.cpu.iew.wb_rate 1.500030 # insts written-back per cycle -system.cpu.iew.wb_sent 1934940770 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads -system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes -system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 1211011051 # num instructions producing a value +system.cpu.iew.wb_rate 1.692178 # insts written-back per cycle +system.cpu.iew.wb_sent 1926273504 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 9735130843 # number of integer regfile reads +system.cpu.int_regfile_writes 1902150318 # number of integer regfile writes +system.cpu.ipc 1.517325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.517325 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219271237 61.75% 61.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1051701 0.05% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 12 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 566539676 28.69% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 187737057 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1971666946 # Type of FU issued -system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 20875026 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 1974599698 # Type of FU issued +system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 168 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 24432078 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012373 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 518261 2.12% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 23578927 96.51% 98.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 334888 1.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2696699928 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2211113711 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1971666946 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 637 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 484979968 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1237098966 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.593783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 1999031702 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5105133398 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1921636797 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2491239828 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2110539690 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1974599698 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 606 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 378853333 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 892460 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 146 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 851689687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1130609606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.746491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.678752 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 343530730 30.38% 30.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 241793067 21.39% 51.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 218551738 19.33% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140017220 12.38% 83.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 100970740 8.93% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 54673459 4.84% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 20221073 1.79% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9737830 0.86% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1113749 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1237098966 # Number of insts issued each cycle -system.cpu.iq.rate 1.533439 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 1130609606 # Number of insts issued each cycle +system.cpu.iq.rate 1.738817 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,107 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1892006 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34501.539320 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.195670 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 979915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 31468543500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 912091 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28586022500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 912091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7649997 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34318.289104 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.516872 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5630330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 69311516000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.264009 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2019667 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_accesses 1892225 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34668.138336 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31525.497909 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 980562 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 31605659000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.481794 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 911663 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28740630000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481794 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 911663 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7664805 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.590029 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.423829 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5643096 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 69398376000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.263765 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2021709 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 62868927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264008 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2019657 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 3122149 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3122149 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3935.335196 # average number of cycles each access was blocked +system.cpu.l2cache.ReadReq_mshr_miss_latency 62984867500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2021699 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 3126399 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 3126399 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8610.632689 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.653954 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 3580 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.658362 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 5690 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 14088500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 48994500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9542003 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34375.299564 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6610245 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 100780059500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.307248 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2931758 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9557030 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34432.739864 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.750375 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6623658 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 101004035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.306933 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2933372 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 91454949500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.307247 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2931748 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 91725497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.306932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2933362 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329914 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 15787.476515 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10639.481396 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.481796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.324691 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 9557030 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34432.739864 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.750375 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6610245 # number of overall hits -system.cpu.l2cache.overall_miss_latency 100780059500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.307248 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2931758 # number of overall misses +system.cpu.l2cache.overall_hits 6623658 # number of overall hits +system.cpu.l2cache.overall_miss_latency 101004035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.306933 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2933372 # number of overall misses system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 91454949500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.307247 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2931748 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 91725497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.306932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2933362 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2919341 # number of replacements -system.cpu.l2cache.sampled_refs 2946667 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2921001 # number of replacements +system.cpu.l2cache.sampled_refs 2948324 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26801.023686 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7820318 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 143319905000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1216305 # number of writebacks -system.cpu.memDep0.conflictingLoads 95681801 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90040335 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 626078428 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225252424 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 2884001507 # number of misc regfile reads -system.cpu.misc_regfile_writes 128 # number of misc regfile writes -system.cpu.numCycles 1285781107 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 26426.957911 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7837713 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 129803259500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1216468 # number of writebacks +system.cpu.memDep0.conflictingLoads 87202635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 84882545 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 598179019 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 212168948 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 2797025769 # number of misc regfile reads +system.cpu.misc_regfile_writes 132 # number of misc regfile writes +system.cpu.numCycles 1135599452 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 67172415 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1360917377 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 14851346 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 600335413 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 10242 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 6331353991 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 2292668273 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 1803116545 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 438383597 # Number of cycles rename is running -system.cpu.rename.SquashCycles 70439042 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 60752889 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 442199165 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 393 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 6331353598 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 15610 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 650 # count of serializing insts renamed -system.cpu.rename.skidInsts 118137729 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 645 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3320275044 # The number of ROB reads -system.cpu.rob.rob_writes 4492885352 # The number of ROB writes -system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 43624609 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1706319975 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3032404 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 568994598 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 25723615 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 11682 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 10112299112 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2191283557 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2168556618 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 426283235 # Number of cycles rename is running +system.cpu.rename.SquashCycles 60139906 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 31553217 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 462236638 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 1010 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 10112298102 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 14041 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 629 # count of serializing insts renamed +system.cpu.rename.skidInsts 61919422 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 626 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3109347935 # The number of ROB reads +system.cpu.rob.rob_writes 4281671298 # The number of ROB writes +system.cpu.timesIdled 552036 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index bd13defc5..42e09915d 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4004296 # Simulator instruction rate (inst/s) -host_mem_usage 206252 # Number of bytes of host memory used -host_seconds 430.31 # Real time elapsed on the host -host_tick_rate 2002150173 # Simulator tick rate (ticks/s) +host_inst_rate 3743034 # Simulator instruction rate (inst/s) +host_mem_usage 253144 # Number of bytes of host memory used +host_seconds 460.34 # Real time elapsed on the host +host_tick_rate 1871519168 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073862 # Number of instructions simulated sim_seconds 0.861538 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1723073862 # Number of instructions executed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_int_insts 1536941850 # number of integer instructions -system.cpu.num_int_register_reads 4663954117 # number of times the integer registers were read -system.cpu.num_int_register_writes 1329729952 # number of times the integer registers were written +system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 1dcb25e1c..c692715dc 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2103726 # Simulator instruction rate (inst/s) -host_mem_usage 213996 # Number of bytes of host memory used -host_seconds 816.30 # Real time elapsed on the host -host_tick_rate 2978588238 # Simulator tick rate (ticks/s) +host_inst_rate 1772581 # Simulator instruction rate (inst/s) +host_mem_usage 260892 # Number of bytes of host memory used +host_seconds 968.80 # Real time elapsed on the host +host_tick_rate 2509731503 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1717270343 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -259,8 +259,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1717270343 # Number of instructions executed system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses system.cpu.num_int_insts 1536941850 # number of integer instructions -system.cpu.num_int_register_reads 5142795796 # number of times the integer registers were read -system.cpu.num_int_register_writes 1329729952 # number of times the integer registers were written +system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read +system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written system.cpu.num_load_insts 485926770 # Number of load instructions system.cpu.num_mem_refs 660773816 # number of memory refs system.cpu.num_store_insts 174847046 # Number of store instructions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index e91437a5d..19caace72 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 15:06:04 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 14:48:18 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 125793203000 because target called exit() +122 123 124 Exiting @ tick 114589481500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index e312dcfc6..debcad22a 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 111275 # Simulator instruction rate (inst/s) -host_mem_usage 221396 # Number of bytes of host memory used -host_seconds 1695.51 # Real time elapsed on the host -host_tick_rate 74191752 # Simulator tick rate (ticks/s) +host_inst_rate 145628 # Simulator instruction rate (inst/s) +host_mem_usage 265820 # Number of bytes of host memory used +host_seconds 1295.56 # Real time elapsed on the host +host_tick_rate 88448039 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 188669132 # Number of instructions simulated -sim_seconds 0.125793 # Number of seconds simulated -sim_ticks 125793203000 # Number of ticks simulated +sim_insts 188668737 # Number of instructions simulated +sim_seconds 0.114589 # Number of seconds simulated +sim_ticks 114589481500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 83359858 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 88566677 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 111813 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 9866046 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 86389460 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 110931092 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 4559844 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 9726959 # The number of times a branch was mispredicted -system.cpu.commit.branches 40284207 # Number of branches committed -system.cpu.commit.bw_lim_events 1785335 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 74760196 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 79995618 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 111816 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 10349538 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 77060035 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 98242064 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 4425750 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 10211892 # The number of times a branch was mispredicted +system.cpu.commit.branches 40284128 # Number of branches committed +system.cpu.commit.bw_lim_events 3189966 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 188683520 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 1635919 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 179794570 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 224388172 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.840880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188683125 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 1635840 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 132289806 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 207214501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.910569 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.539108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 117707920 56.80% 56.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47326882 22.84% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20304092 9.80% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8456473 4.08% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5239140 2.53% 96.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1942567 0.94% 96.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2142710 1.03% 98.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 904751 0.44% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3189966 1.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 224388172 # Number of insts commited each cycle -system.cpu.commit.count 188683520 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 207214501 # Number of insts commited each cycle +system.cpu.commit.count 188683125 # Number of instructions committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.int_insts 150271150 # Number of committed integer instructions. -system.cpu.commit.loads 29852009 # Number of loads committed +system.cpu.commit.int_insts 150116005 # Number of committed integer instructions. +system.cpu.commit.loads 29851930 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.refs 42499167 # Number of memory references committed +system.cpu.commit.refs 42499009 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 188669132 # Number of Instructions Simulated -system.cpu.committedInsts_total 188669132 # Number of Instructions Simulated -system.cpu.cpi 1.333479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.333479 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 26643 # number of LoadLockedReq accesses(hits+misses) +system.cpu.committedInsts 188668737 # Number of Instructions Simulated +system.cpu.committedInsts_total 188668737 # Number of Instructions Simulated +system.cpu.cpi 1.214716 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.214716 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 26526 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 26641 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits 26524 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_rate 0.000075 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 38482154 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33506.489293 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32275.510204 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 38480613 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 51633500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1541 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 735 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 24931 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 24931 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 36836691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32644.833427 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32223.719677 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 36834920 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 57814000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000048 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1771 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1029 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 23910000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 742 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 24852 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 24852 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31178.656598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35098.901099 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 12356739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 235336500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7548 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 38328000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 31348.093725 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35116.758242 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 12356733 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 236803500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7554 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 38347500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 27853.817187 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 26864.722313 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 50846441 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31573.330399 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency -system.cpu.dcache.demand_hits 50837352 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 286970000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000179 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9089 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 7262 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 62050500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1827 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 49200978 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31594.369973 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33946.292257 # average overall mshr miss latency +system.cpu.dcache.demand_hits 49191653 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 294617500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000190 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9325 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 7491 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 62257500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1834 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1387.955871 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.338856 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 50846441 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31573.330399 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 1395.552568 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.340711 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 49200978 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31594.369973 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33946.292257 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 50837352 # number of overall hits -system.cpu.dcache.overall_miss_latency 286970000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000179 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9089 # number of overall misses -system.cpu.dcache.overall_mshr_hits 7262 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 62050500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1827 # number of overall MSHR misses +system.cpu.dcache.overall_hits 49191653 # number of overall hits +system.cpu.dcache.overall_miss_latency 294617500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000190 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9325 # number of overall misses +system.cpu.dcache.overall_mshr_hits 7491 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 62257500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1834 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.sampled_refs 1827 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 49 # number of replacements +system.cpu.dcache.sampled_refs 1833 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1387.955871 # Cycle average of tags in use -system.cpu.dcache.total_refs 50888924 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1395.552568 # Cycle average of tags in use +system.cpu.dcache.total_refs 49243036 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 16 # number of writebacks -system.cpu.decode.BlockedCycles 36464777 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 170249 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 17878904 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 446600367 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 82272510 # Number of cycles decode is idle -system.cpu.decode.RunCycles 104826667 # Number of cycles decode is running -system.cpu.decode.SquashCycles 27129630 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 707147 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 824217 # Number of cycles decode is unblocking +system.cpu.dcache.writebacks 17 # number of writebacks +system.cpu.decode.BlockedCycles 32329175 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 166208 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 14317214 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 406876360 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 79350559 # Number of cycles decode is idle +system.cpu.decode.RunCycles 94851777 # Number of cycles decode is running +system.cpu.decode.SquashCycles 21897649 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 708566 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 682989 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 110931092 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 38679890 # Number of cache lines fetched -system.cpu.fetch.Cycles 111498626 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2123796 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 437074245 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 10106938 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.440926 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 38679890 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 87919702 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.737273 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 251517801 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.873210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.581419 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 98242064 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 37011796 # Number of cache lines fetched +system.cpu.fetch.Cycles 102039448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2084661 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 401290022 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10742446 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.428670 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 37011796 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 79185946 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.750990 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 229112149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.602797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140210227 55.75% 55.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4303837 1.71% 57.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33014843 13.13% 70.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15960765 6.35% 76.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9874938 3.93% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16484434 6.55% 87.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8406542 3.34% 90.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5529159 2.20% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17733056 7.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 127250145 55.54% 55.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4018044 1.75% 57.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29090462 12.70% 69.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15702504 6.85% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9815384 4.28% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13327940 5.82% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7882856 3.44% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4750026 2.07% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 17274788 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 251517801 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2866910 # number of floating regfile reads -system.cpu.fp_regfile_writes 2464301 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 38679890 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 23669.425633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20344.827586 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 38675903 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 94370000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3987 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 478 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 71390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000091 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3509 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 229112149 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2915845 # number of floating regfile reads +system.cpu.fp_regfile_writes 2459384 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 37011796 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 23764.120428 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20374.787294 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 37007777 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 95508000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000109 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 493 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 71841500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000095 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3526 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11021.915930 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10498.660142 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 38679890 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 23669.425633 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency -system.cpu.icache.demand_hits 38675903 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 94370000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000103 # miss rate for demand accesses -system.cpu.icache.demand_misses 3987 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 478 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 71390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000091 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3509 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 37011796 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 23764.120428 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20374.787294 # average overall mshr miss latency +system.cpu.icache.demand_hits 37007777 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 95508000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000109 # miss rate for demand accesses +system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 493 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 71841500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000095 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3526 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1270.764699 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.620491 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 38679890 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 23669.425633 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1276.804996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.623440 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 37011796 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 23764.120428 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20374.787294 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 38675903 # number of overall hits -system.cpu.icache.overall_miss_latency 94370000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000103 # miss rate for overall accesses -system.cpu.icache.overall_misses 3987 # number of overall misses -system.cpu.icache.overall_mshr_hits 478 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 71390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000091 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3509 # number of overall MSHR misses +system.cpu.icache.overall_hits 37007777 # number of overall hits +system.cpu.icache.overall_miss_latency 95508000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000109 # miss rate for overall accesses +system.cpu.icache.overall_misses 4019 # number of overall misses +system.cpu.icache.overall_mshr_hits 493 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 71841500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000095 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3526 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1854 # number of replacements -system.cpu.icache.sampled_refs 3509 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1866 # number of replacements +system.cpu.icache.sampled_refs 3525 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1270.764699 # Cycle average of tags in use -system.cpu.icache.total_refs 38675903 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1276.804996 # Cycle average of tags in use +system.cpu.icache.total_refs 37007777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 68606 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 11160275 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 53273558 # Number of branches executed -system.cpu.iew.exec_nop 53064 # number of nop insts executed -system.cpu.iew.exec_rate 0.964190 # Inst execution rate -system.cpu.iew.exec_refs 53783248 # number of memory reference insts executed -system.cpu.iew.exec_stores 13613267 # Number of stores executed +system.cpu.idleCycles 66815 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 11832778 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 51965807 # Number of branches executed +system.cpu.iew.exec_nop 52722 # number of nop insts executed +system.cpu.iew.exec_rate 1.079834 # Inst execution rate +system.cpu.iew.exec_refs 51989932 # number of memory reference insts executed +system.cpu.iew.exec_stores 13440828 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 19997 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 50338304 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2241625 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4879199 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 18109550 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 368485815 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 40169981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7843894 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 242577015 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 4549 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 16073 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 47405288 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2181665 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 8564193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16540037 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 320981934 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 38549104 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13994480 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 247475158 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 251 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2590 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 27129630 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 7356 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3185 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 21897649 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3565 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 954573 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 20572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.forwLoads 982919 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 222499 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 20486294 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 5462392 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 284801843 # num instructions consuming a value -system.cpu.iew.wb_count 238885590 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.499623 # average fanout of values written-back +system.cpu.iew.lsq.thread0.memOrderViolation 453121 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 17553357 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 3892958 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 453121 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2166634 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 9666144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 237697826 # num instructions consuming a value +system.cpu.iew.wb_count 243310186 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.616543 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 142293577 # num instructions producing a value -system.cpu.iew.wb_rate 0.949517 # insts written-back per cycle -system.cpu.iew.wb_sent 240138833 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 542109498 # number of integer regfile reads -system.cpu.int_regfile_writes 231159216 # number of integer regfile writes -system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 146551038 # num instructions producing a value +system.cpu.iew.wb_rate 1.061660 # insts written-back per cycle +system.cpu.iew.wb_sent 244563892 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1105271362 # number of integer regfile reads +system.cpu.int_regfile_writes 405517163 # number of integer regfile writes +system.cpu.ipc 0.823238 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.823238 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 205122709 78.45% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918079 0.35% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 10109 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 32866 0.01% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166325 0.06% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 251418 0.10% 78.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76052 0.03% 79.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 462207 0.18% 79.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207191 0.08% 79.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71628 0.03% 79.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 79.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 40432924 15.46% 94.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13717806 5.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 250420912 # Type of FU issued -system.cpu.iq.fp_alu_accesses 1881090 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 3742288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 1821838 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 2251906 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 1580075 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst) +system.cpu.iq.FU_type_0::total 261469638 # Type of FU issued +system.cpu.iq.fp_alu_accesses 1855088 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3701583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1822597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2110861 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1743440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006668 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 109941 6.31% 6.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5520 0.32% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1271011 72.90% 79.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 356956 20.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 250119897 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 750424252 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 237063752 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 543997175 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 366166997 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 250420912 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2265754 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 177594377 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 226843 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 629835 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 280770553 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 251517801 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.995639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 261357990 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 750654117 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 241487589 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 445672842 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 318723473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 261469638 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2205739 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 126475271 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 560835 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 569899 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 283578220 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 229112149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.141230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.407706 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108319489 47.28% 47.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46636134 20.36% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34199454 14.93% 82.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22104068 9.65% 92.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11622825 5.07% 97.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4159052 1.82% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1773728 0.77% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 185728 0.08% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111671 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 251517801 # Number of insts issued each cycle -system.cpu.iq.rate 0.995367 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 229112149 # Number of insts issued each cycle +system.cpu.iq.rate 1.140897 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,106 +416,113 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1092 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34291.512915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31033.671587 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 37172000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.992674 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1084 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33640500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992674 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1084 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4244 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34289.280186 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.066978 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1660 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 88603500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.608860 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2584 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34343.345656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 37159500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33586500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4267 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34290.769231 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31075.270898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1667 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 89156000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.609327 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2600 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 79790500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2568 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 80298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2584 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.644410 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.643133 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 5336 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34289.940022 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1668 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 125775500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.687406 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3668 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 5358 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34306.219446 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.193672 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1676 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 126315500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.687197 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3682 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 113431000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.684408 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3652 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 113885000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.684211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3666 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1832.230344 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.029186 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.055915 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 5336 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34289.940022 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1849.891639 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.054324 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.056454 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 5358 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34306.219446 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.193672 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1668 # number of overall hits -system.cpu.l2cache.overall_miss_latency 125775500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.687406 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3668 # number of overall misses +system.cpu.l2cache.overall_hits 1676 # number of overall hits +system.cpu.l2cache.overall_miss_latency 126315500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.687197 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3682 # number of overall misses system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 113431000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.684408 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3652 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 113885000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.684211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3666 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2576 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2592 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1835.259530 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1660 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1852.945963 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1667 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 5314098 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4016301 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 50338304 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18109550 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 524567378 # number of misc regfile reads -system.cpu.misc_regfile_writes 825084 # number of misc regfile writes -system.cpu.numCycles 251586407 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 6544677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3988120 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 47405288 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16540037 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 486015075 # number of misc regfile reads +system.cpu.misc_regfile_writes 824926 # number of misc regfile writes +system.cpu.numCycles 229178964 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 895052 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 180981200 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 614225 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 90974405 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 956098353 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 414819410 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 416850208 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 96863032 # Number of cycles rename is running -system.cpu.rename.SquashCycles 27129630 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 5258013 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 235869004 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 13790121 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 942308232 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 2658319 # count of serializing insts renamed -system.cpu.rename.skidInsts 23659926 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 2454002 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 591075726 # The number of ROB reads -system.cpu.rob.rob_writes 764090765 # The number of ROB writes -system.cpu.timesIdled 1409 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 628152 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 298063712 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 76310 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 88142663 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1597239 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 1589178031 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 372125350 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 635131206 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 86698420 # Number of cycles rename is running +system.cpu.rename.SquashCycles 21897649 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 3896290 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 337067489 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 16987486 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1572190545 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 27848975 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2565042 # count of serializing insts renamed +system.cpu.rename.skidInsts 20623537 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2528667 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 524992265 # The number of ROB reads +system.cpu.rob.rob_writes 663874910 # The number of ROB writes +system.cpu.timesIdled 1540 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index bdd5452bf..a4b991833 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3821612 # Simulator instruction rate (inst/s) -host_mem_usage 209488 # Number of bytes of host memory used -host_seconds 49.37 # Real time elapsed on the host -host_tick_rate 2088466357 # Simulator tick rate (ticks/s) +host_inst_rate 1596483 # Simulator instruction rate (inst/s) +host_mem_usage 256912 # Number of bytes of host memory used +host_seconds 118.18 # Real time elapsed on the host +host_tick_rate 872460307 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188670900 # Number of instructions simulated sim_seconds 0.103107 # Number of seconds simulated @@ -64,10 +64,10 @@ system.cpu.num_fp_register_writes 2378039 # nu system.cpu.num_func_calls 3504894 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 188670900 # Number of instructions executed -system.cpu.num_int_alu_accesses 150261055 # Number of integer alu accesses -system.cpu.num_int_insts 150261055 # number of integer instructions -system.cpu.num_int_register_reads 444541710 # number of times the integer registers were read -system.cpu.num_int_register_writes 177007633 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6b9d8abcc..022cf6be1 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2299830 # Simulator instruction rate (inst/s) -host_mem_usage 217236 # Number of bytes of host memory used -host_seconds 81.83 # Real time elapsed on the host -host_tick_rate 2836221203 # Simulator tick rate (ticks/s) +host_inst_rate 1108469 # Simulator instruction rate (inst/s) +host_mem_usage 264128 # Number of bytes of host memory used +host_seconds 169.77 # Real time elapsed on the host +host_tick_rate 1366998833 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188185929 # Number of instructions simulated sim_seconds 0.232077 # Number of seconds simulated @@ -257,10 +257,10 @@ system.cpu.num_fp_register_writes 2378039 # nu system.cpu.num_func_calls 3504894 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 188185929 # Number of instructions executed -system.cpu.num_int_alu_accesses 150261055 # Number of integer alu accesses -system.cpu.num_int_insts 150261055 # number of integer instructions -system.cpu.num_int_register_reads 474507625 # number of times the integer registers were read -system.cpu.num_int_register_writes 177007633 # number of times the integer registers were written +system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses +system.cpu.num_int_insts 150106226 # number of integer instructions +system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read +system.cpu.num_int_register_writes 294073530 # number of times the integer registers were written system.cpu.num_load_insts 29849485 # Number of load instructions system.cpu.num_mem_refs 42494120 # number of memory refs system.cpu.num_store_insts 12644635 # Number of store instructions diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index f5ea06dc5..811dc859b 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 12:05:01 -M5 started Apr 21 2011 15:18:29 -M5 executing on maize +M5 compiled May 4 2011 13:56:47 +M5 started May 4 2011 14:21:49 +M5 executing on nadc-0364 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10803500 because target called exit() +Exiting @ tick 10782500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 1ac2ece63..7db13d16a 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 81044 # Simulator instruction rate (inst/s) -host_mem_usage 215360 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 152195453 # Simulator tick rate (ticks/s) +host_inst_rate 97592 # Simulator instruction rate (inst/s) +host_mem_usage 257968 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 182664453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10803500 # Number of ticks simulated +sim_ticks 10782500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 701 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 406 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1671 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2180 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 317 # The number of times a branch was mispredicted +system.cpu.BPredUnit.BTBHits 725 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1851 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2185 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 238 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted system.cpu.commit.branches 945 # Number of branches committed -system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4490 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 11008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245214 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 4364 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 10921 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286416 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8442 76.69% 76.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1229 11.16% 87.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 550 5.00% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 321 2.92% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.67% 97.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 1.24% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.46% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.29% 99.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62 0.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8444 77.32% 77.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1188 10.88% 88.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 479 4.39% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 318 2.91% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 171 1.57% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 152 1.39% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 62 0.57% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.30% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10921 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. @@ -50,8 +50,8 @@ system.cpu.commit.refs 2139 # Nu system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.765116 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.765116 # CPI: Total CPI of All Threads +system.cpu.cpi 3.757798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.757798 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits @@ -59,84 +59,84 @@ system.cpu.dcache.LoadLockedReq_miss_latency 76500 system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 1818 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33323.717949 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30423.809524 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1662 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5198500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.085809 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 156 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3194500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 1795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32493.670886 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29240.566038 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5134000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.088022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 158 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059053 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 106 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35788.659794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35800.687285 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35880.952381 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10414500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10418000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1507000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 15.673469 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.398649 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2731 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34928.411633 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2284 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15613000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.163676 # miss rate for demand accesses -system.cpu.dcache.demand_misses 447 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4699500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.053826 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2708 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34636.971047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31125 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15552000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.165805 # miss rate for demand accesses +system.cpu.dcache.demand_misses 449 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4606500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.054653 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 89.381733 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021822 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2731 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34928.411633 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 89.451060 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021839 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 2708 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34636.971047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31125 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2284 # number of overall hits -system.cpu.dcache.overall_miss_latency 15613000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.163676 # miss rate for overall accesses -system.cpu.dcache.overall_misses 447 # number of overall misses -system.cpu.dcache.overall_mshr_hits 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4699500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.053826 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 147 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2259 # number of overall hits +system.cpu.dcache.overall_miss_latency 15552000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.165805 # miss rate for overall accesses +system.cpu.dcache.overall_misses 449 # number of overall misses +system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4606500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.054653 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 89.381733 # Cycle average of tags in use -system.cpu.dcache.total_refs 2304 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.451060 # Cycle average of tags in use +system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 1281 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 346 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 12207 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 7419 # Number of cycles decode is idle -system.cpu.decode.RunCycles 2259 # Number of cycles decode is running -system.cpu.decode.SquashCycles 770 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 1179 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 352 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 12101 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 7437 # Number of cycles decode is idle +system.cpu.decode.RunCycles 2257 # Number of cycles decode is running +system.cpu.decode.SquashCycles 777 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 565 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,241 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1601 # Number of cache lines fetched -system.cpu.fetch.Cycles 2402 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 236 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11132 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 496 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.100889 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 943 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.515180 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.177210 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.592697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2185 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1628 # Number of cache lines fetched +system.cpu.fetch.Cycles 2410 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11189 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.101317 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1628 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 963 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.518826 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.186202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.597096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9375 79.60% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224 1.90% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 1.27% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.73% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 190 1.61% 86.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 260 2.21% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 117 0.99% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 96 0.82% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1162 9.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9287 79.40% 79.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223 1.91% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 149 1.27% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 211 1.80% 84.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 194 1.66% 86.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 259 2.21% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 122 1.04% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 98 0.84% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1154 9.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11697 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34737.313433 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33334.494774 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1266 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11637000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.209244 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 335 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9567000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.179263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35051.051051 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33594.076655 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1295 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11672000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.204545 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 333 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 9641500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.176290 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 287 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.411150 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.512195 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1601 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34737.313433 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency -system.cpu.icache.demand_hits 1266 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11637000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.209244 # miss rate for demand accesses -system.cpu.icache.demand_misses 335 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9567000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.179263 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1628 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35051.051051 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency +system.cpu.icache.demand_hits 1295 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11672000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.204545 # miss rate for demand accesses +system.cpu.icache.demand_misses 333 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 9641500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.176290 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 287 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 145.986730 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.071283 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1601 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34737.313433 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 147.191898 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.071871 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 1628 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35051.051051 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33594.076655 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1266 # number of overall hits -system.cpu.icache.overall_miss_latency 11637000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.209244 # miss rate for overall accesses -system.cpu.icache.overall_misses 335 # number of overall misses -system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9567000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.179263 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1295 # number of overall hits +system.cpu.icache.overall_miss_latency 11672000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.204545 # miss rate for overall accesses +system.cpu.icache.overall_misses 333 # number of overall misses +system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 9641500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.176290 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 287 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.sampled_refs 287 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 145.986730 # Cycle average of tags in use -system.cpu.icache.total_refs 1266 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 147.191898 # Cycle average of tags in use +system.cpu.icache.total_refs 1295 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9831 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 365 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.idleCycles 9869 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 1360 # Number of branches executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_rate 0.372316 # Inst execution rate -system.cpu.iew.exec_refs 3091 # number of memory reference insts executed -system.cpu.iew.exec_stores 1139 # Number of stores executed +system.cpu.iew.exec_rate 0.377446 # Inst execution rate +system.cpu.iew.exec_refs 3052 # number of memory reference insts executed +system.cpu.iew.exec_stores 1120 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 209 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1498 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10370 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1952 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8045 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2335 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10208 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8140 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 777 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1171 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 560 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 7215 # num instructions consuming a value -system.cpu.iew.wb_count 7676 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.492862 # average fanout of values written-back +system.cpu.iew.lsq.thread0.squashedLoads 1134 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 6995 # num instructions consuming a value +system.cpu.iew.wb_count 7761 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.509078 # average fanout of values written-back system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 3556 # num instructions producing a value -system.cpu.iew.wb_rate 0.355239 # insts written-back per cycle -system.cpu.iew.wb_sent 7793 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 18334 # number of integer regfile reads -system.cpu.int_regfile_writes 5503 # number of integer regfile writes -system.cpu.ipc 0.265596 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265596 # IPC: Total IPC of All Threads +system.cpu.iew.wb_producers 3561 # num instructions producing a value +system.cpu.iew.wb_rate 0.359872 # insts written-back per cycle +system.cpu.iew.wb_sent 7887 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 37201 # number of integer regfile reads +system.cpu.int_regfile_writes 7643 # number of integer regfile writes +system.cpu.ipc 0.266113 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266113 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5116 61.06% 61.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2082 24.85% 86.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1172 13.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5232 61.80% 61.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2072 24.47% 86.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1153 13.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8379 # Type of FU issued +system.cpu.iq.FU_type_0::total 8466 # Type of FU issued system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021482 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt 182 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021498 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 1.11% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 119 66.11% 67.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 59 32.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 6.04% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 115 63.19% 69.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56 30.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 8539 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 28698 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7660 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 14568 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 10342 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8379 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6956 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 11777 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.711472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.348484 # Number of insts issued each cycle +system.cpu.iq.int_alu_accesses 8628 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 28796 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7745 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 14142 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 10181 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8466 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedOperandsExamined 10938 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 11697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.723775 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.386140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8190 69.54% 69.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 12.19% 81.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 830 7.05% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.53% 93.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 422 3.58% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 239 2.03% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 96 0.82% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 23 0.20% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8148 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1408 12.04% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.98% 88.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 516 4.41% 93.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 394 3.37% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 234 2.00% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 143 1.22% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11777 # Number of insts issued each cycle -system.cpu.iq.rate 0.387773 # Inst issue rate +system.cpu.iq.issued_per_cycle::total 11697 # Number of insts issued each cycle +system.cpu.iq.rate 0.392562 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,100 +415,100 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34392.857143 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.904762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1444500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1446500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34365.168539 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31250.716332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 36 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12234000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.908163 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 356 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 10906500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.890306 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 393 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34391.549296 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31237.822350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 12209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.903308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 10902000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.888041 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 349 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.103152 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.108883 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34368.090452 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 36 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13678500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.917051 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 398 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12219500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.900922 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34396.725441 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13655500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.912644 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 397 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 12217000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.898851 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 185.350735 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005656 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34368.090452 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 185.920349 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34396.725441 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.524297 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 36 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13678500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.917051 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 398 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12219500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.900922 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_hits 38 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13655500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.912644 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 397 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 12217000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.898851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 185.350735 # Cycle average of tags in use -system.cpu.l2cache.total_refs 36 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 185.920349 # Cycle average of tags in use +system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1498 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 13982 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2335 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 13994 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.numCycles 21608 # number of cpu cycles simulated +system.cpu.numCycles 21566 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 4124 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 48 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 7684 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 118 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 30009 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 11406 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 8239 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 2041 # Number of cycles rename is running -system.cpu.rename.SquashCycles 770 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 193 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 4112 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 390 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 29619 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 760 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.skidInsts 508 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 14 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 21018 # The number of ROB reads -system.cpu.rob.rob_writes 21240 # The number of ROB writes -system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 7695 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 122 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 51738 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 11352 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 11162 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 2047 # Number of cycles rename is running +system.cpu.rename.SquashCycles 777 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 186 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 5473 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 51218 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.skidInsts 482 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 20793 # The number of ROB reads +system.cpu.rob.rob_writes 20998 # The number of ROB writes +system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt index 675d2d339..1364619fb 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 742627 # Simulator instruction rate (inst/s) -host_mem_usage 204296 # Number of bytes of host memory used +host_inst_rate 931505 # Simulator instruction rate (inst/s) +host_mem_usage 249344 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 364670846 # Simulator tick rate (ticks/s) +host_tick_rate 451909477 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -66,8 +66,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 5739 # Number of instructions executed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_int_insts 4985 # number of integer instructions -system.cpu.num_int_register_reads 14295 # number of times the integer registers were read -system.cpu.num_int_register_writes 3802 # number of times the integer registers were written +system.cpu.num_int_register_reads 25237 # number of times the integer registers were read +system.cpu.num_int_register_writes 5345 # number of times the integer registers were written system.cpu.num_load_insts 1201 # Number of load instructions system.cpu.num_mem_refs 2139 # number of memory refs system.cpu.num_store_insts 938 # Number of store instructions diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt index 625b66866..e792babc2 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 564396 # Simulator instruction rate (inst/s) -host_mem_usage 212044 # Number of bytes of host memory used +host_inst_rate 534023 # Simulator instruction rate (inst/s) +host_mem_usage 257088 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2575580302 # Simulator tick rate (ticks/s) +host_tick_rate 2428466145 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5682 # Number of instructions simulated sim_seconds 0.000026 # Number of seconds simulated @@ -254,8 +254,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 5682 # Number of instructions executed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_int_insts 4985 # number of integer instructions -system.cpu.num_int_register_reads 15421 # number of times the integer registers were read -system.cpu.num_int_register_writes 3802 # number of times the integer registers were written +system.cpu.num_int_register_reads 28701 # number of times the integer registers were read +system.cpu.num_int_register_writes 5345 # number of times the integer registers were written system.cpu.num_load_insts 1201 # Number of load instructions system.cpu.num_mem_refs 2139 # number of memory refs system.cpu.num_store_insts 938 # Number of store instructions diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 4bee82022..6eff135de 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2974441 # Simulator instruction rate (inst/s) -host_mem_usage 381360 # Number of bytes of host memory used -host_seconds 17.48 # Real time elapsed on the host -host_tick_rate 1507548482 # Simulator tick rate (ticks/s) +host_inst_rate 2945797 # Simulator instruction rate (inst/s) +host_mem_usage 382504 # Number of bytes of host memory used +host_seconds 17.65 # Real time elapsed on the host +host_tick_rate 1493029395 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 51978646 # Number of instructions simulated sim_seconds 0.026345 # Number of seconds simulated @@ -238,8 +238,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 51978646 # Number of instructions executed system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses system.cpu.num_int_insts 42407849 # number of integer instructions -system.cpu.num_int_register_reads 130779000 # number of times the integer registers were read -system.cpu.num_int_register_writes 34467088 # number of times the integer registers were written +system.cpu.num_int_register_reads 222699258 # number of times the integer registers were read +system.cpu.num_int_register_writes 49674551 # number of times the integer registers were written system.cpu.num_load_insts 9176676 # Number of load instructions system.cpu.num_mem_refs 16251075 # number of memory refs system.cpu.num_store_insts 7074399 # Number of store instructions diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5aad94f8d..2a2d9df74 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1535776 # Simulator instruction rate (inst/s) -host_mem_usage 381388 # Number of bytes of host memory used -host_seconds 33.31 # Real time elapsed on the host -host_tick_rate 3431474709 # Simulator tick rate (ticks/s) +host_inst_rate 1455036 # Simulator instruction rate (inst/s) +host_mem_usage 382532 # Number of bytes of host memory used +host_seconds 35.16 # Real time elapsed on the host +host_tick_rate 3251070052 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 51162775 # Number of instructions simulated sim_seconds 0.114317 # Number of seconds simulated @@ -284,8 +284,8 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 51162775 # Number of instructions executed system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses system.cpu.num_int_insts 42435662 # number of integer instructions -system.cpu.num_int_register_reads 139138635 # number of times the integer registers were read -system.cpu.num_int_register_writes 34495190 # number of times the integer registers were written +system.cpu.num_int_register_reads 248572490 # number of times the integer registers were read +system.cpu.num_int_register_writes 49713526 # number of times the integer registers were written system.cpu.num_load_insts 9182978 # Number of load instructions system.cpu.num_mem_refs 16261071 # number of memory refs system.cpu.num_store_insts 7078093 # Number of store instructions |