cpu: TrafficGen as BaseCPU

TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.

Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 37 insertions, 1 deletions

diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index 7fd8b3066..00fe08743 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2016, 2018 ARM Limited
+# Copyright (c) 2012, 2016, 2018, 2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -85,3 +85,39 @@ class BaseTrafficGen(ClockedObject):
     # Sources for Stream/Substream IDs to apply to requests
     sids = VectorParam.Unsigned([], "StreamIDs to use")
     ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
+
+    # These additional parameters allow TrafficGen to be used with scripts
+    # that expect a BaseCPU
+    cpu_id = Param.Int(-1, "CPU identifier")
+    socket_id = Param.Unsigned(0, "Physical Socket identifier")
+    numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def require_caches(cls):
+        return False
+
+    def createThreads(self):
+        pass
+
+    def createInterruptController(self):
+        pass
+
+    def connectCachedPorts(self, bus):
+        if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0):
+            for p in self._cached_ports:
+                exec('self.%s = bus.slave' % p)
+        else:
+            self.port = bus.slave
+
+    def connectAllPorts(self, cached_bus, uncached_bus = None):
+        self.connectCachedPorts(cached_bus)
+
+    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+        self.dcache = dc
+        self.port = dc.cpu_side
+        self._cached_ports = ['dcache.mem_side']
+        self._uncached_ports = []