x86: Stop using and delete the x86 IntDevice class.

Most of its functionality has been exported already. This change makes
the two classes which were inheriting IntDevice create an IntMasterPort
themselves.

Change-Id: I73d17cd79cf8252b0e26dd2576f552bf9054adf4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20825
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

7 files changed, 25 insertions, 99 deletions

diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 392135def..d4ee9f6a6 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -290,16 +290,15 @@ void
 X86ISA::Interrupts::init()
 {
     //
-    // The local apic must register its address ranges on both its pio
-    // port via the basicpiodevice(piodevice) init() function and its
-    // int port that it inherited from IntDevice.  Note IntDevice is
-    // not a SimObject itself.
-    //
+    // The local apic must register its address ranges on its pio
+    // port via the basicpiodevice(piodevice) init() function.
     PioDevice::init();
-    IntDevice::init();
 
-    // the slave port has a range so inform the connected master
+    // The slave port has a range, so inform the connected master.
     intSlavePort.sendRangeChange();
+    // If the master port isn't connected, we can't send interrupts anywhere.
+    panic_if(!intMasterPort.isConnected(),
+            "Int port not connected to anything!");
 }
 
 
@@ -597,7 +596,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
 
 
 X86ISA::Interrupts::Interrupts(Params * p)
-    : PioDevice(p), IntDevice(this, p->int_latency),
+    : PioDevice(p),
       apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
       pendingSmi(false), smiVector(0),
       pendingNmi(false), nmiVector(0),
@@ -607,6 +606,7 @@ X86ISA::Interrupts::Interrupts(Params * p)
       startedUp(false), pendingUnmaskableInt(false),
       pendingIPIs(0), cpu(NULL),
       intSlavePort(name() + ".int_slave", this, this),
+      intMasterPort(name() + ".int_master", this, this, p->int_latency),
       pioDelay(p->pio_latency)
 {
     memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index e48fd4bb3..a6364c8b1 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -72,7 +72,7 @@ namespace X86ISA {
 
 ApicRegIndex decodeAddr(Addr paddr);
 
-class Interrupts : public PioDevice, IntDevice
+class Interrupts : public PioDevice
 {
   protected:
     // Storage for the APIC registers
@@ -171,8 +171,9 @@ class Interrupts : public PioDevice, IntDevice
 
     int initialApicId;
 
-    // Port for receiving interrupts
+    // Ports for interrupts.
     IntSlavePort<Interrupts> intSlavePort;
+    IntMasterPort<Interrupts> intMasterPort;
 
     Tick pioDelay;
     Addr pioAddr = MaxAddr;
@@ -205,7 +206,7 @@ class Interrupts : public PioDevice, IntDevice
     Tick read(PacketPtr pkt) override;
     Tick write(PacketPtr pkt) override;
     Tick recvMessage(PacketPtr pkt);
-    bool recvResponse(PacketPtr pkt) override;
+    bool recvResponse(PacketPtr pkt);
 
     bool
     triggerTimerInterrupt()
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 4071cc8bd..81a9441fb 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -64,6 +64,3 @@ if env['TARGET_ISA'] == 'x86':
     SimObject('I82094AA.py')
     Source('i82094aa.cc')
     DebugFlag('I82094AA')
-
-    Source('intdev.cc')
-    DebugFlag('IntDevice')
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index dfadbd945..5daebe7b6 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -40,8 +40,9 @@
 #include "sim/system.hh"
 
 X86ISA::I82094AA::I82094AA(Params *p)
-    : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
-      extIntPic(p->external_int_pic), lowestPriorityOffset(0)
+    : BasicPioDevice(p, 20), extIntPic(p->external_int_pic),
+      lowestPriorityOffset(0),
+      intMasterPort(name() + ".int_master", this, this, p->int_latency)
 {
     // This assumes there's only one I/O APIC in the system and since the apic
     // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
@@ -66,12 +67,13 @@ X86ISA::I82094AA::I82094AA(Params *p)
 void
 X86ISA::I82094AA::init()
 {
-    // The io apic must register its address ranges on both its pio port
-    // via the piodevice init() function and its int port that it inherited
-    // from IntDevice.  Note IntDevice is not a SimObject itself.
-
+    // The io apic must register its address range with its pio port via
+    // the piodevice init() function.
     BasicPioDevice::init();
-    IntDevice::init();
+
+    // If the master port isn't connected, we can't send interrupts anywhere.
+    panic_if(!intMasterPort.isConnected(),
+            "Int port not connected to anything!");
 }
 
 Port &
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index d9baf111a..b63fc4a68 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -45,7 +45,7 @@ namespace X86ISA
 class I8259;
 class Interrupts;
 
-class I82094AA : public BasicPioDevice, public IntDevice
+class I82094AA : public BasicPioDevice
 {
   public:
     BitUnion64(RedirTableEntry)
@@ -84,6 +84,8 @@ class I82094AA : public BasicPioDevice, public IntDevice
 
     std::vector<IntSinkPin<I82094AA> *> inputs;
 
+    IntMasterPort<I82094AA> intMasterPort;
+
   public:
     typedef I82094AAParams Params;
 
@@ -106,7 +108,7 @@ class I82094AA : public BasicPioDevice, public IntDevice
     Port &getPort(const std::string &if_name,
                   PortID idx=InvalidPortID) override;
 
-    bool recvResponse(PacketPtr pkt) override;
+    bool recvResponse(PacketPtr pkt);
 
     void signalInterrupt(int line);
     void raiseInterruptPin(int number);
diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc
deleted file mode 100644
index fbc2d518c..000000000
--- a/src/dev/x86/intdev.cc
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2008 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "dev/x86/intdev.hh"
-
-void
-X86ISA::IntDevice::init()
-{
-    if (!intMasterPort.isConnected()) {
-        panic("Int port not connected to anything!");
-    }
-}
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 348ec57b8..274873370 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -48,7 +48,6 @@
 #include <string>
 
 #include "arch/x86/intmessage.hh"
-#include "arch/x86/x86_traits.hh"
 #include "mem/tport.hh"
 #include "sim/sim_object.hh"
 
@@ -131,30 +130,6 @@ class IntMasterPort : public QueuedMasterPort
     }
 };
 
-class IntDevice
-{
-  protected:
-
-    IntMasterPort<IntDevice> intMasterPort;
-
-  public:
-    IntDevice(SimObject * parent, Tick latency = 0) :
-        intMasterPort(parent->name() + ".int_master", parent, this, latency)
-    {
-    }
-
-    virtual ~IntDevice()
-    {}
-
-    virtual void init();
-
-    virtual bool
-    recvResponse(PacketPtr pkt)
-    {
-        panic("recvResponse not implemented.\n");
-    }
-};
-
 } // namespace X86ISA
 
 #endif //__DEV_X86_INTDEV_HH__