diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-02-10 21:26:24 -0600 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-02-10 21:26:24 -0600 |
commit | 7862478eef88d58d8da3c43663aa39bd4b604fc5 (patch) | |
tree | 09bf37b44cb164d03415e64b4d4c52cbccbd194a | |
parent | d3aebe1f91aa166329c8ee102fdcb2c9734fdceb (diff) | |
download | gem5-7862478eef88d58d8da3c43663aa39bd4b604fc5.tar.xz |
ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.
-rw-r--r-- | src/base/SConscript | 1 | ||||
-rw-r--r-- | src/base/types.cc | 43 | ||||
-rw-r--r-- | src/base/types.hh | 3 | ||||
-rw-r--r-- | src/mem/ruby/buffers/MessageBufferNode.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet/flexible-pipeline/flit.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/Message.hh | 21 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/NetworkMessage.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/RubyRequest.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/system/MemoryNode.hh | 1 | ||||
-rw-r--r-- | src/mem/slicc/symbols/Type.py | 4 |
11 files changed, 66 insertions, 17 deletions
diff --git a/src/base/SConscript b/src/base/SConscript index ff6d696d4..2bd255162 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -59,6 +59,7 @@ Source('statistics.cc') Source('str.cc') Source('time.cc') Source('trace.cc') +Source('types.cc') Source('userinfo.cc') Source('loader/aout_object.cc') diff --git a/src/base/types.cc b/src/base/types.cc new file mode 100644 index 000000000..38b6bf2b2 --- /dev/null +++ b/src/base/types.cc @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2013 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nilay Vaish + */ + +#include "base/types.hh" + +#ifndef SWIG // keep the operators away from SWIG + +std::ostream& +operator<<(std::ostream &out, const Cycles & cycles) +{ + out << cycles.c; + return out; +} + +#endif // SWIG not touching operators + diff --git a/src/base/types.hh b/src/base/types.hh index b4cb69a0c..ad9ac766e 100644 --- a/src/base/types.hh +++ b/src/base/types.hh @@ -40,6 +40,7 @@ #include <inttypes.h> #include <cassert> +#include <ostream> /** uint64_t constant */ #define ULL(N) ((uint64_t)N##ULL) @@ -125,6 +126,8 @@ class Cycles const Cycles operator >>(const int32_t shift) { return Cycles(c >> shift); } + friend std::ostream& operator<<(std::ostream &out, const Cycles & cycles); + #endif // SWIG not touching operators }; diff --git a/src/mem/ruby/buffers/MessageBufferNode.hh b/src/mem/ruby/buffers/MessageBufferNode.hh index 57f09a913..11485a3b9 100644 --- a/src/mem/ruby/buffers/MessageBufferNode.hh +++ b/src/mem/ruby/buffers/MessageBufferNode.hh @@ -49,7 +49,7 @@ class MessageBufferNode public: Cycles m_time; - uint64 m_msg_counter; // FIXME, should this be a 64-bit value? + uint64_t m_msg_counter; // FIXME, should this be a 64-bit value? MsgPtr m_msgptr; }; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh index 549dd59d5..9dd4af10e 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh @@ -34,6 +34,7 @@ #include <cassert> #include <iostream> +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/garnet/NetworkHeader.hh" #include "mem/ruby/slicc_interface/Message.hh" diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh index 9e1168409..4e5b2fb8b 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh @@ -31,6 +31,7 @@ #include <cassert> #include <iostream> +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/garnet/NetworkHeader.hh" #include "mem/ruby/slicc_interface/Message.hh" diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index 74b405312..c99d66f5c 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -32,7 +32,6 @@ #include <iostream> #include "base/refcnt.hh" -#include "mem/ruby/common/TypeDefines.hh" #include "mem/packet.hh" class Message; @@ -41,7 +40,7 @@ typedef RefCountingPtr<Message> MsgPtr; class Message : public RefCounted { public: - Message(Time curTime) + Message(Cycles curTime) : m_time(curTime), m_LastEnqueueTime(curTime), m_DelayedCycles(0) @@ -72,19 +71,19 @@ class Message : public RefCounted virtual bool functionalWrite(Packet *pkt) = 0; //{ fatal("Write functional access not implemented!"); } - void setDelayedCycles(const Time cycles) { m_DelayedCycles = cycles; } - const Time getDelayedCycles() const {return m_DelayedCycles;} + void setDelayedCycles(const Cycles cycles) { m_DelayedCycles = cycles; } + const Cycles getDelayedCycles() const {return m_DelayedCycles;} - void setLastEnqueueTime(const Time& time) { m_LastEnqueueTime = time; } - const Time getLastEnqueueTime() const {return m_LastEnqueueTime;} + void setLastEnqueueTime(const Cycles& time) { m_LastEnqueueTime = time; } + const Cycles getLastEnqueueTime() const {return m_LastEnqueueTime;} - const Time& getTime() const { return m_time; } - void setTime(const Time& new_time) { m_time = new_time; } + const Cycles& getTime() const { return m_time; } + void setTime(const Cycles& new_time) { m_time = new_time; } private: - Time m_time; - Time m_LastEnqueueTime; // my last enqueue time - int m_DelayedCycles; // my delayed cycles + Cycles m_time; + Cycles m_LastEnqueueTime; // my last enqueue time + Cycles m_DelayedCycles; // my delayed cycles }; inline std::ostream& diff --git a/src/mem/ruby/slicc_interface/NetworkMessage.hh b/src/mem/ruby/slicc_interface/NetworkMessage.hh index e26612e0f..4d2968f41 100644 --- a/src/mem/ruby/slicc_interface/NetworkMessage.hh +++ b/src/mem/ruby/slicc_interface/NetworkMessage.hh @@ -42,7 +42,7 @@ typedef RefCountingPtr<NetworkMessage> NetMsgPtr; class NetworkMessage : public Message { public: - NetworkMessage(Time curTime) + NetworkMessage(Cycles curTime) : Message(curTime), m_internal_dest_valid(false) { } diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh index 37b89dc8f..654656132 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.hh +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh @@ -51,7 +51,7 @@ class RubyRequest : public Message PacketPtr pkt; unsigned m_contextId; - RubyRequest(Time curTime, uint64_t _paddr, uint8_t* _data, int _len, + RubyRequest(Cycles curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, unsigned _proc_id = 100) @@ -70,7 +70,7 @@ class RubyRequest : public Message m_LineAddress.makeLineAddress(); } - RubyRequest(Time curTime) : Message(curTime) + RubyRequest(Cycles curTime) : Message(curTime) { } diff --git a/src/mem/ruby/system/MemoryNode.hh b/src/mem/ruby/system/MemoryNode.hh index 10648b715..5bf988935 100644 --- a/src/mem/ruby/system/MemoryNode.hh +++ b/src/mem/ruby/system/MemoryNode.hh @@ -42,6 +42,7 @@ #include "mem/protocol/MemoryRequestType.hh" #include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/slicc_interface/Message.hh" class MemoryNode diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index ee1b8102a..f40036e8e 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -246,7 +246,7 @@ $klass ${{self.c_ident}}$parent ''', klass="class") if self.isMessage: - code('(Time curTime) : %s(curTime) {' % self["interface"]) + code('(Cycles curTime) : %s(curTime) {' % self["interface"]) else: code('()\n\t\t{') @@ -291,7 +291,7 @@ $klass ${{self.c_ident}}$parent params = ', '.join(params) if self.isMessage: - params = "const Time curTime, " + params + params = "const Cycles curTime, " + params code('${{self.c_ident}}($params)') |