diff options
| author | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2020-01-13 10:47:55 +0100 |
|---|---|---|
| committer | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2020-01-20 14:04:11 +0000 |
| commit | 7ac4607385f8490b2a12acaef73f2f31583160f0 (patch) | |
| tree | 2e87b310965ee93fc00e5b3275832d87d5b15cf5 | |
| parent | af02aa6a0dc89f22dd0d3b37c3fcc63c61d91417 (diff) | |
| download | gem5-7ac4607385f8490b2a12acaef73f2f31583160f0.tar.xz | |
arch-arm: Fix EL2 target exception level for SP alignment fault.
This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.
Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/faults.cc | 8 | ||||
| -rw-r--r-- | src/arch/arm/faults.hh | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 5a7b8e8ea..bd38fdccb 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1541,6 +1541,14 @@ PCAlignmentFault::routeToHyp(ThreadContext *tc) const SPAlignmentFault::SPAlignmentFault() {} +bool +SPAlignmentFault::routeToHyp(ThreadContext *tc) const +{ + assert(from64); + HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); + return EL2Enabled(tc) && hcr.tge==1; +} + SystemError::SystemError() {} diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 3f61bc722..508fd034e 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -571,6 +571,7 @@ class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> { public: SPAlignmentFault(); + bool routeToHyp(ThreadContext *tc) const override; }; /// System error (AArch64 only) |