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| author | Gabe Black <gabeblack@google.com> | 2020-01-09 01:00:55 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2020-01-14 02:19:19 +0000 |
| commit | 8a3ba27dfe5e5b716b9b35e0ef62c40d5b5cc223 (patch) | |
| tree | a22d1770e87c7ae32f800a45599bf7c5ced4b594 | |
| parent | 2012a0c6519a7198e7158f9bc07b97b98fdd357a (diff) | |
| download | gem5-8a3ba27dfe5e5b716b9b35e0ef62c40d5b5cc223.tar.xz | |
x86: Move local APIC initialization out of initCPU.
The APIC can (and probably should) set its version register on its
own. Also it already configures its CPUID register when associated
with a CPU and doesn't need initCPU to do that.
Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24186
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
| -rw-r--r-- | src/arch/x86/interrupts.cc | 2 | ||||
| -rw-r--r-- | src/arch/x86/utility.cc | 8 |
2 files changed, 2 insertions, 8 deletions
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 06bf41bd1..b447216d9 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -614,6 +614,8 @@ X86ISA::Interrupts::Interrupts(Params * p) regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); ISRV = 0; IRRV = 0; + + regs[APIC_VERSION] = (5 << 16) | 0x14; } diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 13019e90e..b00e6867f 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -84,14 +84,6 @@ initCPU(ThreadContext *tc, int cpuId) // passed. No BIST actually runs, but software may still check this // register for errors. tc->setIntReg(INTREG_RAX, 0); - - Interrupts * interrupts = dynamic_cast<Interrupts *>( - tc->getCpuPtr()->getInterruptController(0)); - assert(interrupts); - - interrupts->setRegNoEffect(APIC_ID, cpuId << 24); - - interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); } void startupCPU(ThreadContext *tc, int cpuId) |