dev-arm: Cleanup GICv3 initialization

This patch is removing the unnecessary initState() / reset() methods
from GICv3 classes, since we can initialize everything at
construction/init time

Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

8 files changed, 71 insertions, 114 deletions

diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 6f4312b03..eb38efe4d 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2018 Metempsy Technology Consulting
  * All rights reserved.
  *
@@ -84,17 +96,6 @@ Gicv3::init()
     BaseGic::init();
 }
 
-void
-Gicv3::initState()
-{
-    distributor->initState();
-
-    for (int i = 0; i < sys->numContexts(); i++) {
-        redistributors[i]->initState();
-        cpuInterfaces[i]->initState();
-    }
-}
-
 Tick
 Gicv3::read(PacketPtr pkt)
 {
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 7dab5a2fb..89a8abec0 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2018 Metempsy Technology Consulting
  * All rights reserved.
  *
@@ -99,7 +111,6 @@ class Gicv3 : public BaseGic
     }
 
     void init() override;
-    void initState() override;
 
     const Params *
     params() const
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index d7988e13d..73257a718 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -58,6 +58,8 @@ Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
       distributor(nullptr),
       cpuId(cpu_id)
 {
+    hppi.prio = 0xff;
+    hppi.intid = Gicv3::INTID_SPURIOUS;
 }
 
 void
@@ -68,18 +70,6 @@ Gicv3CPUInterface::init()
 }
 
 void
-Gicv3CPUInterface::initState()
-{
-    reset();
-}
-
-void
-Gicv3CPUInterface::reset()
-{
-    hppi.prio = 0xff;
-}
-
-void
 Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
 {
     maintenanceInterrupt = gic->params()->maint_int->get(tc);
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index 9e1c9a09f..c88e1f635 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -322,7 +322,6 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     bool isEOISplitMode() const;
     bool isSecureBelowEL3() const;
     ICH_MISR_EL2 maintenanceInterruptStatus() const;
-    void reset();
     void serialize(CheckpointOut & cp) const override;
     void unserialize(CheckpointIn & cp) override;
     void update();
@@ -345,7 +344,6 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
 
     void init();
-    void initState();
 
   public: // BaseISADevice
     RegVal readMiscReg(int misc_reg) override;
diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 4f80d0297..fd43326c1 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -69,15 +69,19 @@ const AddrRange Gicv3Distributor::GICD_IROUTER   (0x6000, 0x7fe0);
 Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)
     : gic(gic),
       itLines(it_lines),
-      irqGroup(it_lines),
-      irqEnabled(it_lines),
-      irqPending(it_lines),
-      irqActive(it_lines),
-      irqPriority(it_lines),
-      irqConfig(it_lines),
-      irqGrpmod(it_lines),
-      irqNsacr(it_lines),
-      irqAffinityRouting(it_lines),
+      ARE(true),
+      EnableGrp1S(0),
+      EnableGrp1NS(0),
+      EnableGrp0(0),
+      irqGroup(it_lines, 0),
+      irqEnabled(it_lines, false),
+      irqPending(it_lines, false),
+      irqActive(it_lines, false),
+      irqPriority(it_lines, 0xAA),
+      irqConfig(it_lines, Gicv3::INT_LEVEL_SENSITIVE),
+      irqGrpmod(it_lines, 0),
+      irqNsacr(it_lines, 0),
+      irqAffinityRouting(it_lines, 0),
       gicdTyper(0),
       gicdPidr0(0x92),
       gicdPidr1(0xb4),
@@ -117,48 +121,17 @@ Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)
         (1 << 17) | (1 << 16) |
         ((gic->getSystem()->haveSecurity() ? 1 : 0) << 10) |
         (it_lines_number << 0);
-}
-
-void
-Gicv3Distributor::init()
-{
-}
-
-void
-Gicv3Distributor::initState()
-{
-    reset();
-}
-
-void
-Gicv3Distributor::reset()
-{
-    std::fill(irqGroup.begin(), irqGroup.end(), 0);
-    // Imp. defined reset value
-    std::fill(irqEnabled.begin(), irqEnabled.end(), false);
-    std::fill(irqPending.begin(), irqPending.end(), false);
-    std::fill(irqActive.begin(), irqActive.end(), false);
-    // Imp. defined reset value
-    std::fill(irqPriority.begin(), irqPriority.end(), 0xAAAAAAAA);
-    std::fill(irqConfig.begin(), irqConfig.end(),
-              Gicv3::INT_LEVEL_SENSITIVE); // Imp. defined reset value
-    std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0);
-    std::fill(irqNsacr.begin(), irqNsacr.end(), 0);
-    /*
-     * For our implementation affinity routing is always enabled,
-     * no GICv2 legacy
-     */
-    ARE = true;
 
     if (gic->getSystem()->haveSecurity()) {
         DS = false;
     } else {
         DS = true;
     }
+}
 
-    EnableGrp0 = 0;
-    EnableGrp1NS = 0;
-    EnableGrp1S = 0;
+void
+Gicv3Distributor::init()
+{
 }
 
 uint64_t
diff --git a/src/dev/arm/gic_v3_distributor.hh b/src/dev/arm/gic_v3_distributor.hh
index 01201fd47..28b2e3218 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -229,7 +229,6 @@ class Gicv3Distributor : public Serializable
         return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
     }
 
-    void reset();
     void serialize(CheckpointOut & cp) const override;
     void unserialize(CheckpointIn & cp) override;
     void update();
@@ -242,7 +241,6 @@ class Gicv3Distributor : public Serializable
     void deassertSPI(uint32_t int_id);
     void clearIrqCpuInterface(uint32_t int_id);
     void init();
-    void initState();
     uint64_t read(Addr addr, size_t size, bool is_secure_access);
     void sendInt(uint32_t int_id);
     void write(Addr addr, uint64_t data, size_t size,
diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index e22ea7080..8b6233c22 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -57,14 +57,22 @@ Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
       cpuInterface(nullptr),
       cpuId(cpu_id),
       memProxy(nullptr),
-      irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
-      irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
+      peInLowPowerState(true),
+      irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
+      irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
+      irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
+      irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
+      irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
+      irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX, Gicv3::INT_EDGE_TRIGGERED),
+      irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
+      irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
+      DPG1S(false),
+      DPG1NS(false),
+      DPG0(false),
+      EnableLPIs(false),
+      lpiConfigurationTablePtr(0),
+      lpiIDBits(0),
+      lpiPendingTablePtr(0),
       addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000)
 {
 }
@@ -78,38 +86,6 @@ Gicv3Redistributor::init()
     memProxy = &gic->getSystem()->physProxy;
 }
 
-void
-Gicv3Redistributor::initState()
-{
-    reset();
-}
-
-void
-Gicv3Redistributor::reset()
-{
-    peInLowPowerState = true;
-    std::fill(irqGroup.begin(), irqGroup.end(), 0);
-    std::fill(irqEnabled.begin(), irqEnabled.end(), false);
-    std::fill(irqPending.begin(), irqPending.end(), false);
-    std::fill(irqActive.begin(), irqActive.end(), false);
-    std::fill(irqPriority.begin(), irqPriority.end(), 0);
-
-    // SGIs have edge-triggered behavior
-    for (uint32_t int_id = 0; int_id < Gicv3::SGI_MAX; int_id++) {
-        irqConfig[int_id] = Gicv3::INT_EDGE_TRIGGERED;
-    }
-
-    std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0);
-    std::fill(irqNsacr.begin(), irqNsacr.end(), 0);
-    DPG1S = false;
-    DPG1NS = false;
-    DPG0 = false;
-    EnableLPIs = false;
-    lpiConfigurationTablePtr = 0;
-    lpiIDBits = 0;
-    lpiPendingTablePtr = 0;
-}
-
 uint64_t
 Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
 {
diff --git a/src/dev/arm/gic_v3_redistributor.hh b/src/dev/arm/gic_v3_redistributor.hh
index c59c3411f..170bdf63d 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2018 Metempsy Technology Consulting
  * All rights reserved.
  *
@@ -205,7 +217,6 @@ class Gicv3Redistributor : public Serializable
     void writeEntryLPI(uint32_t intid, uint8_t lpi_entry);
     bool isPendingLPI(uint32_t intid);
     void setClrLPI(uint64_t data, bool set);
-    void reset();
     void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
     void serialize(CheckpointOut & cp) const override;
     void unserialize(CheckpointIn & cp) override;
@@ -217,7 +228,6 @@ class Gicv3Redistributor : public Serializable
     Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
     uint32_t getAffinity() const;
     void init();
-    void initState();
     uint64_t read(Addr addr, size_t size, bool is_secure_access);
     void sendPPInt(uint32_t int_id);
     void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);