mem-cache: Move Target to QueueEntry

WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.

Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 files changed, 41 insertions, 29 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 19655a57e..f43c2ecf3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -439,7 +439,7 @@ BaseCache::recvTimingResp(PacketPtr pkt)
     }
 
     // Initial target is used just for stats
-    MSHR::Target *initial_tgt = mshr->getTarget();
+    QueueEntry::Target *initial_tgt = mshr->getTarget();
     int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
     Tick miss_latency = curTick() - initial_tgt->recvTime;
 
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 938b6f4e9..eac278a3b 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -687,7 +687,7 @@ Cache::recvAtomic(PacketPtr pkt)
 void
 Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)
 {
-    MSHR::Target *initial_tgt = mshr->getTarget();
+    QueueEntry::Target *initial_tgt = mshr->getTarget();
     // First offset for critical word first calculations
     const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
 
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index b94dfb9c5..e9505ebdc 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -124,7 +124,7 @@ class MSHR : public QueueEntry, public Printable
     /** True if the entry is just a simple forward from an upper level */
     bool isForward;
 
-    class Target {
+    class Target : public QueueEntry::Target {
       public:
 
         enum Source {
@@ -133,10 +133,6 @@ class MSHR : public QueueEntry, public Printable
             FromPrefetcher
         };
 
-        const Tick recvTime;  //!< Time when request was received (for stats)
-        const Tick readyTime; //!< Time when request is ready to be serviced
-        const Counter order;  //!< Global order (for memory consistency mgmt)
-        const PacketPtr pkt;  //!< Pending request packet.
         const Source source;  //!< Request from cpu, memory, or prefetcher?
 
         /**
@@ -161,9 +157,8 @@ class MSHR : public QueueEntry, public Printable
 
         Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
                Source _source, bool _markedPending, bool alloc_on_fill)
-            : recvTime(curTick()), readyTime(_readyTime), order(_order),
-              pkt(_pkt), source(_source), markedPending(_markedPending),
-              allocOnFill(alloc_on_fill)
+            : QueueEntry::Target(_pkt, _readyTime, _order), source(_source),
+              markedPending(_markedPending), allocOnFill(alloc_on_fill)
         {}
     };
 
@@ -476,7 +471,7 @@ class MSHR : public QueueEntry, public Printable
      * Returns a reference to the first target.
      * @return A pointer to the first target.
      */
-    Target *getTarget()
+    QueueEntry::Target *getTarget() override
     {
         assert(hasTargets());
         return &targets.front();
diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 08cfdd654..9a2a1db9d 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -245,9 +245,8 @@ void
 NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
                                      CacheBlk *blk)
 {
-    MSHR::Target *initial_tgt = mshr->getTarget();
     // First offset for critical word first calculations
-    const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
+    const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
 
     MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
     for (auto &target: targets) {
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 7ab9e4f29..39ee0a0b9 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -76,6 +76,33 @@ class QueueEntry : public Packet::SenderState
     bool _isUncacheable;
 
   public:
+    /**
+     * A queue entry is holding packets that will be serviced as soon as
+     * resources are available. Since multiple references to the same
+     * address can arrive while a packet is not serviced, each packet is
+     * stored in a target containing its availability, order and other info,
+     * and the queue entry stores these similar targets in a list.
+     */
+    class Target {
+      public:
+        const Tick recvTime;  //!< Time when request was received (for stats)
+        const Tick readyTime; //!< Time when request is ready to be serviced
+        const Counter order;  //!< Global order (for memory consistency mgmt)
+        const PacketPtr pkt;  //!< Pending request packet.
+
+        /**
+         * Default constructor. Assigns the current tick as the arrival time
+         * of the packet.
+         *
+         * @param _pkt The pending request packet.
+         * @param ready_time The tick at which the packet will be serviceable.
+         * @param _order Global order.
+         */
+        Target(PacketPtr _pkt, Tick ready_time, Counter _order)
+            : recvTime(curTick()), readyTime(ready_time), order(_order),
+              pkt(_pkt)
+        {}
+    };
 
     /** True if the entry has been sent downstream. */
     bool inService;
@@ -105,6 +132,12 @@ class QueueEntry : public Packet::SenderState
      */
     virtual bool sendPacket(BaseCache &cache) = 0;
 
+    /**
+     * Returns a pointer to the first target.
+     *
+     * @return A pointer to the first target.
+     */
+    virtual Target* getTarget() = 0;
 };
 
 #endif // __MEM_CACHE_QUEUE_ENTRY_HH__
diff --git a/src/mem/cache/write_queue_entry.hh b/src/mem/cache/write_queue_entry.hh
index f4ccb1a8c..59714d948 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -76,21 +76,6 @@ class WriteQueueEntry : public QueueEntry, public Printable
     friend class WriteQueue;
 
   public:
-
-    class Target {
-      public:
-
-        const Tick recvTime;  //!< Time when request was received (for stats)
-        const Tick readyTime; //!< Time when request is ready to be serviced
-        const Counter order;  //!< Global order (for memory consistency mgmt)
-        const PacketPtr pkt;  //!< Pending request packet.
-
-        Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
-            : recvTime(curTick()), readyTime(_readyTime), order(_order),
-              pkt(_pkt)
-        {}
-    };
-
     class TargetList : public std::list<Target> {
 
       public:
@@ -165,7 +150,7 @@ class WriteQueueEntry : public QueueEntry, public Printable
      * Returns a reference to the first target.
      * @return A pointer to the first target.
      */
-    Target *getTarget()
+    Target *getTarget() override
     {
         assert(hasTargets());
         return &targets.front();