mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

108 files changed, 98 insertions, 94 deletions

diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh
index 0e842bd3f..64b7ea7f4 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.hh
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh
@@ -37,7 +37,7 @@
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
-#include "mem/protocol/InvalidateGeneratorStatus.hh"
+#include "mem/ruby/protocol/InvalidateGeneratorStatus.hh"
 #include "params/InvalidateGenerator.hh"
 
 class InvalidateGenerator : public DirectedGenerator
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 8c64a3dd0..77688b6f8 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -37,7 +37,7 @@
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
-#include "mem/protocol/SeriesRequestGeneratorStatus.hh"
+#include "mem/ruby/protocol/SeriesRequestGeneratorStatus.hh"
 #include "params/SeriesRequestGenerator.hh"
 
 class SeriesRequestGenerator : public DirectedGenerator
diff --git a/src/cpu/testers/rubytest/Check.hh b/src/cpu/testers/rubytest/Check.hh
index f7922d71f..1a3317485 100644
--- a/src/cpu/testers/rubytest/Check.hh
+++ b/src/cpu/testers/rubytest/Check.hh
@@ -33,9 +33,9 @@
 #include <iostream>
 
 #include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/TesterStatus.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/TesterStatus.hh"
 
 class SubBlock;
 
diff --git a/src/learning_gem5/part3/MSI-cache.sm b/src/learning_gem5/part3/MSI-cache.sm
index 3847b53a8..0d5a20592 100644
--- a/src/learning_gem5/part3/MSI-cache.sm
+++ b/src/learning_gem5/part3/MSI-cache.sm
@@ -482,7 +482,7 @@ machine(MachineType:L1Cache, "MSI cache")
             // across different directories, so query the network.
             out_msg.Destination.add(mapAddressToMachine(address,
                                     MachineType:Directory));
-            // See mem/protocol/RubySlicc_Exports.sm for possible sizes.
+            // See mem/ruby/protocol/RubySlicc_Exports.sm for possible sizes.
             out_msg.MessageSize := MessageSizeType:Control;
             // Set that the reqeustor is this machine so we get the response.
             out_msg.Requestor := machineID;
diff --git a/src/learning_gem5/part3/SConsopts b/src/learning_gem5/part3/SConsopts
index c8573d3ac..6525d4ed3 100644
--- a/src/learning_gem5/part3/SConsopts
+++ b/src/learning_gem5/part3/SConsopts
@@ -1,6 +1,6 @@
 Import('*')
 
-# NOTE: All SLICC setup code found in src/mem/protocol/SConscript
+# NOTE: All SLICC setup code found in src/mem/ruby/protocol/SConscript
 
 # Register this protocol with gem5/SCons
 all_protocols.extend([
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index be52c02d0..22dd973c3 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -98,7 +98,7 @@ def do_embed_text(target, source, env):
 #
 # Link includes
 #
-generated_dir = Dir('../protocol')
+generated_dir = Dir('protocol')
 
 def MakeIncludeAction(target, source, env):
     f = file(str(target[0]), 'w')
@@ -138,9 +138,9 @@ MakeInclude('structures/WireBuffer.hh')
 MakeInclude('system/DMASequencer.hh')
 MakeInclude('system/Sequencer.hh')
 
-# External types : Group "mem/protocol" : include "header.hh" to the bottom
-# of this MakeIncludes if it is referenced as
-# <# include "mem/protocol/header.hh"> in any file
-# generated_dir = Dir('../protocol')
+# External types : Group "mem/ruby/protocol" : include "header.hh" to the
+# bottom of this MakeIncludes if it is referenced as
+# <# include "mem/ruby/protocol/header.hh"> in any file
+# generated_dir = Dir('protocol')
 MakeInclude('system/GPUCoalescer.hh')
 MakeInclude('system/VIPERCoalescer.hh')
diff --git a/src/mem/ruby/common/MachineID.hh b/src/mem/ruby/common/MachineID.hh
index 8fe8f80d9..64082d79c 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -33,7 +33,7 @@
 #include <string>
 
 #include "base/cprintf.hh"
-#include "mem/protocol/MachineType.hh"
+#include "mem/ruby/protocol/MachineType.hh"
 
 struct MachineID
 {
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 0830187c8..606e6704b 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -61,12 +61,12 @@
 #include "base/types.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
-#include "mem/protocol/LinkDirection.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/Topology.hh"
 #include "mem/ruby/network/dummy_port.hh"
+#include "mem/ruby/protocol/LinkDirection.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 #include "params/RubyNetwork.hh"
 #include "sim/clocked_object.hh"
 
diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh
index 71faf4182..ef8104ad5 100644
--- a/src/mem/ruby/network/Topology.hh
+++ b/src/mem/ruby/network/Topology.hh
@@ -44,9 +44,9 @@
 #include <string>
 #include <vector>
 
-#include "mem/protocol/LinkDirection.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/protocol/LinkDirection.hh"
 
 class NetDest;
 class Network;
diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh
index dbb1bbd05..b481ed53e 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -43,9 +43,9 @@
 #include <vector>
 
 #include "mem/packet.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/BasicRouter.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 #include "params/Switch.hh"
 
 class MessageBuffer;
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index 3e9d54499..0d6f71e39 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -31,10 +31,10 @@
 
 #include <iostream>
 
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Set.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class Histogram;
 
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 087b77474..acdc86023 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -31,8 +31,8 @@
 #include <vector>
 
 #include "base/stl_helpers.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 using namespace std;
 typedef AddressProfiler::AddressMap AddressMap;
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 9f12415c5..14d015c82 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -32,12 +32,12 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/AccessType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Histogram.hh"
 #include "mem/ruby/profiler/AccessTraceForAddress.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/AccessType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 class Set;
 
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 900714e5d..505e3a17d 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -52,10 +52,10 @@
 
 #include "base/stl_helpers.hh"
 #include "base/str.hh"
-#include "mem/protocol/MachineType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/profiler/AddressProfiler.hh"
+#include "mem/ruby/protocol/MachineType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 /**
  * the profiler uses GPUCoalescer code even
@@ -72,6 +72,7 @@
  */
 #ifdef BUILD_GPU
 #include "mem/ruby/system/GPUCoalescer.hh"
+
 #endif
 
 #include "mem/ruby/system/Sequencer.hh"
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 6ad65f962..5632b8490 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -51,11 +51,11 @@
 
 #include "base/callback.hh"
 #include "base/statistics.hh"
-#include "mem/protocol/AccessType.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/MachineID.hh"
+#include "mem/ruby/protocol/AccessType.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 #include "params/RubySystem.hh"
 
 class RubyRequest;
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/ruby/protocol/GPU_RfO-SQC.sm
index c28642661..c28642661 100644
--- a/src/mem/protocol/GPU_RfO-SQC.sm
+++ b/src/mem/ruby/protocol/GPU_RfO-SQC.sm
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/ruby/protocol/GPU_RfO-TCC.sm
index ca110e5ff..ca110e5ff 100644
--- a/src/mem/protocol/GPU_RfO-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_RfO-TCC.sm
diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
index a524381f4..a524381f4 100644
--- a/src/mem/protocol/GPU_RfO-TCCdir.sm
+++ b/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/ruby/protocol/GPU_RfO-TCP.sm
index 0c83f5502..0c83f5502 100644
--- a/src/mem/protocol/GPU_RfO-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_RfO-TCP.sm
diff --git a/src/mem/protocol/GPU_RfO.slicc b/src/mem/ruby/protocol/GPU_RfO.slicc
index 7773ce6e0..7773ce6e0 100644
--- a/src/mem/protocol/GPU_RfO.slicc
+++ b/src/mem/ruby/protocol/GPU_RfO.slicc
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
index 1885a68f7..1885a68f7 100644
--- a/src/mem/protocol/GPU_VIPER-SQC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index f8da4abf1..f8da4abf1 100644
--- a/src/mem/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 9dffe0f2c..9dffe0f2c 100644
--- a/src/mem/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
diff --git a/src/mem/protocol/GPU_VIPER.slicc b/src/mem/ruby/protocol/GPU_VIPER.slicc
index 45f7f3477..45f7f3477 100644
--- a/src/mem/protocol/GPU_VIPER.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER.slicc
diff --git a/src/mem/protocol/GPU_VIPER_Baseline.slicc b/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
index 49bdce38c..49bdce38c 100644
--- a/src/mem/protocol/GPU_VIPER_Baseline.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
index 04d7b7a6f..04d7b7a6f 100644
--- a/src/mem/protocol/GPU_VIPER_Region-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
diff --git a/src/mem/protocol/GPU_VIPER_Region.slicc b/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
index cbfef9de3..cbfef9de3 100644
--- a/src/mem/protocol/GPU_VIPER_Region.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
diff --git a/src/mem/protocol/Garnet_standalone-cache.sm b/src/mem/ruby/protocol/Garnet_standalone-cache.sm
index a34c7676d..a34c7676d 100644
--- a/src/mem/protocol/Garnet_standalone-cache.sm
+++ b/src/mem/ruby/protocol/Garnet_standalone-cache.sm
diff --git a/src/mem/protocol/Garnet_standalone-dir.sm b/src/mem/ruby/protocol/Garnet_standalone-dir.sm
index 3a4327972..3a4327972 100644
--- a/src/mem/protocol/Garnet_standalone-dir.sm
+++ b/src/mem/ruby/protocol/Garnet_standalone-dir.sm
diff --git a/src/mem/protocol/Garnet_standalone-msg.sm b/src/mem/ruby/protocol/Garnet_standalone-msg.sm
index 2232e0ff0..2232e0ff0 100644
--- a/src/mem/protocol/Garnet_standalone-msg.sm
+++ b/src/mem/ruby/protocol/Garnet_standalone-msg.sm
diff --git a/src/mem/protocol/Garnet_standalone.slicc b/src/mem/ruby/protocol/Garnet_standalone.slicc
index e467f34c1..e467f34c1 100644
--- a/src/mem/protocol/Garnet_standalone.slicc
+++ b/src/mem/ruby/protocol/Garnet_standalone.slicc
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 84bb0d868..84bb0d868 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index 6db35ceeb..6db35ceeb 100644
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
index 2a5ecc8e8..2a5ecc8e8 100644
--- a/src/mem/protocol/MESI_Three_Level-msg.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
diff --git a/src/mem/protocol/MESI_Three_Level.slicc b/src/mem/ruby/protocol/MESI_Three_Level.slicc
index a24b11c18..a24b11c18 100644
--- a/src/mem/protocol/MESI_Three_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Three_Level.slicc
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 51d3f621c..51d3f621c 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
index 5a8cfae6d..5a8cfae6d 100644
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
index 991de5a2c..991de5a2c 100644
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
index 5d0b8857f..5d0b8857f 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
index 738019e7b..738019e7b 100644
--- a/src/mem/protocol/MESI_Two_Level-msg.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
diff --git a/src/mem/protocol/MESI_Two_Level.slicc b/src/mem/ruby/protocol/MESI_Two_Level.slicc
index b5bf104df..b5bf104df 100644
--- a/src/mem/protocol/MESI_Two_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Two_Level.slicc
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/ruby/protocol/MI_example-cache.sm
index 8738f336e..8738f336e 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/ruby/protocol/MI_example-cache.sm
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/ruby/protocol/MI_example-dir.sm
index e9f652152..e9f652152 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/ruby/protocol/MI_example-dir.sm
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/ruby/protocol/MI_example-dma.sm
index 85d0b7f7d..85d0b7f7d 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/ruby/protocol/MI_example-dma.sm
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/ruby/protocol/MI_example-msg.sm
index 95d6ef18e..95d6ef18e 100644
--- a/src/mem/protocol/MI_example-msg.sm
+++ b/src/mem/ruby/protocol/MI_example-msg.sm
diff --git a/src/mem/protocol/MI_example.slicc b/src/mem/ruby/protocol/MI_example.slicc
index 70614787a..70614787a 100644
--- a/src/mem/protocol/MI_example.slicc
+++ b/src/mem/ruby/protocol/MI_example.slicc
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
index 140bbc400..140bbc400 100644
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
index 620e9ed72..620e9ed72 100644
--- a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
index 5c08c6bd7..5c08c6bd7 100644
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
index cc5ceb0b5..cc5ceb0b5 100644
--- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
index 53b946c6d..53b946c6d 100644
--- a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
index 0ec87f0c1..0ec87f0c1 100644
--- a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
index f0bb31cb7..f0bb31cb7 100644
--- a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 4cde5ad03..4cde5ad03 100644
--- a/src/mem/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-msg.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
index a66939c2b..a66939c2b 100644
--- a/src/mem/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
index d23094a2e..d23094a2e 100644
--- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base.slicc b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
index b38145246..b38145246 100644
--- a/src/mem/protocol/MOESI_AMD_Base.slicc
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index b8d8ab4a0..b8d8ab4a0 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index faea79fec..faea79fec 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index f12d16658..f12d16658 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
index a3a9f63ac..a3a9f63ac 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
index 7dc582215..7dc582215 100644
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory.slicc b/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
index 215a8016f..215a8016f 100644
--- a/src/mem/protocol/MOESI_CMP_directory.slicc
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
index db06fb591..db06fb591 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
index 7911179c2..7911179c2 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
index b9b65b585..b9b65b585 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
index e48b871f2..e48b871f2 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
index 05cefa7c8..05cefa7c8 100644
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
diff --git a/src/mem/protocol/MOESI_CMP_token.slicc b/src/mem/ruby/protocol/MOESI_CMP_token.slicc
index 5bc3a5700..5bc3a5700 100644
--- a/src/mem/protocol/MOESI_CMP_token.slicc
+++ b/src/mem/ruby/protocol/MOESI_CMP_token.slicc
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
index 66e1676d5..66e1676d5 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
index 42522c727..42522c727 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/ruby/protocol/MOESI_hammer-dma.sm
index 6a4c5ace4..6a4c5ace4 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dma.sm
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/ruby/protocol/MOESI_hammer-msg.sm
index 326290386..326290386 100644
--- a/src/mem/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-msg.sm
diff --git a/src/mem/protocol/MOESI_hammer.slicc b/src/mem/ruby/protocol/MOESI_hammer.slicc
index ab8eb730a..ab8eb730a 100644
--- a/src/mem/protocol/MOESI_hammer.slicc
+++ b/src/mem/ruby/protocol/MOESI_hammer.slicc
diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
index c6b30edf5..c6b30edf5 100644
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm
+++ b/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/ruby/protocol/RubySlicc_Defines.sm
index eb235f8f3..eb235f8f3 100644
--- a/src/mem/protocol/RubySlicc_Defines.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Defines.sm
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 8e17f9849..8e17f9849 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
index f211789be..f211789be 100644
--- a/src/mem/protocol/RubySlicc_MemControl.sm
+++ b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 28fb6ef00..28fb6ef00 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/ruby/protocol/RubySlicc_Util.sm
index 848f8c2c9..848f8c2c9 100644
--- a/src/mem/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
diff --git a/src/mem/protocol/RubySlicc_interfaces.slicc b/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
index f5a2b632d..f5a2b632d 100644
--- a/src/mem/protocol/RubySlicc_interfaces.slicc
+++ b/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
diff --git a/src/mem/protocol/SConscript b/src/mem/ruby/protocol/SConscript
index e66c6b303..e5a6f6d1d 100644
--- a/src/mem/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -47,7 +47,7 @@ output_dir = Dir('.')
 html_dir = Dir('html')
 slicc_dir = Dir('../slicc')
 
-sys.path[1:1] = [ Dir('..').srcnode().abspath ]
+sys.path[1:1] = [ Dir('..').Dir('..').srcnode().abspath ]
 from slicc.parser import SLICC
 
 slicc_depends = []
diff --git a/src/mem/protocol/SConsopts b/src/mem/ruby/protocol/SConsopts
index 54cd4dbc0..54cd4dbc0 100644
--- a/src/mem/protocol/SConsopts
+++ b/src/mem/ruby/protocol/SConsopts
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index f0e950030..c943c75d0 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -36,8 +36,8 @@
 #include <iostream>
 
 #include "base/logging.hh"
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 
 class DataBlock;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index c953e8257..cc1ac26ec 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -41,8 +41,8 @@
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 
 #include "debug/RubyQueue.hh"
-#include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/network/Network.hh"
+#include "mem/ruby/protocol/MemoryMsg.hh"
 #include "mem/ruby/system/GPUCoalescer.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/ruby/system/Sequencer.hh"
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 8888bd0a7..2007026e7 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -48,7 +48,6 @@
 #include "base/addr_range.hh"
 #include "base/callback.hh"
 #include "mem/packet.hh"
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/qport.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
@@ -56,6 +55,7 @@
 #include "mem/ruby/common/Histogram.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/system/CacheRecorder.hh"
 #include "params/RubyController.hh"
 #include "sim/clocked_object.hh"
diff --git a/src/mem/ruby/slicc_interface/AbstractEntry.hh b/src/mem/ruby/slicc_interface/AbstractEntry.hh
index 2cf1c4b5b..a75055f5e 100644
--- a/src/mem/ruby/slicc_interface/AbstractEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractEntry.hh
@@ -31,7 +31,7 @@
 
 #include <iostream>
 
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 
 class AbstractEntry
 {
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
index c62b4e123..0c2e0aa42 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -34,8 +34,8 @@
 #include <stack>
 
 #include "mem/packet.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 
 class Message;
 typedef std::shared_ptr<Message> MsgPtr;
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 6c84f3823..f6b25bf9a 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -32,15 +32,15 @@
 #include <ostream>
 #include <vector>
 
-#include "mem/protocol/HSAScope.hh"
-#include "mem/protocol/HSASegment.hh"
-#include "mem/protocol/Message.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/WriteMask.hh"
+#include "mem/ruby/protocol/HSAScope.hh"
+#include "mem/ruby/protocol/HSASegment.hh"
+#include "mem/ruby/protocol/Message.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class RubyRequest : public Message
 {
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index dfc2c73fc..a48405d69 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -29,10 +29,10 @@
 #ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 #define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 
-#include "mem/protocol/MachineType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/MachineType.hh"
 #include "mem/ruby/structures/DirectoryMemory.hh"
 
 inline NetDest
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 6c93c3260..5dc346388 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -35,7 +35,7 @@
 #include "debug/RubyCacheTrace.hh"
 #include "debug/RubyResourceStalls.hh"
 #include "debug/RubyStats.hh"
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/ruby/system/WeightedLRUPolicy.hh"
 
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 5b30505d3..16339ee55 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -35,10 +35,10 @@
 #include <vector>
 
 #include "base/statistics.hh"
-#include "mem/protocol/CacheRequestType.hh"
-#include "mem/protocol/CacheResourceType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/DataBlock.hh"
+#include "mem/ruby/protocol/CacheRequestType.hh"
+#include "mem/ruby/protocol/CacheResourceType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/structures/AbstractReplacementPolicy.hh"
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh b/src/mem/ruby/structures/DirectoryMemory.hh
index 36defd5e9..bbed4f975 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -45,8 +45,8 @@
 #include <string>
 
 #include "base/addr_range.hh"
-#include "mem/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 #include "params/RubyDirectoryMemory.hh"
 #include "sim/sim_object.hh"
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 61d5e1244..363e3e8f1 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -31,8 +31,8 @@
 
 #include <unordered_map>
 
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 
 template<class ENTRY>
 struct PerfectCacheLineState
diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh
index e5296d1e8..bc1d79e9d 100644
--- a/src/mem/ruby/structures/PersistentTable.hh
+++ b/src/mem/ruby/structures/PersistentTable.hh
@@ -32,10 +32,10 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/AccessType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/AccessType.hh"
 
 class PersistentTableEntry
 {
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index 7748b4ceb..53ab8e557 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -38,10 +38,10 @@
 #include <vector>
 
 #include "base/types.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/TypeDefines.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class Sequencer;
 
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 0ad8a205d..bad49c97d 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -32,8 +32,8 @@
 
 #include "debug/RubyDma.hh"
 #include "debug/RubyStats.hh"
-#include "mem/protocol/SequencerMsg.hh"
-#include "mem/protocol/SequencerRequestType.hh"
+#include "mem/ruby/protocol/SequencerMsg.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 9f1f4e503..a3ee8afa7 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -33,9 +33,9 @@
 #include <ostream>
 #include <unordered_map>
 
-#include "mem/protocol/DMASequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
+#include "mem/ruby/protocol/DMASequencerRequestType.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "params/DMASequencer.hh"
 
diff --git a/src/mem/ruby/system/GPUCoalescer.hh b/src/mem/ruby/system/GPUCoalescer.hh
index 6e40238c1..56f81c6ea 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -40,15 +40,15 @@
 #include <unordered_map>
 
 #include "base/statistics.hh"
-#include "mem/protocol/HSAScope.hh"
-#include "mem/protocol/HSASegment.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
-#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/request.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/HSAScope.hh"
+#include "mem/ruby/protocol/HSASegment.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/system/Sequencer.hh"
 
 class DataBlock;
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ff3bbe8f0..800046e10 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -45,7 +45,7 @@
 #include "debug/Config.hh"
 #include "debug/Drain.hh"
 #include "debug/Ruby.hh"
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/simple_mem.hh"
 #include "sim/full_system.hh"
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 20bc03a07..b57828d58 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -45,9 +45,9 @@
 #include <cassert>
 #include <string>
 
-#include "mem/protocol/RequestStatus.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
+#include "mem/ruby/protocol/RequestStatus.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/tport.hh"
 #include "params/RubyPort.hh"
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index ba67311c7..9d317aaa0 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -37,9 +37,9 @@
 #include "debug/RubySequencer.hh"
 #include "debug/RubyStats.hh"
 #include "mem/packet.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
 #include "mem/ruby/slicc_interface/RubyRequest.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "sim/system.hh"
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index fcfa8ad86..33fd53064 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -32,10 +32,10 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/MachineType.hh"
-#include "mem/protocol/RubyRequestType.hh"
-#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/MachineType.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/structures/CacheMemory.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "params/RubySequencer.hh"
diff --git a/src/mem/ruby/system/VIPERCoalescer.hh b/src/mem/ruby/system/VIPERCoalescer.hh
index 0727ea7e6..3f3597855 100644
--- a/src/mem/ruby/system/VIPERCoalescer.hh
+++ b/src/mem/ruby/system/VIPERCoalescer.hh
@@ -38,11 +38,11 @@
 
 #include <iostream>
 
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 #include "mem/ruby/system/GPUCoalescer.hh"
 #include "mem/ruby/system/RubyPort.hh"
 
diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py
index f2a47510f..f7f04946d 100644
--- a/src/mem/slicc/main.py
+++ b/src/mem/slicc/main.py
@@ -90,7 +90,8 @@ def main(args=None):
     output("SLICC v0.4")
     output("Parsing...")
 
-    protocol_base = os.path.join(os.path.dirname(__file__), '..', 'protocol')
+    protocol_base = os.path.join(os.path.dirname(__file__),
+                                 '..', 'ruby', 'protocol')
     slicc = SLICC(slicc_file, protocol_base, verbose=True, debug=opts.debug,
                   traceback=opts.tb)
 
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 03e624b11..a92e078e2 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -230,7 +230,7 @@ from m5.objects.Controller import RubyController
 
 class $py_ident(RubyController):
     type = '$py_ident'
-    cxx_header = 'mem/protocol/${c_ident}.hh'
+    cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
 ''')
         code.indent()
         for param in self.config_parameters:
@@ -272,9 +272,9 @@ class $py_ident(RubyController):
 #include <sstream>
 #include <string>
 
-#include "mem/protocol/TransitionResult.hh"
-#include "mem/protocol/Types.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/TransitionResult.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "params/$c_ident.hh"
 
@@ -283,7 +283,7 @@ class $py_ident(RubyController):
         seen_types = set()
         for var in self.objects:
             if var.type.ident not in seen_types and not var.type.isPrimitive:
-                code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{var.type.c_ident}}.hh"')
                 seen_types.add(var.type.ident)
 
         # for adding information to the protocol debug trace
@@ -459,18 +459,18 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
 #include <typeinfo>
 
 #include "base/compiler.hh"
-#include "mem/ruby/common/BoolVec.hh"
 #include "base/cprintf.hh"
+#include "mem/ruby/common/BoolVec.hh"
 
 ''')
         for f in self.debug_flags:
             code('#include "debug/${{f}}.hh"')
         code('''
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
-#include "mem/protocol/Types.hh"
 #include "mem/ruby/network/Network.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 ''')
@@ -486,7 +486,7 @@ using namespace std;
         seen_types = set()
         for var in self.objects:
             if var.type.ident not in seen_types and not var.type.isPrimitive:
-                code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{var.type.c_ident}}.hh"')
             seen_types.add(var.type.ident)
 
         num_in_ports = len(self.in_ports)
@@ -1057,17 +1057,17 @@ $c_ident::functionalWriteBuffers(PacketPtr& pkt)
         for f in self.debug_flags:
             code('#include "debug/${{f}}.hh"')
         code('''
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
 
 ''')
 
         if outputRequest_types:
-            code('''#include "mem/protocol/${ident}_RequestType.hh"''')
+            code('''#include "mem/ruby/protocol/${ident}_RequestType.hh"''')
 
         code('''
-#include "mem/protocol/Types.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 ''')
@@ -1172,10 +1172,10 @@ ${ident}_Controller::wakeup()
 #include "base/trace.hh"
 #include "debug/ProtocolTrace.hh"
 #include "debug/RubyGenerated.hh"
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
-#include "mem/protocol/Types.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 #define HASH_FUN(state, event)  ((int(state)*${ident}_Event_NUM)+int(event))
diff --git a/src/mem/slicc/symbols/SymbolTable.py b/src/mem/slicc/symbols/SymbolTable.py
index e991fec2b..e4fc0a3fb 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -133,7 +133,7 @@ class SymbolTable(object):
 
         for symbol in self.sym_vec:
             if isinstance(symbol, Type) and not symbol.isPrimitive:
-                code('#include "mem/protocol/${{symbol.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{symbol.c_ident}}.hh"')
 
         code.write(path, "Types.hh")
 
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index e9ea61815..c4d8eae06 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -201,15 +201,16 @@ class Type(Symbol):
 #include <iostream>
 
 #include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
+
 ''')
 
         for dm in self.data_members.values():
             if not dm.type.isPrimitive:
-                code('#include "mem/protocol/$0.hh"', dm.type.c_ident)
+                code('#include "mem/ruby/protocol/$0.hh"', dm.type.c_ident)
 
         parent = ""
         if "interface" in self:
-            code('#include "mem/protocol/$0.hh"', self["interface"])
+            code('#include "mem/ruby/protocol/$0.hh"', self["interface"])
             parent = " :  public %s" % self["interface"]
 
         code('''
@@ -404,7 +405,7 @@ operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
 #include <iostream>
 #include <memory>
 
-#include "mem/protocol/${{self.c_ident}}.hh"
+#include "mem/ruby/protocol/${{self.c_ident}}.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 using namespace std;
@@ -456,7 +457,7 @@ out << "${{dm.ident}} = " << printAddress(m_${{dm.ident}}) << " ";''')
 
 ''')
         if self.isStateDecl:
-            code('#include "mem/protocol/AccessPermission.hh"')
+            code('#include "mem/ruby/protocol/AccessPermission.hh"')
 
         if self.isMachineType:
             code('#include <functional>')
@@ -558,7 +559,7 @@ std::ostream& operator<<(std::ostream& out, const ${{self.c_ident}}& obj);
 #include <string>
 
 #include "base/logging.hh"
-#include "mem/protocol/${{self.c_ident}}.hh"
+#include "mem/ruby/protocol/${{self.c_ident}}.hh"
 
 using namespace std;
 
@@ -588,7 +589,8 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
         if self.isMachineType:
             for enum in self.enums.itervalues():
                 if enum.primary:
-                    code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
+                    code('#include "mem/ruby/protocol/${{enum.ident}}'
+                            '_Controller.hh"')
             code('#include "mem/ruby/common/MachineID.hh"')
 
         code('''